KR930007983B1 - Middle tone picture processing system for fax - Google Patents

Abstract

The system for converting half-tone image into high tone image without replacing half-tone output sole purpose DIPP (Document Image Pre-processor) comprises: a CPU (145) for generating line sync. and page sync. signal, and controlling high tone picture data generation; a DIPP (155) for inputting analog CCD (150) picture signal, and outputting a filtered analog picture signal (IOUT), a shape compensated shading signal (DAO), an absolute voltage level of the black intensity and a clock signal (T/RCLK); a half tone to high tone converting unit (160) for generating binary high tone picture data from IOUT signal by using VBL and DAO control signal.

Description

High Tone Halftone Image Processing System Using Image Processor

1 is a block diagram of a conventional halftone image cj retrieval system.

2 is a block diagram of a high gradation halftone image processing system according to the present invention;

3 is a detailed block diagram of a high gradation intermediate processing part of FIG.

4 is an exemplary diagram of a 64 gradation pattern matrix according to the present invention.

5 is a control flowchart according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a half tone image processing system of an image processing system. In particular, a high tone halftone for converting and outputting a halftone image signal processed with a tone of a predetermined state into high tone halftone image data of more than a predetermined tone An image processing system.

A general image processing system has a gradation processing circuit to realize contrast density processing. For example, a facsimile system, an image scanner system, an image transmission system, a display system, and the like have a gradation processing circuit for dividing a state of light and shade in an input image into a predetermined density division. Such a gradation image processing method is described on pages 31 to 54 of "Basic of image processing" published on October 25, 1990 by "Jung Iksa" which is a domestic book publisher.

1 is a block diagram of a conventional half-tone image processing system, which is an example of using an image preprocessor. 100 in FIG. 1 shows system control as a central processing unit (CPU).

120 denotes a Document Image Pro-Processor (DIPP), which performs shading correction and enlargement and reduction processing of the input image signal and 16-tone halftone processing of the input image signal.

140 is a charge coupled device (CCD) that scans a document and an image, converts the document and the image into an electrical signal, and provides an analog image signal to the DIPP 120.

A 16 gradation halftone processing operation procedure in the conventional circuit as shown in the first diagram will be described.

When the CPU 100 outputs the halftone control signal and the DIPP drive control signal for halftone processing, the DIPP 120 is driven by the drive control signal of the CPU 100 to control the CCD 140. At this time, the CCD 140 scans the document image of the document under the control of the DIPP 120, converts the image into an electrical signal, and inputs the image to the DIPP 120.

The DIPP 120 reads the analog image signal output from the CCD 140, and processes the read image signal therein with 16 gradation halftones therein to output binarized halftone data. At this time, the DlPP 120 corrects the shading of the input image signal to perform gradation processing. However, the conventional multi-gradation halftone processing system configured as described in the first diagram above has not obtained high-gradation halftone image data of 16 or more gradations by processing an image signal using a DIPP chip that processes only specific gradations, for example, 16 gradations.

Therefore, the conventional circuit using DIPP which processed only the halftone image data of a specific gray scale could not be used in a system requiring high grayscale halftone image data of a specific gray level or more.

Accordingly, an object of the present invention is to provide a system for generating and outputting high gray level halftone image data of a predetermined gray level or more using DIPP which performs a halftone image processing of a predetermined gray level.

Another object of the present invention is to provide a high gradation intermediate processing unit for outputting high gradation halftone image data by inputting an absolute black potential value, a shading waveform output, and an analog image signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a high gradation halftone processing system according to the present invention, and outputs a high gradation halftone processing control signal, and includes line sync and page sync according to the input of a one-line processing completion signal. A CPU 145 which outputs a signal to control the generation of high gradation halftone image data, a CCD 150 which scans a document according to a scan control signal to convert an image of the document into an electrical signal, and outputs the same; 145 is connected between the CCD 150 and the CCD 150 to drive the CCD 150 in response to the halftone processing control signal and the driving control signal, and receives an analog image signal, corrects the shading waveform, and simultaneously smoothes the waveform. DIPP 155 which outputs the corrected shading signal DAO, smoothed analog image signal UOUT, absolute hull potential VBL, clock T / RCLK, and absolute black output from the DIPP 155 Potential value (VBL) and waveform The smoothed analog image signal IOUT is encoded as digital image data of high gradation based on the corrected shading signal DA0, and output as high gradation halftone image data which is substituted by the control of the CPU 145. It is composed of a high gradation halftone processing unit 160.

In the configuration description of FIG. 2, Line Sync is a signal indicating the start and end of one scan line of a document, and Page Sync is a signal indicating the start and end of one page of a document. ) Is output from the output port of).

First, the operation of the same configuration as the second diagram will be briefly described.

When the CPU 145 now gives the driving start signal of the DIPP 155 to the DIPP 155, the DIPP 155 drives the CCD 150 to read a document image. The analog image signal read from the CCD 150 is smoothed by the DIPP 155 and then input to the high gradation halftone processing unit 160. In this case, the high gray scale processing unit 160 performs a shading waveform DAO, an absolute black potential value VBL, and a clock T / outputted from the input analog image signals lOUT and DIPP 155. RCLK) is processed to process the high tone halftone and then outputs the high tone halftone image data.

FIG. 3 is a detailed view of the high gray scale intermediate processing unit 160 according to the present invention, and the analog corrected shading signal DAO outputted from the DIPP 155 and the absolute black level value VBL are smoothed. The image signal IOUT is input, and only the smoothed analog image signal IOUT between the shading signal DAO and the absolute black level value VBL is encoded into digital image data by the input clock T / RCLK. An analog to digital converter (ADC) 180 to output, a clock (T / RCLK) output from the DIPP 155, a line sync output from the CPU 145, and a page sync. The pattern address generator 200 which inputs (Page Sync) to generate a halftone pattern address, and halftone data are stored in a predetermined address area, and the address is generated from the pattern address generator 200 and inputted to an address inputted therein. Memo to output halftone pattern data And a comparator 240 for comparing the level of the image data output from the ADC 180 with the level of the halftone data output from the memory 220 and outputting binarized high gray level halftone image data. It is composed.

In the configuration of FIG. 3, the pattern address generator 200 is cleared by an input of the line sync, and the clock T / RCLK counts an input to access pattern data of one line. A first counter 202 for generating a column address CA and a row address RA for counting the line sync and specifying a next line until a page sync is input; It consists of two counters 204.

4 illustrates an example of a 64 gradation halftone pattern matrix using pattern data stored in a predetermined address area of the memory of FIG. 3.

5 is an operation flowchart of the CPU 145 of FIG.

An operation example of FIGS. 2 and 3 according to the present invention will now be described in detail with reference to FIG.

If the CPU 145 now outputs the DIPP drive start signal in Fig. 5, the DIPP 155 is driven. At this time, the DIPP 155 drives the CCD 150 to read an image of the document. The DIPP 155 reads an analog image signal through the CCD 150. The DIPP 155, which reads the analog image signal through the CCD 150, smoothes the input analog image signal FMF and simultaneously corrects the shading waveform to correct the waveform corrected shading signal DAO and the smoothed image signal IOUT. Output The DIPP 155 inputs the absolute black level sense VBL, which is a processing reference of the analog image signal, and the clock T / RCLK of a predetermined period to the high gradation intermediate processor 160.

In this case, the corrected shading signal DAO is a signal for correcting the sensitivity unevenness of the CCD 150 due to the positive difference between the light of the center portion and the side portion of the document irradiation light source. The absolute black level value VBL is a level which becomes a processing reference of an analog image signal and is a voltage for determining the absolute black level.

The ADC 180 inputs the signals output from the DIPP 155 and inputs the smoothed analog image signal IOUT based on the input correction shading signal DAO and the absolute black potential value VBL. (T / RCLK) converts and outputs to 64 gradations of digital image data. That is, the ADC 180 converts the analog image signal IOUT between the corrected shading signal DAO and the absolute black level value VBL into 6-bit digital data and outputs the digital image data SNTD. Encoded image data output from the ADC 180 is input to the comparator 240 and compared to the halftone pattern value generated in the memory 200, which is a halftone pattern generator that generates a halftone pattern. It is output as crude image data. The pattern address generator 200 for generating the halftone pattern value from the memory 220 which is the pattern generator controls the address so that the halftone pattern value is repeatedly generated repeatedly. The pattern address generator is composed of a first counter 202 and a second counter 204 as described above.

Referring to the operation of the first and second counters 202 and 204 using the 64 gradation halftone process as an example, the first line of the 64 gradation halftone pattern matrix stored in the memory 220 shown in FIG. When the eight pattern values of the first row are repeatedly addressed by the first counter 202, the first counter 202 is cleared by a line sync signal output from the CPU 145, and the second counter is cleared. 204 is operated to output the pattern data from the memory 220 by addressing the second line, that is, the second line. In this case, when the next line sync signal is input, the first counter 202 repeats sequentially the eight pattern values of the second row until all the lines are processed. In this manner, when the addressing of the halftone pattern values of the eighth row is completed, the first and second counters 202 and 204 are cleared, and addressing starts from the first halftone pattern of the first row. The addressing of the counter is repeated until the page sync signal clears the second counter 204 to stop the operation of the address generator.

Next, the operation of the comparator 240 during the 64 gradation halftone processing will be described in detail. The analog image signal read by the CCD 150 is digitalized by the ADC 180 into 64 gradation image data and is converted into 6 bits (Bit). When encoded image data is input to the comparator 240, the address generator 200 is compared with the halftone pattern generated in the memory 220. "1" is output, and vice versa, "0" is output.

Accordingly, the present invention digitally converts the smoothed analog image signal output from the DIPP 155 into 64 bit data of 6 bits, and outputs 64 gray level image data by comparing with 64 gray pattern data generated from the memory. It can be seen.

In the present invention, the digital image data of 64 gradations is generated using the shading-corrected analog image signal, the waveform-corrected shading signal, and the absolute black level signal using DIPP. Note that the device may be used.

In the exemplary embodiment of the present invention, an example of 64 gradation halftone processing using a 6-bit ADC and 64 gradation pattern memory is described. The processing can be facilitated.

As described above, the present invention can obtain high-gradation halftone image data of 16 or more gradations using the conventional DIPP as it is in the image processing system, thereby realizing high image quality.

Claims (3)

In a high gradation halftone image processing system using an image processor, a high gradation halftone processing control signal is output, and a line sync and page sync signals are output according to the input of a single line processing completion signal to generate high gradation halftone image data. Is connected between the CPU 145 and the CCD 150, a CPU 145 for controlling the operation, a CCD 150 for scanning a document by a scan control signal, and converting and outputting an image of the document into an electrical signal. The CCD 150 is driven in response to a halftone processing control signal and a driving control signal, and receives an analog image signal input thereto, corrects a shading waveform, and simultaneously smoothes the shading signal DAO and a smoothed analog image. DIPP 155 for outputting signal IOUT, absolute black potential value VBL, clock T / RCLK, absolute black potential value VBL and waveform corrected shading scene output from DIPP 155 A high gradation medium that encodes the smoothed analog image signal IOUT as high gradation digital image data on the basis of (DAO) and outputs it as binarized high gradation halftone image data under the control of the CPU 145. A high gradation halftone image processing system using an image processor, characterized by comprising a roughness processor 160. 2. The high gradation intermediate processing section 16 according to claim 1, wherein the high gray level intermediate processing section 16 outputs the waveform-corrected shading signal DAO outputted from the DIPP 155, the absolute black level value VBL, and the analog image signal IOUT smoothed. An ADC 180 that encodes and outputs only the smoothed analog image signal IOUT between the shading signal DAO and the absolute black level value VBL by the input clock T / RCLK as digital image data. ), A clock (T / RCLK) output from the DIPP 155, a line sink output from the CPU 145, and a pattern address generator 200 for generating a halftone pattern address by inputting a page sink. ), A memory 220 for storing halftone data in an address area, and outputting halftone pattern data according to an address generated and input from the pattern address generator 200, and the ADC 180. Image data and memory output from And a comparator (240) for comparing the level of the halftone data output from 220 to output binarized high-grayscale halftone image data. The method of claim 2, wherein the pattern address generator 200 is cleared by the input of the line sink and counts an input of the clock T / RCLK to generate an open dress CA for accessing one line of pattern data. The first counter 202 and a row address RA which counts the line sink and designates the next line are configured as a second counter 204 which is generated until a page sink is input. High gradation halftone image processing system.