KR930005398U - Parallel port communication system - Google Patents
Parallel port communication systemInfo
- Publication number
- KR930005398U KR930005398U KR2019910012551U KR910012551U KR930005398U KR 930005398 U KR930005398 U KR 930005398U KR 2019910012551 U KR2019910012551 U KR 2019910012551U KR 910012551 U KR910012551 U KR 910012551U KR 930005398 U KR930005398 U KR 930005398U
- Authority
- KR
- South Korea
- Prior art keywords
- communication system
- parallel port
- port communication
- parallel
- port
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910012551U KR950008788Y1 (en) | 1991-08-07 | 1991-08-07 | Parallel port communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910012551U KR950008788Y1 (en) | 1991-08-07 | 1991-08-07 | Parallel port communication system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930005398U true KR930005398U (en) | 1993-03-22 |
KR950008788Y1 KR950008788Y1 (en) | 1995-10-14 |
Family
ID=19317649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019910012551U KR950008788Y1 (en) | 1991-08-07 | 1991-08-07 | Parallel port communication system |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950008788Y1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7127631B2 (en) | 2002-03-28 | 2006-10-24 | Advanced Analogic Technologies, Inc. | Single wire serial interface utilizing count of encoded clock pulses with reset |
-
1991
- 1991-08-07 KR KR2019910012551U patent/KR950008788Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950008788Y1 (en) | 1995-10-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20010927 Year of fee payment: 7 |
|
LAPS | Lapse due to unpaid annual fee |