KR930004301B1 - Making method of transistor of short channel effect structure - Google Patents
Making method of transistor of short channel effect structure Download PDFInfo
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- KR930004301B1 KR930004301B1 KR1019900020953A KR900020953A KR930004301B1 KR 930004301 B1 KR930004301 B1 KR 930004301B1 KR 1019900020953 A KR1019900020953 A KR 1019900020953A KR 900020953 A KR900020953 A KR 900020953A KR 930004301 B1 KR930004301 B1 KR 930004301B1
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- South Korea
- Prior art keywords
- gate
- forming
- film
- photo
- oxide film
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000000694 effects Effects 0.000 title abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 125000006850 spacer group Chemical group 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims abstract 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제1도는 종래의 구조 단면도.1 is a cross-sectional view of a conventional structure.
제2도는 본 발명의 제조 공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 베어 웨이퍼 2 : 산화 규소막1: bare wafer 2: silicon oxide film
3 : P형 에피층 4, 5, 8 : 산화막3: P type epi layer 4, 5, 8: oxide film
6 : 폴리 실리콘막 7 : 실리사이드막6: polysilicon film 7: silicide film
본 발명이 소이(S.O.I) 구조의 트랜지스터 제조방법에 관한 것으로, 특히 소자들이 고집적화되면서 게이트 효과길이(Gate Effective Length)가 짧아 짐에 따른 쇼트 채널 효과(Short Channel Effect)의 발생을 방지하도록 한 것이다.The present invention relates to a transistor manufacturing method of a soy (S.O.I) structure, in particular to prevent the occurrence of a short channel effect (short channel effect) as the gate effective length (Gate Effective Length) is shortened as the devices are highly integrated.
종래의 소이(S.O.I : Slicon On Insulator) 구조의 트랜지스터는 제1도에 나타낸 바와 같이 게이트 부분이 기판과 평행한 구조로 제조되었다. 이것의 제조공정은 먼저 P형 실리콘 기판(20)위에 산화규소막(21)과 P형 에피(Epi)층 (22)을 차례로 형성한 후 P형 에피층(22)위에 이방성 에치(Anisotropic Etch)를 설시하여 소정갯수의 아일랜드(Island)(23)를 형성한다.In the conventional S.O.I (Slicon On Insulator) transistor, as shown in FIG. 1, the gate portion is manufactured in a structure parallel to the substrate. Its manufacturing process first forms a silicon oxide film 21 and a P-type epi layer 22 on the P-type silicon substrate 20 in turn, and then anisotropic etching on the P-type epi layer 22. To form a predetermined number of islands 23.
이어 아일랜드(23)와 아일랜드(23) 사이의 트렌치(Trench)에 LOCOS(Local Oxidation of Silicon) 공정을 실시하여 필드산화막(24)을 형성하고 각 아일 랜드(23) 중앙부위에 게이트 산화규소막(25)과 게이트 폴리실리콘막(26)을 차례로 형성한다.Subsequently, a LOCOS (Local Oxidation of Silicon) process is performed in the trench between the island 23 and the island 23 to form a field oxide layer 24, and a gate silicon oxide layer is formed at the central portion of each island 23. 25 and the gate polysilicon film 26 are formed in this order.
이어 소오스/드레인용 n+이온주입 및 p+이온주입용 마스크 공정과 이온주입공정을 차례로 실시하여 각 게이트 양측밑에 소오스/드레인 접합을 형성한다.Subsequently, a source / drain junction for n + ion implantation, a p + ion implantation mask process, and an ion implantation process are sequentially performed to form a source / drain junction under both gates.
이와 같이 제조되어지는 트랜지스터는 각 게이트에 문턱전압(Threshold Vol tage) 이상이 인가되면 소오스와 드레인사이에 채널이 형성되어 전류가 흐르게 된다.In the transistor manufactured as described above, when a threshold voltage or more is applied to each gate, a channel is formed between the source and the drain so that current flows.
그러나 상기 종래 기술은 다음과 같은 단점이 있었다.However, the prior art has the following disadvantages.
소이구조의 트랜지스터가 고집적화 될수록 게이트길이가 줄어들게 된다. 반면에 게이트의 길이는 쇼트 채널 효과가 발생되지 않을 정도의 최소길이를 유지해야 하나 종래 제조기술로는 고집적화에 따른 게이트의 최소길이를 유지하는데 한계가 있었다.As the transistor structure of the soy structure becomes more integrated, the gate length decreases. On the other hand, the gate length should maintain a minimum length such that a short channel effect does not occur, but the conventional manufacturing technique has a limitation in maintaining the minimum length of the gate due to high integration.
본 발명은 상기 단점을 제거키 위한 것으로 이를 첨부된 제2(a)도 내지 제2(g)도를 참조하여 상술하면 다음과 같다.The present invention is to eliminate the above disadvantages and will be described below with reference to the second (a) to 2 (g) attached to it as follows.
먼저 제2(a)도와 같이 베어 웨이퍼(Bare Wafer)(1)를 산화시켜 산화규소막(2)을 성장시키고 이에 P형 에피층(3)을 성장시킨다. 이어 제2(b)도와 같이 포토/에치 공정을 실시하여 상기 P형 에피층(3)에 소정갯수의 트렌치를 형성한다. 그리고 제2(c)도와 같이 트렌치 부위에 산화를 행한다음 제2(d)도와 같이 마스킹용 산화막(4)을 증착한다.First, as shown in FIG. 2 (a), the bare wafer 1 is oxidized to grow the silicon oxide film 2, and thus the P-type epitaxial layer 3 is grown. Next, a photo / etch process is performed as shown in FIG. 2 (b) to form a predetermined number of trenches in the P-type epi layer 3. Then, oxidation is performed in the trench portion as shown in FIG. 2 (c), and the masking oxide film 4 is deposited as shown in FIG. 2 (d).
이어 감광제를 코팅하여 게이트 형성을 위한 에치부위를 한정한 다음 이방성 에치를 실시하여 게이트가 형성될 P형 에피층부위가 경사지도록 한다.Subsequently, the photoresist is coated to define an etched portion for forming the gate, and then anisotropic etching is performed to incline the P-type epilayer portion to be formed with the gate.
이에 제2(e)도와 같이 상기 마스킹용 산화막(4)을 에치하여 제거하고 게이트용 산화막(5)과 게이트용 폴리실리콘막(6)과 실리사이드(Silicide) 막(7)을 차례로 증착한 다음 제2(f)도와 같이 감광제를 이용하여 게이트 영역을 한정하고 게이트이외의 부분의 산화막(5)과 폴리실리콘막(6) 및 실리사이드(Silicide) 막(7)은 에치하여 제거한다.As shown in FIG. 2 (e), the masking oxide film 4 is etched and removed, and the gate oxide film 5, the gate polysilicon film 6, and the silicide film 7 are sequentially deposited. As shown in FIG. 2 (f), the gate region is defined using a photosensitive agent, and the oxide film 5, the polysilicon film 6, and the silicide film 7 in portions other than the gate are etched and removed.
그리고 n-및 p-마스킹 공정을 거쳐 소오스/드레인 접합용 n-및 p-이온 주입을 실시한다.Then, n - and p - ion implants for source / drain junctions are performed through an n - and p - masking process.
이에 제2(g)도와 같이 LTO(Low Temperature Oxide) 막을 성장시키고 이를 에치하여 측벽 스페이서(8)를 형성한 다음 소오스/드레인 접합용 n+및 p+이온 주입을 실시하여 LDD(Lightly Doped Drain) 구조를 형성한다.As shown in FIG. 2 (g), a low temperature oxide (LTO) film is grown and etched to form sidewall spacers 8, and then n + and p + ion implantation for source / drain junctions are performed to perform lightly doped drain (LDD). To form a structure.
상기와 같이 제조되어지는 모스 메모리(Mos Memory) 소자의 동작은 종래의 모스 메모리 소자의 동작과 동일하다.The operation of the MOS memory device manufactured as described above is the same as that of the conventional MOS memory device.
그러나 기존 메모리 소자에서 사용된 P형 또는 N형 기판대신 산화규소막을 사용하므로써 동작중 누설전류(Leakage Carrent)가 발생되지 않게 된다.However, by using a silicon oxide film instead of the P-type or N-type substrate used in the conventional memory device, leakage current during operation is not generated.
이상과 같이 본 발명에 의하면 다음과 같은 효과가 있다.As described above, the present invention has the following effects.
첫째, 게이트를 경사지게 형성하므로써 종래기술과 같이 평탄하게 게이트를 형성할 경우보다 게이트길이를 늘릴수 있다(게이트의 경사도가 약 55°인 경우, 1/cos 55°=1.8배).First, by forming the gate inclined, the gate length can be increased than in the case of forming the gate flatly as in the prior art (when the inclination of the gate is about 55 °, 1 / cos 55 ° = 1.8 times).
따라서 고집적화에 따라 게이트 효과길이가 작아지는 소자에 있어서 발생되는 쇼트 채널 효과를 방지할 수 있다.Therefore, it is possible to prevent the short channel effect generated in the device in which the gate effect length becomes small due to high integration.
둘째, 길이 0.5㎛ 이하의 게이트를 형성할때는 LDD효과까지도 얻을 수 있으므로 핫 전자(Hot Electron) 효과를 방지할 수 있다.Second, when forming a gate of 0.5 μm or less in length, the LDD effect can be obtained, thereby preventing the hot electron effect.
셋째, 소이구조로 형성되므로 씨모스(CMOS)의 단점인 래치-업(Latch-up)현상을 방지할 수 있다.Third, since it is formed of a soy structure, it is possible to prevent the latch-up phenomenon, which is a disadvantage of the CMOS.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900020953A KR930004301B1 (en) | 1990-12-18 | 1990-12-18 | Making method of transistor of short channel effect structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900020953A KR930004301B1 (en) | 1990-12-18 | 1990-12-18 | Making method of transistor of short channel effect structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920013700A KR920013700A (en) | 1992-07-29 |
| KR930004301B1 true KR930004301B1 (en) | 1993-05-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900020953A KR930004301B1 (en) | 1990-12-18 | 1990-12-18 | Making method of transistor of short channel effect structure |
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| KR (1) | KR930004301B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100304974B1 (en) * | 1993-03-11 | 2001-11-30 | 김영환 | Method for manufacturing mos transistor |
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1990
- 1990-12-18 KR KR1019900020953A patent/KR930004301B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR920013700A (en) | 1992-07-29 |
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