KR930000545B1 - Integrated circuit tester and remote pin electronics therefor - Google Patents

Abstract

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Description

[Name of invention]

Integrated circuit tester and pin-to-pin interface provider

[Brief Description of Drawings]

1 is a block diagram of an integrated circuit tester.

2 is a detailed block diagram of an integrated circuit tester portion that is in accordance with the principles of the present invention.

Detailed description of the invention

[Field of Invention]

BACKGROUND OF THE INVENTION The present invention relates generally to electronic devices for use in test heads of automated integrated circuit testers. In particular, the present invention relates to a low divice count circuit capable of positioning the application and measurement circuitry of an automated integrated circuit tester relatively remote from the test head.

[Background of invention]

In the fabrication of semiconductor integrated circuits, it is very important to test the circuits in various stages. Integrated circuits become more complex and require more pins to be interconnected to circuit boards and the like, further increasing the problems caused by the testing of the circuits.

A fundamental problem that arises in the testing of high pin count integrated circuits is the size of the test head required. Conventional automatic testers are provided with an application and measurement unit capable of measuring the response by applying a number of forces to each pin of the device being tested. In order to eliminate signal degradation and other problems, it is necessary to position the application and measurement unit as close to the pin under test as possible. Thus, considerable effort is required in the design of the accreditation and measurement unit, the tester is designed to test more pins and the physical size of the test head increases unhandily. All of these problems are further exacerbated by the rapid increase in conventional tester speed. The high switching speeds that result in the test heads cause problems with interference and signal quality, making the problems even worse.

[Summary of invention]

It is therefore an object of the present invention to provide an improved automated integrated circuit tester.

It is another object of the present invention to provide an improved electronic circuit for use in a test head of an automatic integrated circuit tester.

It is another object of the present invention to provide an improved electronic circuit for use in a test head of an automatic integrated circuit tester.

It is a further object of the present invention to provide a low device counting circuit which places the application and measurement unit of the automatic integrated circuit tester away from the test head.

The above and other objects and advantages are to provide an integrated circuit test with an application and measurement unit away from the test head. The switching device at the test head is close to the pin under test and provides high speed switching between multiple test conditions. One or more application circuits may be used to switch the signal on the line that couples the application circuit to the test head at a much lower speed than would appear on the pin under test.

The above objects and advantages of the present invention will be apparent to those skilled in the art by the following detailed description with reference to the drawings.

Detailed description of the invention

1 is a simple block diagram of a typical integrated circuit tester. Most tester components are installed in a cabinet 10. The components installed in the cabinet 10 include the basic control structure of the tester and other parts of the tester and interface devices to external computers. The tester architecture has been assigned to the assignee of the present invention and may be of the type described in co-pending US patent application SC-05099. Typically, one or more operator interface consoles 12 are provided to be coupled to the tester cabinet 10. Substantial testing is done in one or more test heads 14 coupled to the tester cabinet 10. Each test head 14 includes a socket 15 that is used to couple the device under test to a test electronic component. Other means, such as probes for providing such a bond, are also similar in the prior art.

In a high speed multi-pin integrated circuit tester, it is necessary to locate a relatively large portion of the application and measurement circuits to complete the test in the test circuit 14. This is necessary to avoid interference timing and other problems. In order to implement high-speed integrated circuit testing, it is necessary to accurately time the pulse edges, to accurately measure relatively small currents and voltages, and, above all, to quickly switch states. It is very difficult to achieve the goal on a long line. The most common solution is to shorten the line by bringing the application and measurement circuits close to the device pins under test. As the testing becomes more complex and the number of pins increases, the size of the test head 14 and hence the cost increases significantly.

2 is a detailed block diagram illustrating a particular embodiment of the present invention. In the present invention, the low device counting circuit 20 at the test head couples each pin 21 of the device under test to a force and measure (FAM) unit 22, which unit is from the test head. It is about 10 feet away. The circuit 20 is repeated for each pin 21 of the socket or probe at the test head. The remote FAM 22 may be located in the same enclosure as the remainder of the tester or may be located anywhere convenient. Typically, the remote FAM 22 is multiplied by the number of test heads at the multiplexer point 23. In a particular embodiment of the invention shown in FIG. 2, the remote FAM 22 can apply and measure current and voltage across two ranges of high and low ranges. A first pair of field effect transistors or FETs 25, 26 are used to switch between the high range application and measurement circuit and the low range application and measurement circuit. The gate of the FET 25 is connected to the switch high line from the remote FAM 22. The drain of the FET 25 is connected to the pin 21. The source of the FET 25 is connected to the high range application and measurement line 27. Technically similar, the gate of the FET controls the conductivity between the source and the drain. Thus, the remote FAM 22 can selectively couple and disconnect the high range application and measurement line 27 to the pin 21 via the FET 25. The gate of the FET 26 is connected to the switch low line from the remote FAM 22. The drain of the FET 26 is connected to the pin 21. The source of FET 26 is connected to the low range application and measurement line 28. Thus, the remote FAM 22 can be selectively coupled to and disconnected from the pin 21 via the low range application and measurement lines 28 and the FETs 26.

FETs 25 and 26 are used as high speed switches between high and low range application and measurement of remote FAM 22. The voltage gain available from the device switches the slow signal relatively quickly on lines 27 and 28. FETs 25 and 26, and each of the other FETs described below, are preferably very slow capacitance devices. This is because the capacitance limits the switching speed. In this regard, VMOS devices from multiple discrete semiconductor sources are available.

Second pairs 30 and 31 of FETs are used to control the coupling of the current application and measurement circuits with pin 21. The gate of the FET 30 is connected to the high current application line from the remote FAM 22. The drain of the FET 30 is connected to the high range application and measurement line 27. The source of the FET 30 is connected to the high range current application and measurement line 32. Thus, the remote FAM 22 can control the coupling of the low current application and measurement line 33 with the low range application and measurement line 28 via the high current application line and the FET 31.

Similarly, it is connected to the low current application line from the remote FAM 22 of the gate of the FET 31. The drain of the FET 31 is connected to the low range application and measurement line 28. Thus, the remote FAM 22 can control coupling the high current application and measurement line 33 with the high range application and measurement line 28 via the high current application line and the FET 30.

In addition to making it possible as a simple switch, the FETs 30 and 31 operate as a common gate impedance converter for current application. In other words, FETs 30 and 31 act as active devices rather than as saturation switches when current is applied. This causes lines 32 and 33 to appear high impedance in FETs 30 and 31, respectively, and low impedance in lines 27 and 28, respectively.

The third pair of FETs 35 and 36 is used to control the voltage application path. The gate of the FET 35 is connected to the high voltage application line of the remote FAM 22. The drain of the FET 35 is connected to the high range application and measurement line 27. The source of the FET 35 is connected to the high range voltage application line 37. Thus, via the high voltage application line and the FET 35, the remote FAM 22 can control coupling the high range voltage application line 37 with the high range application and measurement line 27.

The gate of the FET 36 is connected to the applied low voltage line from the remote FAM 22. The drain of the FET 36 is applied to the low range and is connected to the measurement line 28. The gate of the FET 36 is connected to the low range voltage potential line 38. Thus, via the low voltage application line and the FET 36, the remote FAM 22 can control coupling the low range application line 38 with the low range application and measurement line 28.

In addition to functioning as a switch, FETs 35 and 36 include parasitic diodes that act as voltage compliant clamps when applying current. Another function of the FETs 35 and 36 is to accelerate very low level current measurements. The measurement is slow due to the time required to charge the stray capacity between the pin and the measuring device at low current levels. When measuring current with the present invention, the appropriate FET 35 or 36 is simply challenged at the beginning of the test. This provides a low impedance path so that all of the capacity is charged very quickly, then the FET 35 or 36 is in a non-conductive state, where a practical measurement takes place.

Capacitor 40 is connected between high range voltage applying line 37 and ground to reduce the AC impedance of the line. Similarly, capacitor 41 is connected between low range voltage applying line 38 and ground.

A pair of coaxial cables 45 and 46 couple the high range and low range application and measurement circuits to the FET switch, respectively. Other transmission line devices, such as shielded ribbon cables, can be used in place of coaxial cables. The central conductor of the coaxial cable 45 is connected to the high range current application and measurement line 32 at one end and to the line 50 leading to the remote FAM 22 at the other end. The outer or shielded conductor of the coaxial cable 45 is connected to the high range voltage applying line 37 at one end and to the line 51 leading to the remote FAM 22 at the other end. Similarly, the center conductor of coaxial cable 46 is connected to the low range current application and measurement line 33 and to the line 52 that enters the remote FAM 22 at the other end. The outer or shielded conductor of the coaxial cable 46 is connected to the low range voltage applying line 38 at one end and to the line 53 leading to the remote FAM 22 at the other end.

The digital word corresponding to the analog current value applied to use the high range current application circuit is transferred from the other part of the tester to the digital to analog converter 55. Once converted, the analog value is transferred and applied to the high current circuit 56. The high current application circuit 56 is a programmable current source. The circuit 56 ″ applies ″ a current value characterized by the tester as received from the converter 55. The output of the high current application circuit 56 is connected to the line 50 and to the center conductor of the coaxial cable 45. As long as the FETs 25 and 30 are conductive, as determined by the switch high line and the high current application line, the current application condition characterized by the high current application circuit 56 is applied to the pin 21. In addition, the line 50 leading to the remote FAM 22 is also connected to the high current measurement circuit 57. The high current measurement circuit 57 also receives a reference input from the line 51, which is connected to an outer conductor of the coaxial cable 45. The output of the high current measuring circuit 57 is connected to the high current measuring circuit of the tester via a calibrator 58.

The voltage application state applied to the pin 21 via the high range application circuit is digitized and transferred to the digital / analog converter 60. Once converted, the analog signal is transmitted to the high voltage application circuit 61. Once converted, the analog signal is transmitted to the high voltage application circuit 61. The high voltage application circuit 61 is a programmable voltage source. The circuit 61 applies a specific voltage value. The output of the high voltage application circuit 61 is connected to the line 51 and to the outer conductor of the coaxial cable 45. When the FETs 25 and 35 are conductive, a voltage application state characterized by the high voltage application circuit 61 is applied to the pin 21.

The low range application and measurement circuit is parallel to the regulation circuit for the high range. The low range applied current state is connected to the digital / analog converter 65 and to the low current application circuit 66. The output of the low current application circuit 66 is connected to the line 52 and to the center conductor of the coaxial cable 46. Low range current measurement is implemented by low current measurement circuit 67, which receives inputs from lines 52 and 53 and passes the output through calibrator 68. FETs 26 and 31 must be conductive for low range current application and measurement.

The low range voltage application state is connected to the digital / analog converter 70 and to the low voltage application circuit 71. The output of the low voltage application circuit 71 is connected to the line 53 and to the outer conductor of the coaxial cable 46. FETs 26 and 36 must be conductive so that voltage is applied in the low range.

Voltage sensing at pin 21 is done by a follower amplifier 75 where one input is connected to pin 21 and the other input is connected to the output itself. The output of the voltage follower 75 is connected to the voltage measuring circuit of the remote FAM 22 via the center conductor of the coaxial cable 76. The outer conductor of the coaxial cable 76 is grounded.

A combination of multiple application and measurement units and the above-described circuits is provided for highway test of integrated circuits with inexpensive test heads. All switching is implemented by the line coupled to the gate of the low capacitance FET, reducing the importance of the line length. In addition, the ability to quickly measure low current levels is provided. In a suitable embodiment described above, the high range FET is of opposite channel type (P channel), while the low range FET is of opposite channel type (N channel). This is preferred, for example, by applying and measuring positive currents and voltages with high range circuits and negative currents and voltages with high range circuits and negative currents and voltages with low range circuits.

However, an automatic integrated circuit test improved by the present invention is provided. By using one or more application and measurement circuits on the unit pins, tests with high switching speeds are implemented. The application and measurement unit is removed from the test head and replaced by a row device counting circuit at each pin and provides high speed switching to compensate for long lines for the application and measurement unit. Thus, the price of the test head is reduced.

Claims (11)

Interface between the integrated circuit tester 10 consisting of current application means 56, 66, voltage application means 61, 71, current measurement means 57, 67 and voltage measurement means and pin 21 of the device under test In the apparatus for providing a first switch means (25, 26) for selectively coupling and disconnecting the integrated circuit tester to the pin, and the current applying means (55, 56) of the integrated circuit tester (25) Second switch means (30,31) for selectively coupling and disconnecting to the first switch means, and second switch means (30,31) for selectively coupling and disconnecting to the first switch means (35,36). Apparatus for providing an integrated circuit tester and pin-to-pin interface comprising a). The voltage section of the integrated circuit tester also includes a voltage measurement section, and couples the pin 21 to the voltage measurement means of the integrated circuit tester 10 separately from the first switch means 25, 26. Apparatus for providing an integrated circuit tester and pin-to-pin interface, further comprising means (75, 76) for. 2. The switch according to claim 1, wherein the first switch means (25, 26) is also a gate controlled by an integrated circuit tester, a drain coupled to the pin (21) and a second switch means (30, 31) and a third switch means And at least one field effect transistor having a source coupled to (35, 36). 4. The switch according to claim 3, wherein the second switch means (30, 31) are also gates controlled by an integrated circuit tester, drain and current application means (56, 66) coupled to the sources of the first switch means (25, 26). And at least one field effect transistor having a source coupled to the current measuring means (57, 67). 5. The third switch means (35, 36) further comprises a gate controlled by an integrated circuit tester (10), a drain and voltage application means (61) coupled to the source of the first switch means (25, 26). And 71) at least one field effect transistor having a source coupled to it. The pin 21 of the device under test and the integrated circuit provide an interface between the tester 10, the current applying means 55, 56, the voltage applying means 61, 71, the current measuring means 57, 67. And a voltage measuring means, comprising: at least one first field effect transistor switch 25 having a gate controlled by an integrated circuit tester 10, a drain coupled to pin 21, and a source 27. 26, a gate controlled by the integrated circuit tester 10, a drain coupled to the source of at least one first field effect transistor switch 25, 26, and coupled to a current application means 56, 66 At least one second field effect transistor switch 30, 31 with sources 32, 33, and a gate controlled by the integrated circuit tester 10, at least one first field effect transistor switch 25, 26. Drain (37,38) coupled to the drain and voltage applying means (61,71) And at least one third field effect transistor switch (35,36) having an integrated circuit tester and pin-to-pin interface providing device. Device according to claim 6, comprising means (75,76) for coupling pins (21) to the voltage measuring means of the integrated circuit tester (10). 7. A source according to claim 6, characterized in that the sources (32, 33) of the at least one second field effect transistor switch (30, 31) are also coupled to the current measuring means (57, 67) of the integrated circuit tester (10). An integrated circuit tester and a pin-to-pin interface providing device. 7. The source (37, 38) of at least one third field effect transistor switch (35, 36) is also coupled to the current measuring means (57, 67) of the integrated circuit tester (10). An integrated circuit tester and a pin-to-pin interface providing device. Integrated circuit tester consisting of a high range portion and a low range portion having current applying means 56,66, voltage applying means 61,71, current measuring means 56,67, and voltage measuring means 61,71. 10. An apparatus for providing an interface between a pin 21 of a device under test, comprising: a first gate having a gate coupled to the integrated circuit tester 10, a drain coupled to the pin 21, and a source 27; A second field effect transistor switch 26 having a field effect transistor switch 25, a gate coupled to the integrated circuit tester 10, a drain coupled to the pin 21, and a source 28, and an integrated circuit tester ( A third field effect transistor having a gate coupled to 10, a drain 27 coupled to the source of the first field effect transistor 25, and a source 32 coupled to the current application means 56 and the current measurement means. Switch 30, gate coupled to integrated circuit tester 10, second field effect transistor A fourth field effect transistor 31 having a drain coupled to the source 28 of the stub 26 and a source 33 coupled to the current application means 66 and the low current range measurement means 67; A gate coupled to the integrated circuit tester 10, a drain and voltage application means 61 coupled to the source 27 of the first field effect transistor 25 and a high range portion current measurement means 57 A fifth field effect transistor switch 35 having a source 37 and a drain and voltage applying means 71 coupled to the source 28 of the gate second field effect transistor 26 coupled to the integrated circuit tester 10. And a sixth field effect transistor having a source (38) coupled to the low range portion current measuring means (67). 11. Apparatus according to claim 10, characterized in that it comprises a voltage follower (75) for coupling a pin (21) to the voltage measuring means of the integrated circuit tester (10).

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