KR920017103A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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Publication number
KR920017103A
KR920017103A KR1019920001717A KR920001717A KR920017103A KR 920017103 A KR920017103 A KR 920017103A KR 1019920001717 A KR1019920001717 A KR 1019920001717A KR 920001717 A KR920001717 A KR 920001717A KR 920017103 A KR920017103 A KR 920017103A
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KR
South Korea
Prior art keywords
circuit
signal
semiconductor memory
test mode
test
Prior art date
Application number
KR1019920001717A
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Korean (ko)
Inventor
소오이치 구니토
도시오 노사카
히로시 요시다
스스무 스기타
히데아키 나카무라
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치 세이사쿠쇼
오오노 미노루
히타치 쬬오 엘.에스.아이 엔지니어링 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 가나이 쓰토무, 가부시키가이샤 히타치 세이사쿠쇼, 오오노 미노루, 히타치 쬬오 엘.에스.아이 엔지니어링 가부시키가이샤 filed Critical 가나이 쓰토무
Publication of KR920017103A publication Critical patent/KR920017103A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

반도체 기억장치Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본발명이 적용된 다이나믹형 RAM의 중 메모리 어레이와 로우계의 선태회로의 일시시예를 나타내는 회로도, 제2도는 본 발명이 적용된 다이나믹형 RAM중 센스앰프, 컬럼계 선택회로의 일실시예를 나타내는 회로도.1 is a circuit diagram showing a temporary example of a memory array of a dynamic RAM and a row type circuit of a dynamic RAM to which the present invention is applied, and FIG. 2 is an embodiment of a sense amplifier and a column type selection circuit of a dynamic RAM to which the present invention is applied. Circuit diagram showing.

Claims (3)

정보기억용 캐패시터와 어드레스 선택용 MOSFET로 된 메모리 셀이 워드선과 데이터선과의 교점에 매트릭스 배치되어 구성된 메모리, 어레이와, 테스트모드의 때 상기 메모리 어레이 중의 복수개의 워드선을 동시에 선택상태로 하는 테스트회로를 구비하게 되는 것을 특징으로 하는 반도체 기억장치.A memory circuit comprising an information storage capacitor and an address selection MOSFET in a matrix arranged at an intersection of a word line and a data line, and a test circuit for simultaneously selecting a plurality of word lines in the memory array in a test mode. And a semiconductor memory device. 제1항에 있어서, 메모리 어레이중의 복수의 워드선을 동시에 선택상태로 하는 테스트회로는 테스트 모드때에 워드선 구동신호를 형성하는 구동회로와, 상기 구동회로신호 및 선택신호를 우수번째의 워드선에 공급하는 제2의 스위치군과, 소정의 타이밍신호와 기수 및 우수의 어드레스를 지정하는 어드레스 신호들을 받아서 상기 제1또는 제2의 스위치군을 선택적으로 온상태로 하는 선택회로를 구비하게 된 것을 특징으로 하는 반도체 기억장치.2. The test circuit according to claim 1, wherein the test circuit which makes a plurality of word lines in the memory array selected at the same time includes a driving circuit which forms a word line driving signal in a test mode, and the driving circuit signal and the selection signal are even-numbered words. A second switch group for supplying a line, and a selection circuit for receiving the predetermined timing signal and address signals designating the odd and even addresses to selectively turn the first or second switch group on. A semiconductor memory device, characterized in that. 제2항에 있어서, 상기테스트모드의 지정은 테스트모드때에 사용하지 않는 제어신호 또는 어드레스 신호가 통상 하이레벨 보다 높은 레벨로 입력되도록 행해지는 것을 특징으로 하는 반도체 기억장치.3. The semiconductor memory device according to claim 2, wherein the designation of the test mode is performed such that a control signal or an address signal not used in the test mode is input at a level higher than a normal high level. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920001717A 1991-02-13 1992-02-06 Semiconductor memory KR920017103A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3041153A JPH04258880A (en) 1991-02-13 1991-02-13 Semiconductor memory device
JP91-41153 1991-02-13

Publications (1)

Publication Number Publication Date
KR920017103A true KR920017103A (en) 1992-09-26

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ID=12600479

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001717A KR920017103A (en) 1991-02-13 1992-02-06 Semiconductor memory

Country Status (2)

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JP (1) JPH04258880A (en)
KR (1) KR920017103A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10269800A (en) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPH04258880A (en) 1992-09-14

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