KR920008249Y1 - Sync-detection circuit - Google Patents

Abstract

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Description

Synchronous Detection Circuit by Pulse Width

1 is a synchronization detection circuit based on the pulse width according to the present invention.

FIG. 2 is an operating waveform diagram of each part of the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

G1: logical multiplication device 10: first inspection means

14: delay means 20: second inspection means

30: output stabilization means 40: pulse heat supply means

The present invention relates to a video receiving apparatus, and more particularly, to a circuit for detecting a synchronization signal to remove video and audio noise by providing a non-broadcast channel during a broadcast receiving channel.

BACKGROUND ART In general, a video receiving apparatus includes a television and a video tape recorder (hereinafter, referred to as a VTR), wherein the VTR records a television image signal on a magnetic tape or a television image signal recorded on a magnetic tape. It is a device to play.

The non-broadcast reception channel, which is a no-signal band, of the TV and VTR broadcast reception channels, is difficult to see due to noise and is difficult to listen to voice. And images tend to replace or mute with blue or other monochromatic colors.

In addition, since there are considerably more non-broadcast channels than the broadcast channels among the reception channels of the TV and the VTR, if the number of non-broadcast channels is large between the broadcast channels at the time of receiving channel switching, the time is increased by passing through many non-broadcast channels from the current broadcast channel to the next broadcast channel. There is a lot of inconvenience.

In order to improve this, certain TVs and VTRs use a screen search function to distinguish between broadcast and non-broadcast channels, store the divided broadcast channels in a memory, and skip the non-broadcast channels between the broadcast channels when switching channels. Skip) reduces the channel switching time.

The television and the VTR must mute the non-broadcast channel in order to mute the video and audio in a non-broadcast channel or to skip the non-broadcast channel when switching channels, and to detect the presence of a synchronous signal by a synchronous detector. By determining the presence or absence of the image signal according to the detected result to recognize the non-broadcast channel.

However, the conventional synchronous detection circuit determines that the non-broadcast channel is a broadcast channel by recognizing that the synchronous signal is detected even when there is a pulsed noise signal arranged at a period similar to the vertical synchronous or horizontal synchronous.

Therefore, the TV and the VTR have a problem in that a non-broadcast channel without a broadcast signal does not replace a screen with a single color, mute voice, and skip a non-broadcast channel without a broadcast signal when searching for a screen.

Therefore, the purpose of the present invention is to detect the synchronization by pulse width inspection in the image receiving device, and to detect the synchronization by the pulse width that can mute the video and audio noise of non-broadcast channel or skip the broadcasting channel accurately during channel search. In providing a circuit.

In order to achieve the above object, the present invention provides a synchronization detection circuit of an image receiving apparatus having a synchronization signal separation means for providing a synchronization signal and a measurement pulse generation means for generating a synchronous measurement pulse train; A gate element for gating and outputting the pulse string output from the measuring pulse generating means during a synchronous pulse period of the synchronous signal applied; First inspection means for judging synchronization by inspecting the number of pulses of the first pulse train gated from the gate element during the synchronization pulse period; Delay means for delaying and outputting the output of said first inspection means for a predetermined period; Pulse train supply means for generating an operation control signal having a pulse width according to a delay pulse output from said delay means, and supplying a gate pulse output from said gate element to a second pulse train; And second inspection means for determining whether the signal is a synchronous signal by controlling the number of pulses of the second pulse string during the synchronous pulse period controlled by the dongak control signal output from the pulse train supply means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a configuration as a circuit diagram of an embodiment according to the present invention.

The AND device G1 connects one input terminal to the output terminal of the synchronous separation means (not shown) via the line 1 and the pulse generating means for measurement (not shown) via the other input terminal 2. It is connected to and functions as a gate element.

The first inspection means 20 connects the clock terminal CLK to the output terminal of the logical multiplication device G1 through the line 3 and the output terminal of the synchronous separation means (not shown) through the line 1. A first counter 11 having a reset terminal RS connected thereto, a second counter 12 having a clock terminal CLK connected to an output terminal of the first counter 11, and the line 1; The reset terminal RS is connected to the output terminal of the synchronous separation means (not shown), and the clock terminal CLK is connected to the output terminal of the pulse generating means (not shown) for measurement. And an output terminal comprising a third counter 13 connected to the reset terminal RS of the second counter 12.

The delay means 14 is for delaying the signal output from the first inspection means 10 for a predetermined time and connects an input terminal to an output terminal of the second counter 12 at the end of the first inspection means 10. .

The pulse train supply means 40 is a monostable multivibrator 15 for generating the signal output from the delay means 14 into a pulse of a predetermined width and outputting it through the line 4, and logic through the line 3; A transistor connected to the output terminal of the multiplying device G1 and a base connected to the output terminal of the monostable multivibrator 15 via a line 4 and switched by the output signal of the monostable multivibrator l5 ( Q1).

The second inspection means 20 connects the clock terminal CLK to the emitter of the transistor Q1 and connects the reset terminal RS to the output terminal of the synchronous separation means (not shown) through the line 1. The reset terminal RS is connected to the connected fourth counter 21 and the output terminal of the monostable multivibrator 15 via the line 4, and the clock terminal CLK is connected to the output terminal of the fourth counter 21. ) And a fifth counter 22 connected thereto.

The output stabilization means 30 connects the base to the output terminal of the fifth counter 22 through the inverting element I1, the collector to the reference power supply GND, and the emitter to the supply power supply through the resistor R1. The base is connected to the transistor Q2 connected to Vcc and the emitter of the transistor Q2, the collector is connected to the reference power supply GND, and the emitter is connected to the supply power supply Vcc through the resistor R2. It consists of a transistor Q3 and a capacitor C1 connected between the base of the transistor Q3 and the reference power supply GND.

2 is an operation waveform diagram for each part of FIG. 1, (a) is a synchronization signal, (b) is a pulse train for measurement, (c) is an output waveform diagram of the logical product element G1, (d) is the output waveform diagram of the second counter 12, (e) is the output waveform diagram of the delay means 14, (f) is the monostable multivibrator 15 is the output waveform diagram, (g ) Is an output waveform diagram of the transistor Q1, (h) is an output waveform diagram of the fifth counter 22, and (i) is an operation waveform diagram of the capacitor C1.

The operation of FIG. 1 is then described in detail in conjunction with FIG.

Register separation means (not shown) is an essential component of general televisions and VTRs, and pulse generating means for measurement (not shown) operates a microcomputer in a television and a VTR using a microcomputer (not shown). In the case of televisions and VTRs that are not required for the use of microcomputers, they are artificially added.

The pulse train for measurement, which is the output of the pulse generator for measurement (not shown), has a period that is much smaller than the period of the simultaneous signal as shown in FIG. 2A, as shown in FIG. The synchronization signal as shown in (a) may use either a horizontal or vertical synchronization signal.

A logical product for introducing a synchronous signal supplied from a synchronous separating means (not shown) and a measuring pulse string supplied from a measuring pulse generating means (not shown) through both input terminals (1, 2). The element G1 outputs the pulse string for measurement supplied during the period in which the synchronizing signal is in the high logic state through the line 3 to the collector terminal CLK of the first counter 11 and the collector of the transistor Q1.

At this time, the waveform of the output signal of the logical multiplication device (G1) generates a pulse train as shown in (c) of FIG.

The first counter 11 is an synchronous separation means (not shown) and is in an initialization state while the synchronization signal applied to the reset terminal through the line is in the low logic state. Each time the first predetermined number (for example, "7") is repeatedly counted up to the first predetermined number (here, "7" for convenience) by the gated pulse train supplied from G1) to the clock terminal CLK. Is supplied to the clock terminal CLK of the second counter 12.

The third counter 13 is in the initialization state in the low logic state of the synchronization signal applied from the synchronization separating means (not shown) to the reset terminal RS through the line 1, and then in the high-noise state. Low when a second predetermined number (e.g., "58") is counted by the measurement pulse train applied from the measurement pulse generating means (not shown) to the clock terminal CLK through the line 2 during the period. The logic pulse is supplied to the reset terminal RS of the second counter 12.

When the second counter 12 receives the low logic pulse from the third counter 13 to the reset terminal RS, the second counter 12 is initialized from the first counter 11 to the clock terminal CLK. Delaying means for delaying the first synchronous detection signal as shown in (d) of FIG. 2 having a high logic pulse when the number of pulses is applied is added by "1" to become the third predetermined constant (for example, "8"). 14).

In this case, the first to third constants are set to 7,58,8 so as to assume that the pulse width (synchronous pulse period) of the synchronization signal is greater than about 56 times the period of the measurement pulse and less than 58 times. .

The delay means 14 delays the first synchronous detection signal drawn from the second counter 12 to the monostable multivibrator 15 by delaying a predetermined time as shown in FIG.

The monostable multivibrator 15 generates a high logic pulse having a width wide enough to include the next synchronization pulse period each time the delayed first synchronization detection signal from the delay means 14 is applied. It is applied to the base of the transistor Q1 and the reset terminal RS of the fifth counter 22 via (4).

The output of the monostable multivibrator 15 has a waveform having a pulse width larger than the pulse width from the start point to the end point of the synchronization signal as shown in FIG.

Transistor Q1 is turned on during the period of the high logic state of the output of monostable multivibrator 15 applied to the base via line 4 and is applied to the collector via line 3 to the logic product element G1. The output of the signal is supplied to the clock terminal CLK of the fourth counter 21 through an emitter.

At this time, the output of the transistor Q1 has a waveform of (g) in FIG.

The fourth counter 21 is in the initialization state in the low logic state of the synchronization signal supplied from the synchronization separating means (not shown) to the reset terminal RS through the line 1, and then in the high logic state. The first predetermined number (for example, "7") is repeatedly counted by the gated pulse train applied from the emitter of the transistor Q1 to the clock terminal CLK for a period of time, and the first predetermined value as in the first counter 11 is obtained. Each time a number (eg, "7") is supplied, one pulse is supplied to the clock terminal CLK of the 55th counter 22.

The fifth counter 22 is in the initialization state during the low logic state during the output of the monostable multivibrator 15 applied to the reset terminal RS through the line 4, and then during the high logic state. Every time a pulse is applied from the fourth counter 21 to the clock terminal CLK, a counter is counted by "1", and a second pulse having a high logic state is obtained every time a second constant (for example, "8") is obtained. The second synchronous detection signal as shown in FIG. 7H is applied to the base of the transistor Q2 through the inversion element I1.

In this case, the first and second constants of the fourth and fifth counters 21 and 22 are assumed to be the same as the first and second counters 11 and 12 for convenience of description and to allow an allowable range if necessary. It may be set differently from the first and second counters 11 and 12.

The transistor Q2 is turned on during the pulse period of the second synchronous detection signal, which is the output of the fifth counter 22 that is inverted through the inverting element I1 and applied to the base, to thereby charge all the charging voltages charged in the capacitor C1. Discharge.

The capacitor C1 discharges the charged voltage while the transistor Q2 is turned on through the emitter and the collector of the transistor Q2, and then gradually starts charging from the time when the transistor Q2 is turned off. do.

At this time, the charging speed of the capacitor C1 is determined by the product of the resistance value of the resistor R1 and its capacitance value. Therefore, the charge / discharge voltage waveform of the capacitor C1 becomes as shown in FIG.

After the transistor Q3 is turned on by the transistor Q2, the transistor Q3 is maintained until the charge voltage of the capacitor C1 reaches its turn-on-off voltage by reaching the reference voltage Vr in FIG. The line 5 connected to the emitter transmits a stabilized synchronous detection signal that maintains a stable low logic state.

In order to maintain a stable logic state while the output of the transistor Q3 continues to detect the synchronization signal, the time constants of the resistor R1 and the capacitor C1 must be set larger than the period of the synchronization signal.

As described above, the present invention enables accurate synchronization detection by determining that the synchronization signal has been detected only when the pulse width of the received synchronization signal coincides with the pulse width of the synchronization signal that is continuously defined over two orders. It is possible to accurately skip the non-broadcast channel when switching between the video and the channel in the non-broadcast channel by determining the presence or absence of an image signal, that is, the classification of the broadcast channel and the non-broadcast channel.

Claims (12)

A synchronous detection circuit of an image receiving apparatus comprising: synchronous signal separating means for providing a synchronous signal, and measuring pulse generating means for generating a synchronous measurement pulse train; A gate element (G1) for gating and outputting the pulse string output from the measuring pulse generating means during a synchronous pulse period of the synchronous signal applied; First inspection means (10) for determining whether the synchronization signal is detected by checking the number of pulses of the first pulse string gated from the gate element (G1) during the synchronization pulse period; Delay means (14) for delaying and outputting the output of said first inspection means for a predetermined period; Pulse heat supply means 40 for generating a control signal while supplying a control signal while having a pulse width due to the delay pulse output from the delay means 14, and supplying the gate pulse output from the gate element G1 to the second pulse train; ; And a second inspection means 20 which is controlled by the operation control signal output from the pulse train supply means 40 and determines the synchronization signal by checking the number of pulses of the second pulse train during the synchronization pulse period. A synchronous detection circuit using a pulse width, characterized in that. 2. The first synchronous device of claim 1, wherein the first inspecting means (10) counts the number of pulses of the first pulse string output from the gate element (G1) so that a first predetermined constant is counted. And a plurality of counting means (11,12) for generating a detection signal. 3. The first inspection means (10) according to claim 2, wherein the first inspection means (10) counts a measurement pulse applied from the measurement pulse generation means during the synchronous pulse period to become a second predetermined number of the first counting means. And a counter (13) for initializing a termination counter (12) for generating a synchronous detection signal. 4. The synchronous detection circuit according to the pulse width of claim 3, wherein the second predetermined constant is set larger than the first predetermined constant part. The second synchronous means according to claim 2, wherein the second inspection means (20) counts the number of pulses of the second pulse string output from the pulse train supply means (40) and the second synchronous in the form of a second pulse when the second predetermined number is counted. A synchronous detection circuit with a pulse width comprising a plurality of counting means (21, 22) for generating a signal detection signal. The operation of the first pulse type according to claim 1, wherein the pulse heat supply means 40 has a pulse width larger than the width from the start point to the end point of the synchronization signal by the delay pulse from the delay means 14. A monostable multivibrator 15 for generating an output signal of the first inspection means 10 as a signal and outputting the operation control signal to the second inspection means 20, and the gate by the operation control signal. And a switching means (Q1) for sampling said second pulse string output from the element (G1). 5. The operation according to claim 4, wherein the pulse heat supply means (40) has a pulse width larger than the width from the start point to the end point of the synchronization signal by the delay pulse from the delay means (14). A monostable multivibrator 15 for generating an output signal of the first inspection means 10 as a signal and outputting the operation control signal to the second inspection means 20, and the operation control signal. And a switching means (Q1) for sampling the second pulse string output from the gate element (G1). 2. The synchronization signal detection circuit according to claim 1, wherein the first and second inspection means (10, 20) are reset by a synchronization signal supplied from the synchronization separation means. The method according to claim 1, wherein the first inspection means (10) comprises a first counter (11) for counting the first pulse train during the synchronous pulse period and a pulse train output from the pulse generator for measurement for a predetermined period. And a third counter 12 for outputting a synchronous detection signal in the form of a pulse by counting the second counter 13 for counting and the first and second counters 11 and 13. Synchronous signal detection circuit by width. 10. The method according to claim 9, wherein the second inspection means (20) comprises a first counter (21) for counting the first pulse train output from the pulse train supply means (40) during the synchronous pulse period, and the pulse supply means ( A second counter 22 for outputting a pulse type synchronization signal detection signal when the counting value of the first counter 21 counts the first constant during the pulse period of the operation control signal output from 40). A synchronization signal detection circuit using a pulse width, characterized in that consisting of. 8. The pulse according to claim 7, wherein the synchronization signal detection circuit further comprises output stabilization means (30) for outputting a synchronization detection signal in a stable logic state by the output of the second inspection means (20). Synchronous signal detection circuit by width. 11. The pulse according to claim 10, wherein the synchronization signal detection circuit further comprises an output stabilization means (30) for outputting a synchronization detection signal in a stable logic state by the output of the second inspection means (20). Synchronous signal detection circuit by width.