KR920007425Y1 - Recording and play back mode locking circuit - Google Patents

Abstract

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Description

Recording and Playback Mode Locking Circuit in VTR

1 is a circuit diagram according to the present invention.

FIG. 2 is a detailed circuit diagram of the gate circuit unit 16 in FIG.

3 is a timing diagram for each part according to the present invention.

* Explanation of symbols for main parts of the drawings

10: ciscon 11: key input

12 switch unit 13 first pulse generator

14: second pulse generator 15: program switch unit

16 gate circuit portion 17 third pulse generator

The present invention relates to a system control circuit of a video tape recorder (hereinafter referred to as a VTR) and an audio recorder, and more particularly to a recording and playback mode locking circuit. .

In the current VTR, if the alternating current (AC) power supply is turned off during the playback operation or the recording operation, the VTR stops the operation while the tape is being loaded. When the AC power is turned on again, the system control microcomputer is reset to unload the tape. Therefore, the user has to operate the VTR by pressing the play button or the record button again, which is inconvenient.

In addition, since the tape is unloaded and loaded, the position of the tape is different from the position before the power is turned off, and during playback, a different content is displayed on the monitor (Dksplay).

On the other hand, during recording, there is a problem that noise is generated during playback because the recording portion is left out of position before the power is turned off.

Therefore, the purpose of the present invention is to record and play back in the VTR, which can prevent the system from performing the unloading operation even when the AC power is turned off and on while playing or recording in the VTR. It is to provide a mode locking circuit.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram according to the present invention, and a plurality of keys such as a ciscon 10 for controlling all input signals, a power key PWR, a regeneration key PB, and a recording key REC are described. 10) and the first and second switches SW1 and SW2 and the capacitor C1 to switch to generate a differential signal when switching to lock the current mode during playback or recording mode. Switching unit 12 consisting of resistors R1 and R2 and at least one differential signal is applied by switching of switching unit 12 to delay a predetermined time to generate pulse signal oragate G1 and first stage. A first pulse generator 13 comprising a stable multivibrator 1 and a pulse signal generated by a delay of a predetermined signal by switching of the switch unit 12 to control the key input unit 1 The second pulse generator 14 comprising 2-5 single-stable multivibrators 2-5, and during playback or recording And a program switch unit 15 for outputting different data depending on the stop state and a pulse signal of the first pulse generator 13 to switch the output signal of the program switch unit 15 to the sheath cone 10. The reset circuit 6 and the sixth to generate a pulse signal by resetting the sheath 10 with a reset signal generated by the AC power-on and the gate circuit unit 16 outputting The key input unit 12 includes a third pulse generator 17 comprising a monostable multivibrator 7, a pulse signal of the first pulse generator 13, and a pulse signal of the third pulse generator 17. And an gate G2 for controlling the power key PWR.

FIG. 2 is a detailed circuit diagram of the gate circuit part 16 of FIG.

3 is a timing diagram for each part according to the present invention.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 1-3.

First, when reproducing at the VTR or recording the current mode while operating the recording mode, the first switch SW1 or the second switch SW2 is pressed.

The first and second switches SW1 and SW2 are locking type switches, and the circuit of the present invention operates only when the switch is pressed, and does not operate without pressing and performs normal operation.

First, when the AC switch is turned off when the first switch SW1 which is a reproducing lock switch or the second switch SW2 which is a recording lock switch is turned off, the ciscon 10 is reset again. The power source Vc is connected to the power source terminal VDD of the sheath cone 10 to receive power. The program switch 15 detects that all the modes were the playback or recording mode, and unloads them to control the stop mode. However, when one of the first and second switches SW1 and SW2 is turned on during playback or recording, the power source Vc is input to the switch unit 12 when the AC power is turned off and then on again. The power supply Vc is always a 6V power supply and is independent of the power key PWR when only the AC power supply is turned on.

Since the power supply Vc is applied to the switch unit 12, the differential circuits of the capacitor C1 and the resistor R1, the capacitor C1, and the resistor R2 are applied to the first and second lines L1 and L2, respectively. Pulse waveforms similar to those in FIG. 3 (a) are generated.

The pulse waveform is input to the oar gate G1 and the first and second input terminals of the first pulse generator 13, and the second and fourth stage stable multivibrators 2 and 4 of the second pulse generator 14 are provided. Enter The pulse input to the oragate G1 is changed into a pulse waveform equal to the waveform of FIG. 3 (b) by the first single-stable multivibrator 1. In this case, the pulse duration is about 2 seconds, which includes the reset time and the settling period of the sheath cone 10.

The pulse waveform output from the first stage stable multivibrator 1 is applied to the first input terminal of the AND gate G2 while being applied to the gate circuit unit 16.

A detailed circuit diagram of the gate circuit 16 is shown in FIG. 2. Referring to this detailed circuit diagram, a pulse waveform input to the gate circuit 16 is applied to the transistor Q1 base through the resistor R4 and turned off. The transistor Q2 is biased. The resistor R3 is connected to the transistor Q1 base terminal and the emitter terminal, and the resistor R8 is connected to the collector terminal to ground, and the diode D1 is connected to the input ports A1, B1, To C1).

The signal output from the output terminals A, B, and C of the program switch unit 15 is applied to the base of the transistor Q2 through the resistor R to turn on the transistor Q2.

A resistor R5 is connected to the base terminal of the transistor Q2. The pulse waveform input to the gate circuit 16 at the turn-on of the transistor Q2 is input to the collector terminal of the transistor Q2 through the resistor R7, and is inverted and output only while the transistor Q2 is turned on.

The inverted signal is input to the scissor 10 input ports A1, B1, and C1 through the diode D2. The output state of the output terminals A, B, and C of the program switch unit 15 is A = 1, B = 1, C = 1 during playback or recording, and A = 0, B = 0, C at stop. = 0

Therefore, when turning on after AC off, the system 10 should be recognized as a stop state for a while rather than a play state or a recording state, so that it should not be unloaded.

Therefore, when the operation of the VTR set is played back or recorded before the AC power is turned off during the period in which the waveform of FIG. 3 (b) is high, the scissor 10 Since the data corresponding to the stop mode A = 0, B = 1, and C = 0 are input, the unloading operation is not performed.

During the operation, a pulse waveform, such as the waveform of FIG. 3C, is generated in the reset circuit 6 of the third pulse generator 17 and applied to the reset terminal R of the sheath cone 10 to generate the sheath comb. Reset (100).

In addition, the pulse waveform is applied to the sixth single-stable multivibrator 7, and after a predetermined delay, a waveform such as the waveform of FIG. 3 (d) is input to the second input terminal of the AND gate G2. The AND gate G2 performs a logic operation on two input signals and applies them to the base of the transistor Q3 installed in parallel with the power key PWR of the key input unit 11 through the third line L3.

Thus, transistor Q3 is turned on and transistor Q3 performs the same operation as pressing power key PWR.

On the other hand, the differential pulses applied through the lines L1 and L2 are respectively input to the second and fourth single-stable multivibrators 2 and 4, respectively, and delayed outputs are performed as shown in FIGS. 3G and 3H waveforms.

The output signals of the second and fourth stage stable multivibrators 2 and 4 are inputted to the third and fifth stage stable multivibrators 3 and 5, respectively, and delayed again as shown in FIGS. 3E and 3F. Output

The output signals of the third and fifth multistable multivibrators 3 and 5 are parallel to the playback key PB and the recording key REC of the key input unit 11 through the fourth and fifth lines L4 and L5. It is applied to the installed bases of the transistors QR and Q5.

Therefore, since the transistors Q4 and Q5 are turned on to operate as if the playback key PB or the recording key REC is pressed, the VTR performs the playback or recording operation. Therefore, even when the AC power is turned off and on again, the VTR during playback or recording can continue to perform playback or recording without unloading the magnetic tape.

As described above, even if the AC power is turned off and then turned on again during playback or recording, the VTR is prevented from performing the unloading operation so that the continuity on the tape can be perfected, thereby improving the reliability and quality of the product.

Claims (3)

The system control circuit during playback or recording mode in the VTR having the sheath cone 10 and the key input unit 11 switches to generate a differential signal when the current mode is to be locked during the playback or recording mode. A switching unit 12 and a first pulse generator 13 controlling the key input unit 11 with a pulse signal generated by a predetermined delay when at least one differential signal is applied by the switching of the switch unit 12; And a second pulse generator 14 for controlling the key input unit 11 with a pulse signal generated by a predetermined delay caused by switching of the switch unit 12, and during playback, recording, and stop. A gate for outputting the output signal of the program switch unit 15 to the sheath (10) by switching the program switch unit 15 for outputting other data, the first pulse generator 13 and the pulse signal By circuit part 16 and AC power on And a third pulse generator 17 which resets the sheath cone 10 with a reset signal generated and simultaneously controls the key input unit 11 with a pulse signal. Recording and playback mode locking circuit. 2. Recording and playback mode locking in a VTR according to claim 1, characterized in that the gate circuit section (16) converts the output of the program switch section (15) only during a period when the potential of the first pulse generator (13) is high. Circuit. The recording and reproducing mode in a VTR according to claim 2, characterized in that an AND gate (G2) for controlling the key input unit (11) by ANDing the output signals of the first and third pulse generators (13, 17) is provided. Locking circuit.