KR920005014B1 - Intuterface system of tdx-10 switching centre - Google Patents

Abstract

The circuit includes an address buffer (11) and an address decoder (12) connected to the address buffer (11). A control signal generating means (13) is connected to the address decoder (12), and a data latch means (14) is connected to the control signal generating means (13), thereby forming a level interface means (1) . A relay decoding and driving means (15) is connected to the level interface means (1), and a relay group (16) is connected to the relaying and driving means (15), thereby forming a relay control means (2). Further, subscriber line modules (17,18) and a time slot designating means (20) constitute a communication means (3). With the circuit, a line testing and a circuit testing can be carried out simultaneously.

Description

Interface device of the test device of the TDX-10 exchanger

1 is a block diagram showing the configuration of the present invention.

2 is a block diagram showing the configuration of the control signal generator of FIG.

3 is a timing diagram of the parallel interface of FIG.

* Explanation of symbols for main parts of the drawings

1: parallel interface unit 2: relay control unit

3: call circuit section 11: address buffer

12: address decoder 13: control signal generator

14: Data latch 15: Relay decoder & driver

16: relay group 17: SLIM 0

18: SLIM 1 19: COMBO

20: Time slot designation circuit 21: D type flip flop

22: hexadecimal counter 23: 3/8 decoder

The present invention relates to a circuit for creating a test environment for performing a subscriber test of a TDX-10 switch, and in particular, a test path for a subscriber line, a subscriber terminal, a subscriber circuit, and an analog relay circuit, and a call function of a subscriber to be measured. The present invention relates to an interface circuit of a subscriber test device configured to provide an eavesdropping function.

In the conventional mechanical exchanger, inverter or electronic exchange, all tests except the subscriber circuit and analog trunk test have been tested by installing a test bench that is separate from the exchanger. However, it is possible to perform maintenance on the subscribers accommodated in the host using the test bench method, but it is inefficient to perform maintenance on the subscribers accommodated in the remote switching system (RSS) operated remotely from the host. have.

Therefore, the present invention devised to eliminate the above problems is a board (PBA: Printed Board Assembly) included in the subscriber test apparatus of the TDX-10 exchanger, a test equipment control board (TECA) in which a CPU is mounted. It aims to provide a path that can be tested in the same environment regardless of host or subscribers accommodated in RSS.

In order to achieve the above object, the present invention provides a parallel interface means comprising an address buffer, an address decoder connected to the address buffer, a control signal generating means connected to the address decoder, and a data latch means connected to the control signal generating means. A relay decoder and driver means connected to the parallel interface means, a relay control means consisting of a relay group connected to the relay and drive means, connected to the parallel interface means and a relay control means, SLM 0 and SLM 1, COMBO and It is characterized in that it is configured as a time slot designation means and a call means having a call function and an eavesdropping function.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram showing the configuration of the control signal generator in FIG. 1, and FIG. 3 is a timing diagram of the parallel interface in FIG. 1, where 1 is a parallel interface and 2 is a relay. 3, call circuit, 11 address buffer, 12 address decoder, 13 control signal generator, 14 data latch, 15 relay decoder & driver, 16 relay group, 17 SLIM 0, 18 SLIM 1, 19 is COMBO, 20 is a time slot designation circuit, 21 is a D-type flip-flop, 22 is a hexadecimal counter, and 23 is a 3/8 decoder.

As shown in FIG. 1, the interface circuit of the subscriber test apparatus can be largely divided into details.

First, the parallel interface unit 1 with TECA, the upper control board on which the CPU is mounted, includes the address buffer 11 and the address decoder 12 including a control signal generator 13 and a data latch circuit 14. have. Sending / receiving with TECA receives addresses A0 to A3 and 8-bit data D0 to D7. If bit A3 of the received addresses is at level " 1 ", the data is latched by the control signal generator 13 and received. A ready signal is generated which means completion. The remaining three bits of the address (A0 to A2) are relays constituting a test path, a subcriber line interface module (SLIM) and a time slot assignment circuit (TSAC) that constitute a communication circuit. Second, it is used to generate an address enable signal that controls the control circuit, and second, between the test bus selected by the Test Bus Distributer Board Assembly (TBDA) and the Test Equipment Module Unit (TEMU) responsible for the actual measurement. The relay control unit 2 constitutes the actual test path, and is composed of a relay decoder, a driver 15, and a relay group 16. In addition, the relay group is divided into two groups. The first group that constitutes the path of call function, voice transmission and subscriber terminal test is the subscriber line test, It consists of relays that constitute the pass-through function with the subscriber, the sound transmission, and the path of the subscriber terminal test, and the second group consists of the test path configuration relays related to the subscriber circuit. Since 4/16 decoder 74LS154 selects the relays that constitute each path as the lower 4 bits (D0 to D3) of the data, and generates a signal to control the relay group by the upper 2 bits (D4 and D5). By latching the relay drive data to the drive, the test and tip terminals of the test bus are finally connected to the TEMU, which is the actual measurement equipment, to configure the test environment. The relays of the group are designed to be driven even if they are not restored, ie a line test and a circuit test can be performed simultaneously on the same subscriber under test.

Thirdly, the call circuit unit 3 which provides the call function and the interception function of the subscriber under measurement includes two SLIMs having the functions of a subscriber line interface circuit (SLIC) and a combo (Codee / Filter). TP3211) (17, 18), one COMBO (TP3054) 19, and a time slot designation circuit 20 for time slot designation. For the subscriber terminal test, a call with the subscriber to be measured is essential. For this purpose, the subscriber is connected with TEMU, which is a real measurement device, and the operator provides a call path through the call circuit of the present invention. In the case of the subscriber under measurement accommodated in the host, the two-wire measurement line connected to the present invention is converted into four PCM lines to perform the call and interception function, and then through the TSU (Time Switch Unit) to the four-wire line by the communication circuit of the present invention. It provides the operator with the PCM route as a two-wire call route. In the case of the interception function, the relay group is driven so that the subscriber in the call is not interrupted. In the case of subscribers accommodated in RSS, the operator exists only in the host, so the 2-wire measured line is converted to 4 PCM wires and connected to the present invention through the TSU to the present invention in the host. It converts into 2 lines and connects to the operator, and provides the call function and the eavesdropping function with the RSS receiver. This allows testing of the host and RSS subscribers in the same environment, unlike conventional exchanges. In order to perform the above functions, TSU receives 2.048MHz clock, 8KHz frame synchronization signal, and DrM and Dx, PCM data transmission / reception paths.

The control signal generator 13, as shown in FIG. 2, has a D-type flip-flop 21 triggered by a communication start signal, a received address A3, and a hexadecimal signal whose output is an enable signal. It consists of a counter 22 and a 3/8 decoder 23 which generates a substantial control signal. As shown in FIG. 3, which shows a timing diagram when interfacing with TECA, the data latch clock is configured to generate the third clock after the input of the strobe signal, and the ready is generated to the eighth clock. After that, the latch part and the counter are cleared at the first clock to prepare for the next data transmission and reception.

The present invention configured and operated as described above is capable of automatically connecting the TDX-10 subscriber line and the circuit under test to a test apparatus through a test apparatus controller and connecting an external test apparatus for manual testing according to the needs of the operator. Providing a test point has the advantage of simultaneously performing line and circuit tests on the same subscriber under measurement.

Claims (2)

An address buffer 11, an address decoder 12 connected to the address buffer 11, a control signal generating means 13 connected to the address decoder 12, and a data connected to the control signal generating means 13. Parallel interface means (1) consisting of latch means (14), relay decoder and driver means (15) connected to the parallel interface means (1), and relay group (16) connected to the relay and drive means (15). It is connected to the configured relay control means 2, the parallel interface means 1 and the relay control means 2, and the SLM 0 (17), the SLM 1 (18), the COMBO (19), and the time slot designation means (20). And a call means (3) configured to pass through and intercept. The control signal generating means (13) according to claim 1, wherein the control signal generating means (13) checks the output of the D-type flip-flop (21) and the D-type flip-flop (21) which triggers the strobe which is a communication start signal and the received address (A3). The interface of the subscriber test apparatus comprising a hexadecimal counter means 22 serving as an enable signal and a 3/8 decoder 23 connected to the hexadecimal counter means 22 to generate a substantial control signal. Device.

Images