KR920000396B1 - Error correcting method - Google Patents

Abstract

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Description

Error Correction Method

1 is a block diagram of an example of an error correction encoder to which the present invention is applied.

2 is a block diagram showing an arrangement during transmission.

3 is a block diagram of an example of an error correction decoder.

4, 5 and 6 are diagrams for explaining the operation of the decoder of the error correction decoder.

The present invention relates to an error correction method having high error correction capability for both burst errors and random errors, and furthermore, the risk of missing error detection is reduced.

The applicant of the present application first proposes what is called a cross interleave as a valid data transmission method for a burst error. This is provided to each of the first checkword sequence and the multiple channel PCM data sequence by supplying one word included in each of the multiple channel PCM data sequence in the first arrangement state to the first error correcting coder. By supplying the included one word to the first error correcting code, the first checkword sequence and the plurality of channel PCM data sequences are arranged in the second array, and the one word included in each of the second By supplying to the correction coder, a second checkword sequence is generated, which is to perform a dual reave (array of array change) in units of words. Interleaving distributes and transmits the checkword and PCM data included in the common error correction block, and the error in the multiple words included in the common error correction block when returned to the original arrangement on the receiving side. I'm trying to reduce the number of word. In other words, when a burst error occurs during transmission, the burst error can be distributed. If such interleaving is performed twice, each of the first and second checkwords constitutes a separate error correction block, so that the other side can be corrected even when one of the checkwords cannot correct the error. Can be used to correct errors, and thus the error correction capability can be further improved. However, if even one bit of one word is wrong, the whole one word is regarded as wrong. Therefore, when a random error handles a relatively large amount of received data, it cannot be said that the error correction capability is sufficient.

Therefore, K word within 1 block, for example, 2 word error can be corrected, and when the error location is known, M word error, for example, 3 word error or 4 word error can be corrected. Error correction code (a kind of adjacent code) is combined with the above-described multiple interleaving. In addition, this error correcting code has a feature that makes the configuration of a decoder very simple when only one error is to be corrected.

In this manner, the first stage of decoding for the second error correction block is performed, and after returning to the first array state, the blocking of the first error correction block is performed. In this case, there is a fear that error detection such as determining that there is no error even though there is an error due to decoding of the blocking may occur.

In the present invention, when an error is detected by the first stage decoding, a pointer indicating that there is an error is added, and by determining the coefficient within one block of the pointer by the decoding of the blocking, there is a fear of an error of error detection in the decoding of the blocking. It is preventing. In this way, the possibility of omission of error detection is reduced, and for example, the problem of audible sound when an audio PCM signal is transmitted is solved.

First, the error correction code used in the present invention will be described. When describing error correction codes, vector expressions or representations by circuit groups are used. In GF (2), we consider the m order polynomial F (X), which is the weak point. In the body GF (2), where only the circles of "0" and "1" exist, the covenant polynomial F (X) has no root. So consider a hypothetical root α that satisfies (F (X) = 0). At this time, 2 m different circles 0, α, α ² , α ³ ... Represented by powers of α including eternity. α ^2m-1 constitutes the enlarged body GF (2m). GF (2m) is a polynomial ring in which the m-th order weak polynomial F (x) on GF (2) is a method.

The circle of GF (2m) is 1, α = {X}, α ² = [x ² }... … , α ^m-1 = {X ^m-1 }. A ₀ + a ₁ {X} + a ₂ {X ² } +... + a _m-1 {X ^{m + 1} } = a ₀ + a ₁ α + a ₂ α ² +... + a _m-1 α ^m _-1

Or (a _m-1 , a _m-2 , …… a ₂ , a ₁ , a ₀ )

Where a ₀ , a ₁ ,... , a _{m -1} GF (2).

As an example, considering GF (2 ⁸ ), all 8 bits of data are (modF (x) = X ⁸ + X ⁴ + X ³ + X ² +1) and a ₇ X ⁷ + a ₆ X ⁶ + a ₅ X ⁵ + a ₄ X ⁴ + a ₃ X ³ + a ₂ X ² + a ₁ X + a ₀ or (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ), so that a ₇ is assigned to the MSB side and a ₀ is assigned to the LSB side. An belongs to GF (2), and therefore is 0 or 1.

In the polynomial F (X), the next matrix T of (m × m) is derived.

Another expression is the use of a circuit group.

This is the use that the circle with the exception of the 0 circle in GF (2 ^m) forms a multiplicative group of a percentile 2 ^{m + 1.} The circle of GF (2 ^m ) is expressed using a traversal group, where 0,1 (= α ^2m-1 ), α, α ³ , α ³ ,. α ^{2m −2} .

In one example of the present invention, when m bits are one word and one block is formed by n word, K checkwords are generated based on the following parity check matrix H.

Similarly, the parity check matrix H can be expressed by the matrix T.

Where I is the unit matrix of (m × m).

As mentioned above, both representation using root α and representation using generation matrix T are essentially the same.

In the case of using four checkwords, for example, parity check matrix H is

(단

:에러패터언)이라고 하면, 수신측에서 발생하는 4개의 신드로움 S₀,S₁, S₂,S₃는It becomes Column vector of 1 block of received data

(only

Error pattern), the four syndromes S ₀ , S ₁ , S ₂ , and S ₃

It becomes This error correcting code can correct errors up to two word errors in one error correction block, and can correct three or four word errors when the error location is known.

Four checkwords (p = W ₃ , q = W, r = W ₁ , s = W ₀ ) are included in one block. This checkword is obtained as follows.

를 뜻한다.Where ∑ is

It means.

p + q + r + s = ∑W ⁱ = a

α ³ p + α ² q + αr + s = ∑α ⁱ W ⁱ = b

α ⁶ p + α ⁴ q + α ² r + s = ∑α ²ⁱ W ⁱ = c

α ⁹ p + α ⁶ q + α ³ r + s = ∑α ³ⁱ W = d

If the calculation process is omitted and only the result is displayed

Becomes In this way, the formation of the checkwords p, q, r, s is the role of the encoder on the transmitting side.

Next, data including the checkword formed as described above is transmitted, and the basic algorithm of error correction in the case of reception is described.

[1] Without error: S ₀ = S ₁ = S ₂ = S ₃ = 0

[2] In the case of 1 word error (error pattern is ei): S ₀ = ei S ₁ = α ⁱ ei S ₂ = α ²ⁱ ei S ₃ = α ³ⁱ ei

therefore

When i is sequentially changed, it is possible to determine whether or not the relationship is true or not. or

The error location i can be known by comparing the pattern ⁱ of α ⁱ with those previously stored in the ROM. The syndrome S _{1 at} this time becomes the error pattern ei itself.

[3] in the case of two error (ei, ej)

If we transform the common expression

therefore

Is a 2 word error, and the error pattern

[4] in case of three error (ei, ej, ek)

By transforming common sense

therefore

At the top

If this is true, it can be determined as a three-word error. The condition is that (S ₀ ≠ 0, S ₁ ≠ 0, S ₂ ≠ 0). Each error pattern at that time

Obtained by In practice, the configuration for correcting the third error becomes complicated, and the time required for the correcting operation also becomes long. Therefore, in combination with the case where the error location of i, j, k, l is known by the pointer, it is practical to use the above expression for the check at that time and perform the error correction operation.

[5] In case of four error (ei, ej, ek, el):

If we transform the common expression

When the error location (i, j, k, l) is known by the pointer, error correction can be performed by the above operation. The basic algorithm of error correction described above is to check whether there is an error in the first step, using the syndrome S ₀ to S ₃ , check whether or not it is a 1 step error in the second step, and 2 in the third step. Checking whether there is a warning error, and when trying to correct even two warning errors, the time required to complete all steps is long, and this problem occurs especially when obtaining the error location of two warning errors. do. Therefore, a modified modified aridium that is applied to a case where correction of a second error is assumed without causing such a problem will be described next.

2 The equation for the syndrome S ₀ , S ₁ , S ₂ , S ₃ in the case of an error (ei, ej) is as described above.

If you transform this expression

Transform again to obtain the following error location polynomial.

Where the coefficients of each equation

Place it.

By using the coefficients A, B, and C in the above equation, the error location in the case of two-word error can be obtained.

[1] Without error: A = B = C = 0, S ₀ = 0, S ₃ = 0

에서 에러로케이션 i를 알 수 있고, (ei=S₀)를 사용하여 에러정정이 이루어진다.[2] In case of 1 error: When 1 = A = B = C = 0, S ₀ ≠ 0, S ₃ ≠ 0, it is determined as 1 error.

The error location i can be found at, and error correction is made using (ei = S ₀ ).

[3] In the case of two-word error: (A ≠ 0, B ≠ 0, C ≠ 0) is established in the case of an error of two words or more, and the determination becomes very simple. At this time

라고 놓으면

이며Is established. here

If you release

And

Becomes If the difference between two error locations is t, that is (j = i + t)

Is transformed into therefore

의 값을 미리 써넣어 두고, ROM의 출력과 수신워어드에서 연산된

의 값과의 일치를 검출하는 것으로 t가 구해진다. 만약, 이 일치관계가 성립되지 않으면, 3워어드 이상의 에러이다. 그래서Becomes Each of (t = 1-(n-1)) in ROM,

The value of is written in advance, and the output of the ROM and the received word are calculated.

T is found by detecting a match with the value of. If this match does not hold, it is an error of more than 3 words. so

By putting

Error locations I and j are obtained. Error pattern ei, ej

Can be corrected.

The modified correction algorithm described above can shorten the time required to obtain an error location when performing correction of two-word error compared to the basic algorithm.

If the number K of checkwords is further increased, the error correction capability is further improved. For example, if (K = 6), up to 3 word errors can be corrected, and up to 6 word errors can be corrected when the error location is known.

와 각 워어드가 연속되는 PCM 데이터가 얻어지며, 우측채널의 오디오신호에 대해서도

로 각 워어드가 연속되는 PCM 데이터가 얻어진다. 이 좌우의 채널의 PCM 데이터가 각기 6채널씩으로 나누어지며, 합계 12채널의 PCM 데이터계열이 입력된다. 소정에 타이밍에 있어서는

의 12워어드가 입력된다. 이 예에서는 1워어드를 상위 8비트와 하위 8비트로 나누고, 12채널을 다시 24채널로 해서 처리하고 있다. PCM 데이터의 1워어드를 간단하게 하기 위해 W_i로서 표시하고, 상위 8비트에 대해서는 W_i, A와 A의 서픽스를 부가하고, 하위 8비트에 대해서는 Wi, B와 B의 서픽스를 부가해서 구별하고 있다. 예를 들면,

이

및

의 둘로 분할되게 된다.Next, a specific example in which the present invention is applied to recording and reproducing an audio PCM signal will be described with reference to the drawings. Fig. 1 shows the error correction encoder installed in the recorder as a whole. The audio PCM signal is supplied to the input side. The audio PCM signal is formed by sampling each of the left and right stereo signals at a sampling frequency f _s (for example, 44.1 [KHz]) and converting one sample into one word (16 bits as a two's complement code). have. Therefore, the audio signal of the left channel

And each word are contiguous PCM data, and the right channel audio signal

This results in PCM data in which each word is contiguous. The PCM data of the left and right channels are divided into six channels each, and a total of 12 channels of PCM data sequences are input. In the timing

12 words of are entered. In this example, 1 word is divided into upper 8 bits and lower 8 bits, and 12 channels are processed into 24 channels again. Shown as W _i For the sake of simplicity the first War Admiral of PCM data, and adds the W _i, A and A suffix of for the upper 8-bits, and added to Wi, B and B suffix of for the lower 8 bits To distinguish them. For example,

this

And

Will be divided into two.

의 각각의 짝수번째의 워어드이며, 이것 이외가 홀수번째의 워어드이다. 짝수번째의 워어드로 이루어진 PCM 데이터계열의 각각이 우기인터리이버(1)의 1워어드지연회로(2A)(2B)(3A)(3B)(4A)(4B)(5A)(5B)(6A)(6B) ( 7A)(7B)에 의해서 1워어드 지연된다. 물론 1워얻보다 큰 예를들어 8워어드를 지연시키도록 해도 된다. 또, 우기인터리이버(1)에서는 짝수번째의 워어드로 이루어진 12개의 데이터계열이 제1~제12번째까지의 전송채널을 차지하며, 짝수번째의 워어드로 이루어진 12개의 데이터계열이 제13~제24번째까지의 전송채널을 차지하도록 변환된다.This 24-channel PCM data sequence is first supplied to the rainy season interleaver 1. If we say (n = 0,1,2 ...),

Each even word is an odd word. Each of the PCM data sequences consisting of even-numbered words is one word delay circuit (2A) (2B) (3A) (3B) (4A) (4B) (5A) (5B) of the rainy season interleaver (1). One word is delayed by (6A) (6B) (7A) (7B). Of course, you may want to delay 8 words, for example, larger than 1 gain. In the rainy season interleaver 1, twelve data sequences consisting of even-numbered words occupy the first to twelfth transmission channels, and twelve data sequences consisting of even-numbered words are represented by thirteenth. It is converted to occupy the up to 24th transmission channel.

로 연속되는 3워어드를 생각하면, L_i가 틀렸으며, 더구나 이 에러의 정정이 불가능한 경우에 L_i-1또는 L_i+1이 올바른 것이 요망된다. 그것은 틀린 데이터 L_i를 보정할 경우에 있어서, 상기 올바른 워어드 L_i-1로써 L_i로써 보간(補間)(전치호울드)하거나, L_i-1및 L_i+1의 평균치로써 L_i를 보간하기 위해서다. 우기인터리이버(1)의 지연회로(2A)(2B)~(7A)(7B)는 인접하는 워어드가 다른 에러정정블록에 포함되도록 하기 위해서 설치되어 있다. 또, 짝수번째의 워어드로 이루어진 데이터계열과 홀수번째의 워어드로 이루어진 데이터계열마다에 전송채널을 묶은 것은 인터리이브 했을때에, 근접하는 짝수번째의 워어드와 홀수번째의 워어드와 홀수번째의 워어드와의 기록위치 사이의 거리를 되도록 크게 하기 위해서이다.The rainy season interleaver 1 is for preventing two or more consecutive successive wrongs for each of the left and right stereo signals, and furthermore, it is impossible to correct this error. E.g

Considering three consecutive words, L _i is wrong, and furthermore, it is desired that L _i-1 or L _{i + 1} be correct when this error cannot be corrected. It is the in the case to correct the wrong data L _i, the correct War Admiral L interpolation (補間) as L _i as _i-1 (the pre-arc Ould) or, L _i as L _i-1 and the average value of L _{i + 1} To interpolate. Delay circuits 2A (2B) to (7A) and (7B) of the rainy season interleaver 1 are provided so that adjacent wordwords are included in other error correction blocks. In addition, when the transmission channel is bound to each data sequence of even numbered and odd numbered words, when interleaved, adjacent even numbered and odd numbered and odd numbered numbers This is to increase the distance between the first word and the recording position.

가 형성된다.At the output of the wet interleaver 1, the 24 channel PCM data sequences in the first arrangement state are shown, one word from each of them is supplied to the encoder 8, and the first check word is input.

Is formed.

The first error correction block, including the first checkword,

It becomes In the first encoder 8, the number of words of one block; (n = 28), the number of bits in one word; (n = 8), Checkword number; (k = 4) encoding is performed.

The 24 PCM data sequences and four checkword sequences are supplied to the interleaver 9. In the interleaver 9, the check word sequence is changed between the PCM data sequence of even numbered word and the PCM data sequence of odd numbered word, and then the position of the transmission channel is changed. Delay processing is performed for Eve. This delay processing is performed for each of the 27 other transport channels except for the first transport channel, 1D, 2D, 3D, 4D, ..., 26D, 27D (where D is the unit delay amount, for example, 4 It consists of inserting an ad delay circuit.

가 형성된다. 제2의 체크워어드를 포함해서 구성되는 32워어드로 이루어진 제2의 에러정정블록은 다음의 것으로 된다.At the output of the interleaver 9, 28 data sequences in a second array are shown, and one word is taken out from each of these data sequences and supplied to the encoder 10, and the second check word is displayed.

Is formed. A second error correction block consisting of 32 words including a second check word is as follows.

Of the 32 data sequences including the first and second checkwords, an interleaver 11 is provided in which a delay circuit of one word is inserted for the even numbered transmission channel, and a second interleaver 11 is provided. Inverters 12, 13, 14 and 15 are inserted into the checkword series. The interleaver 11 copes with the fact that the error across the boundary between blocks cannot easily be corrected to the number of words and errors. Inverters 12 to 15 are provided to prevent a malfunction in which all data in one block is "0" due to the dropout at the time of transmission, and this is determined to be correct in the reproduction system. have. For the same purpose, an inverter may be inserted for the first checkword series.

Then, serialized every 32 words taken out from each of the 24 PCM data sequences and 8 checkword sequences finally obtained, and as shown in FIG. It is sent in blocks. In FIG. 2, for simplicity, the 1 word taken out of the i-th transmission channel is indicated as ui. Specific examples of the transmission system include a magnetic recording / playback apparatus and a rotating disk apparatus.

The encoder 8 relates to an error correcting code as described above, wherein (n = 28, m = 8, k = 4), and the same encoder 10 is (n = 32, m = 8, k = 4). )to be.

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transport block. Because it is reproduction data, it may contain an error. If there are no errors, the 32 words applied to the input of this decoder will match the 32 words that appear in the error correction encoder's output. In the error correction decoder, deinterleaving processing corresponding to the interleaving processing in the encoder is performed, and the error is corrected after the data order is restored.

를 단지 Wi로서 나타내고 있다.First, a deinterleaver 16 is inserted into which an odd-word supporting circuit is inserted into an odd numbered transmission channel, and inverters 17, 18, 19, and 20 are inserted into a checkword sequence. It is supplied to the decoder 21 of the first stage. In the decoder 21, as shown in FIG. 4, the parity check matrix H _C1 and the 32 words of input (V ^T ) are generated, and the syndromes S ₁₀ , S ₁₁ , S ₁₂ , and S ₁₃ are generated. Thus, error correction as described above is performed. α is a circle of GF (2 ⁸ ) of (F (X) = X ⁸ + X ⁴ + X ³ + X ² +1). Decoder 21 shows 24 PCM data sequences and 4 checkword sequences, and at least one bit pointer ("1" when there is an error) indicating an error in every word of this data sequence. Otherwise, “0”) is added. In FIG. 4 and FIG. 5 described later, and in the following description, the received word is received.

Is only shown as Wi.

The output data sequence of the decoder 21 is supplied to the deinterleaver 22. The deinterleaver 22 is for canceling the delay processing of the interleaver 9 in the error correction encoder, and is applied to each of the first to 27th transmission channels (27D and 26D). A delay circuit having a delay amount of 25D, 2D, 1D) is inserted. The output of the deinterleaver 22 is supplied to the decoder 23 for blocking. A decoder (23) in as shown in FIG. 5, roum Sind in parity check matrix 28 War Admiral of H _C2 to the input S _20, S _21, S _22, and the S ₂₃ occurs, the error correction is performed on the basis of this .

The data sequence appearing at the output of the decoder 23 of such a block is supplied to the rainy season interleaver 24. In the UGI deinterleaver 24, the PCM data sequence consisting of the even numbered word and the PCM data sequence consisting of the odd numbered word are returned so as to be located in the mutually staggered transmission channel, and the PCM data consisting of the odd numbered word One word delay circuit is inserted into the data series. At the output of the rainy season deinterleaver 24, a PCM data sequence having the same arrangement and a predetermined transmission channel as that supplied to the input of the error correction encoder is obtained. Although not shown in FIG. 3, a correction circuit is provided next to the UGI de-interleaver 24, so that an error that cannot be corrected by the decoders 21 and 23 becomes inconspicuous, for example, Average value interpolation is performed.

In one example of the present invention, up to one word error is corrected in the decoder 21 of the first stage.

If it is detected that there are two or more errors in one error correction block, a pointer of at least one bit indicating that there is an error is added to all of the words in the error correction block except 32 or checkwords. do. This pointer will be "1" if there is an error, or "0" otherwise. When one word is 8 bits, a pointer is added as the uppermost 1 bit of the most significant bit, and one word is 9 bits, which is processed by the deinterleaver 22 and supplied to the decoder 23 for blocking.

In the blocking decoder 23, error correction is performed by using the error word coefficient or the error location in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the decoder 23 of this blocking. In FIG. 6 and the following description, the coefficient of the error word by the pointer is represented by N _p , and the error location by the pointer is represented by E. _It is represented by _i . In FIG. 6, Y represents a process and N represents indefinite.

Z_i)인지 여부를 조사한다.(N_p

Z₁)이라면, 에러가 없는 것으로 판정해서, 그 에러정정블록내의 포인터를 클리어(“0”)로 한다. (N_p＞Z₁)이라면 신드로움에 의한 검출이 틀린 것으로 해서, 포인터를 그대로 두든지, 그 블록내의 모든 워어드의 포인터를 “1”로 한다. Z₁로서는 매우 크며 예를들면 14로 한다.(1) Examine the presence or absence of the error by the syndrome S ₂₀ to S ₂₃ . If (S ₂₀ = S ₂₁ = S ₂₂ = S ₂₃ = 0), no error is assumed. In that case, (N _p

Z _i ) to see if it is (N _p ).

Z ₁ ), it is determined that there is no error, and the pointer in the error correction block is cleared ("0"). If (N _p > Z ₁ ), the detection by the syndrome is wrong, and the pointer is left as it is or the pointers of all the words in the block are set to "1". Z _{1 is} very large, for example, 14.

(2) If there is an error, check whether or not it is a single error by calculating the syndrome. In case of one error, the error location i is obtained. It is detected whether or not the error location i obtained by the operation of this syndication coincides with that by the pointer.

Z₂)인지의 여부를 조사한다. Z₂는 예를들면 10이다. (N_p

Z₂)이라면, 이것은 1워어드에러로 판단하며, 1웨어드에러의 정정을 한다. (N_p＞Z₂)이라면 1워어드에러라고 판단하는 것은 위험하므로, 포인터를 그대로 두든지, 또는 모든 워어드를 에러로 간주해서 각 포인터를 “1”로 한다.When there are multiple error locations by pointer, we check whether they match any. If (i = Ei), then ((N _p

Z ₂ ). Z ₂ is for example 10. (N _p

Z ₂ ), it is determined as a 1 error and corrects 1 wear error. If (N _p > Z ₂ ), it is dangerous to judge that it is a 1 word error, so either leave the pointer as is or set each pointer to "1" considering all the words as errors.

Z₃)인지의 여부를 조사한다. Z₃는 매우 작은 수로서 예를들면 3이다. (N_p

Z₃)가 성립 할 때에는 신드로움의 연산으로써 에러로케이션 i에 대한 1워어드에러를 정정한다.(N _{p for} (i ≠ E _i )

Z ₃ ) or not. Z ₃ is a very small number, for example 3. (N _p

When Z ₃ ) is established, one word error for the error location i is corrected as a calculation of the syndrome.

Z₄)이지의 여부를 조사한다. 즉, (Z₃＜N_p

Z₄)일 때는 신드로움에 의한 1워어드에러의 판정이 틀려 있는 것치고는 N_p가 지나치게 작은 것을 뜻하므로, 그 블록의 전 워어드의 포인터를 “1”로 한다. 반대로 (N_p＞Z₄)이라면, 포인터를 그대로 둔다. Z₄는 예를 들면 5이다.In the case of (N _p > Z ₃ ) again (N _p

Z ₄ ) to see if it is. That is, (Z ₃ <N _p

In case of Z ₄ ), N _p is too small compared with the fact that one word error is judged incorrectly. Therefore, the pointer of all word of the block is “1”. Conversely, if (N _p > Z ₄ ), the pointer is left as it is. Z ₄ is, for example, 5.

Z₅)인지의 여부를 판단하며, (N_p

Z₅)일 때는 포인터의 신뢰성이 빈약하므로, 모든 워어드의 포인터를 “1”로 한다. (N_p＞Z₅)일 때에는 포인터를 그대로 둔다.(3) If it is not one word error (N _p

Z ₅ ) or (N _p

In case of Z ₅ ), pointer reliability is poor, so all the word pointers should be “1”. When (N _p > Z ₅ ), the pointer is left as it is.

(4) Correction to the M word may be made by using an error location by a pointer as indicated by the line in FIG. Although it is possible to correct up to four warning errors, in order to prevent wrong correction, it is about (M = 2) and the correction of the two warning errors is made with respect to the error location (i, j) indicated by the pointer. In the case of N _p ≠ M), either leave the pointer as is or change all the pointers of the word to indicate an error.

The specific values of the comparison values Z ₁ to Z ₅ with respect to the number N _p of pointers indicating an error in one block are only examples. If the error correcting code in the above example is more than 5 word errors, there is a fear that this error does not exist, and the comparison value can be set to an appropriate value in consideration of the probability of occurrence of such omission.

In the error correction decoder shown in Fig. 3, error correction using the first checkwords Q _12n , Q _{12n + 1} , Q _{12n + 2} , and Q _{12n + 3} , and the second _{checkword P12n} , P _12n Error correction using ₊₁ , P _{12n + 2} and P _{12n + 3} is performed once.

If each error correction is performed two or more times (about two times in practice), the error can be reduced by the corrected result, and thus the error correction capability can be further increased. In this way, when the decoder is further provided at the rear end, it is necessary to correct the checkword in the decoders 21 and 23.

In the above example, as the delay processing in the interleaver 9, the delay amount is changed by P. However, unlike the change in the regular delay amount, it may be irregular. The second checkword P _i is an error correcting code including not only PCM data but also the first check word Q _i .

Similarly, it is also possible for the first checkword Q _i to also include the second checkword P _i . Specifically, the second check word P _i may be fed back and supplied to the encoder forming the first check word P _i .

As can be understood from the above description, according to the present invention, since the burst error is distributed by cross-interleaving, effective error correction can be performed for both random error and burst error. In case of detecting the presence or absence of an error at the time of decoding in the blocking decoder, not only the calculated reliability but also the number of pointers from the first stage decoder are judged that there is no error, so that the detection of the presence or absence of an error is ensured. can do. Therefore, the fear of missing an error can be prevented.

In the example of the present invention described above, in the first stage decoder, errors up to one word error are corrected, but modifications such as corrections up to two error errors are possible. It is also possible to add a pointer indicating that there is an error for every word in the error correction block that contains the word. Similarly, a configuration for correcting errors up to two words in the blocking decoder may be provided.

Claims (1)

A first error correction block is formed, which is comprised of one word included in each of the plurality of channel PCM data sequences in the first array state and the first check word associated therewith, wherein the plurality of channel PCM data sequences are formed. And the first checkword sequence in a second arrangement state by delaying a different time for each channel, and each of the plurality of channels of the PCM data sequence and the first checkword sequence in this second arrangement state. A second error correction block is formed, which includes one word included and a second checkword therein, wherein the first and second error correction blocks calculate an error syndrome, and from this error syndrome In the error correction method of the constitution of the adjacent code | symbol which can correct the error to the Kword contained in the same block by obtaining a location, the first stage decoding with respect to a 2nd error correction block is performed. I) Next, the plurality of PCM data sequences and the first checkword sequence in the second array state are set to the first array state by delaying different times for each channel, followed by the first error correction block. In the first stage of decoding, a pointer indicating the presence or absence of an error is added to each word according to the decoding result of the second error correction block. The number of pointers indicating an error in the first error correction block is counted. When the number of pointers indicating this error exceeds a predetermined number, even when a determination result without an error is obtained by decoding of the blocking, at least the first step is obtained. Error correction method that prevents omission of error detection while leaving the pointer added in decoding.

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