KR910007711B1 - Method and apparatus for transmitting data converted by line transmission code system - Google Patents

Abstract

The apparatus uses the line transmission code (Park-cho 86) to transmit the European standard first multiple signal to the north west standard first transmission relay system. The method includes steps: (A) converting 2048Kbps serial 8bit binary data transmitted from the European standard first multiple transmission system to 1536Kbps parallel 6bit ternary data and generating the 1544Kbps bi- polarity data by adding the 8Kbps frame data; (B) converting the 1544Kbps bi-polarity 6-bit ternary data into the 8-bit binary data, synchronizing the frame data, and converting to the 2048Kbps serial data. The apparatus includes a transmitter (310) for converting the European standard signal into PC86 code signal and transmitting to the North American Standard relay system, and a receiver (350) for converting the PC86 code signal into the European standard signal and transmitting to the European standard transmission system.

Description

First Multiple Transmission Matching Method and Apparatus in North America and Europe

1 is a comparison of the conventional AMI code and the PC86 code.

2 is a North American conversion form of the first multiple frames for the PC86 code according to the present invention.

3 is a functional block diagram of a transmission / reception matching circuit of the present invention.

4 is a detailed diagram of a transmission matching circuit of the present invention.

5 is a detailed view of the reception matching circuit of the present invention.

6 is a PC86 encoding flowchart according to the present invention.

7 is a PC86 decoding flowchart according to the present invention.

8 is a configuration diagram of the test switch of the present invention.

9 is a coded data output table according to the present invention.

10 is a diagram showing the functions of the first multiplex transmission matching device in North America and Europe.

* Explanation of symbols for main parts of the drawings

301: clock input terminal 303: clock output terminal

302: data input terminal 304: data output terminal

308, 309: positive and secondary transmission line 310: transmitting unit

315: first phase synchronizing loop (PLL) 316: second phase synchronizing loop

320: frame counter 325: first buffer controller

326: second buffer controller 321: clock recovery and frame synchronization unit

322 disparity counter 323 frame generator

330-333, 451-455, 551-555: buffer

335: PC86 encoder 336: PC86 decoder

340: Bipolar Drive 341: Bipolar Receiver

350: receiver 401-412, 501-504, 806: endgate

421-423, 521, 522, 803: Oagate

431-439, 531-534, 805: Inverter

441-443, 541, 542: counter 461,462: encoder

561: Decoder 470: Disparity Counter

481, 482, 581: latch circuit 801, 802: switch

807 multivibrator 808 light emitting diode

R1-R4: Resistance

The present invention utilizes a special line transmission code called Park-Cho 86 code (hereinafter referred to as PC86 code) to a European primary multiplex signal on a North American primary relay transmission system (transmission rate; referred to as a T1 system of 1,544 Kbps or less). The present invention relates to a first multi-transmission matching method and apparatus in North America and Europe that enables transmission of (information amount; 2,048 Kbps).

North American primary multiplexing devices and relay systems have been used in the United States since 1962. Currently, this method is widely used in relay stations and subscriber carriers in Korea. However, in North America, as the digital exchange is used and the communication network is developed into an integrated information communication network (ISDN), the following fundamental problems are exposed.

First, the internal bus structure of the digital exchange is similar to that of the European primary multiplexing signal. Therefore, when the European transmission scheme is adopted, the transmission and the exchange can be easily matched. Additional matching is required for this purpose.

Secondly, the narrowband Telecommunication Network is based on the B channel with 64Kbps of information. The European method satisfies this, but the North American method can only secure 56Kbps channel for some reasons.

Therefore, there is an active discussion in Korea to switch from the existing North American transmission method to the European transmission method for the development of a comprehensive information communication network. However, even if the one-to-one conversion of the communication method is difficult to be promoted in a short period of time, the existing T1 system is used. Appropriate complementary measures are needed.

The present invention has been devised to solve the above problems, and matched to enable the transmission of the first group signal (2.048 Kbps) multiplexed in Europe as in FIG. 10 using the existing North American T1 relay transmission system without modification. The main principle of the device is to apply an appropriate transmission code that reduces the actual transmission speed rather than the amount of information to be transmitted. As such a transmission code, various types can be considered, but the present invention devises and uses a PC86 code of a concept similar to 4B3T currently used in some foreign large-capacity transmission systems under the premise of utilizing the existing T1 system. The purpose of this PC86 code is to provide a code for converting eight binary data (combination of "ψ" and "1") into six ternary data (combination of "+" "ψ" "-").

That is, 256 combinations of 8 binary numbers are possible, and 729 combinations of 6 ternary numbers are possible. Therefore, a direct current on the transmission line as shown in FIG. 9 can be transmitted to the T1 system by taking an appropriate combination among these 729 combinations. The PC86 code was devised to minimize the components.

In order to minimize the direct current component (hereinafter referred to as "disparity") in the PC86 code window, a series of identical polarity limitations (e.g. "+, +, +, ..." or "-,-,-, ...") Avoiding the form and taking the form '+,-, +,-,…' and focusing on the prevention of accumulation of DC components by the same polarity repetition).

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of transmission to an existing T1 system adopting Alternate Mark Inversion (AMI) transmission code and transmission by PC86 code when transmitting binary data. When transmitting in binary data, the transmission rate is reduced to 3/4. Therefore, when the PC86 code is adopted for data transmission of 2,048 Kbps, the transmission speed becomes 1,536 Kbps, and there is a difference of 8 Kbps from the transmission speed of the existing T1 system (1,544 Kbps). In the original T1 system, 1,536 Kbps is used for information transmission, and 8 Kbps is used as frame bits for frame synchronization at the receiving end. Therefore, as shown in FIG. Used for the same purpose as the frame bits used.

Thus, if 2,048Kbps data is applied to PC86 code, ternary data of 1,536Kbps can be obtained, and if 8Kbps of frame bit is added to this, finally, it becomes ternary data of 1,544Kbps transmission rate. It can be used as it is to transfer data of 2,048 Kbps.

Herein, the operation principle of the PC86 code will be described in more detail in view of the above-described DC component removal. In general, the first condition that the transmission code must satisfy is the removal of the DC component on the line. When a DC component is present in a line, it is difficult to set a threshold level, automatic gain control, and heavy feeding at the receiving end.

Therefore, the existing T1 relay transmission system adopts the AMI transmission code, which transmits the "+" pulse and the "-" pulse alternately in the data transmission of "1" to achieve direct current balance (by the AMI code of FIG. 1). Bipolar pulses). However, when 6-bit ternary data is combined and coded, DC equilibration is performed in 6-bit data units such as "+,-, +,-, +,-" or "+, 0,-, +, 0,-". There are 112 combinations in total, which makes it impossible to display all 256 combinations of 8-bit binary numbers.

Therefore, there is no choice but to use a combination that cannot achieve DC balance in 6-bit ternary data units, such as "+,-, +,-, +, 0". In this case, a method for achieving DC balance in a wide time zone must be devised. do.

This introduces the concept of disparity (the difference between the number of "+" and "-" pulses), as shown in FIG. 9 for 6-bit binary data in positive mode and negative mode. Bit ternary data is allocated. Assuming that 8-bit binary data "10000000" is transmitted, the parent data "-,-, 0, 0, +,-" is transmitted when the state before transmission is positively unbalanced. If the previous status is DC unbalanced negatively, select and transmit "+, +, +, 00,-, +" data in the forward mode. Allow it to proceed in the direction of equilibrium. That is, the PC86 code is set to parent and positive mode codes, and the positive and negative codes are selected and transmitted according to the previous DC balance state to control the DC balance in the long term even if the DC imbalance appears in the short term. For this purpose, the combination of 729 6-bit ternary digits with the least possible DC unbalance (disparity number) corresponds to 8-bit binary digits.

Except where two or more identical polarities are consecutive at the beginning or end of a combination (in the worst case, to prevent four or more consecutive pulses of the same polarity)

Except in the case of 3 or more consecutive identical polarities in a combination

Except when the disparity is 3 or more

3 is a functional block diagram of the transmitting and receiving apparatus of the present invention for transmitting 2,048 Kbps data at a speed of 1,544 Kbps using a PC86 code. In the case of transmission, 2,048 Kbps input to the clock input terminal 301 in the transmitting unit 310. The clock is applied to the first phase locked loop 315 to generate a 1,544 Kbps clock synchronized with the 2,048 Kbps clock, and at the same time, the 2,048 Kbps data inputted to the data input terminal 302 is set to the 2,048 Kbps clock. Under the control of the first buffer controller 325, the first buffer 330 is stored in a data unit of 8 bits.

At this time, the first buffer controller 325 prevents a malfunction of the PC86 encoder 335 which may appear due to a phase difference between 2,048 Kbps and 1,544 Kbps. Thus, 8-bit data stored in the first buffer 330 is stored in PC86. The encoder 335 converts the 6-bit ternary parallel data and the parallel data is converted into serial data by the second buffer 331 so that the "+" sign is the line 308 and the "-" sign is the line 309. Is applied to the bipolar driver 340 via the T1 transmission system in " + " and "-"

At this time, the disparity counter 322 has an unbalanced DC state of previously transmitted data, thereby selecting an appropriate positive and parent data to be transmitted next. The counter of disparity 322 is continuously adjusted each time data is sent.

In addition, the frame counter 320 and the frame generator 323 generate the appropriate frame bits according to the regulations used in the North American primary PCM multiplexer and insert them into the transmission data at an appropriate time. Receiving unit 350 is performed in the reverse operation order of the transmitting unit 310, the bipolar pulse received from the T1 system is the 6-bit serial "+" polar data 308 and "-" polarity by the bipolar receiver 341 The data 309 is converted into and stored in the third buffer 333, respectively. At this time, the "+" "-" polar data 308 and 309 are also applied to the clock recovery and frame synchronizer 321 so that a 1,544 Kbps clock is reproduced and frame frames sent from the transmitter are detected to perform frame synchronization. .

Appropriate timing signals from the frame synchronizer are applied to the second buffer controller 326, and by control thereof, the 6-bit data blocks sent from the transmitter are stored in the third buffer 333 exactly for each block.

The received data stored in this way is converted into 6-bit parallel data by the third buffer 333, and "+" and "-" polar 6-bit parallel data are applied to the PC86 decoder 336 so that the first parallel 8-bits in the reverse order of the transmitter. Binary data is reproduced (see Fig. 7).

The parallel 8-bit binary data thus reproduced is converted into 2,048 Kbps serial data in the fourth buffer 332 and output through the output terminal 304. At this time, the fourth buffer 332 is controlled by the second buffer controller 326.

The second phase synchronizer loop 316 generates a 2,048 Kbps clock synchronized with the 1,544 Kbps clock, and the phase difference generated therein is compensated by the second buffer controller 326 and the fourth buffer 332.

4 is a detailed view of the transmitter 310. The first buffer controller 325 includes a counter 441-443 and a plurality of gates, and the first buffer controller 325 stores 8-bit 2,048 Kbps data. The first and second buffers 330 and 331 configured as buffers 451 to 455 to prevent the PC86 encoder 335 from malfunctioning because the time to be stored makes a proper difference between the times when the PC86 is encoded and transmitted. Supply the appropriate load pulse to load.

At this time, in the first buffer 330 composed of the buffers 451-453, the buffer 451 converts the 8-bit serial data to be encoded into parallel data once, and in order to encode the same, the D-type latches 452 and 453 again. ).

The PC86 encoder 335, which consists of encoders 461 and 462, is a form in which encoding result data is stored in a ROM (Ready Only Memory) storage device.

Meanwhile, the disparity counter 470 determines whether the disparity of data to be transmitted at this time is positive or negative, and an appropriate ROM area is determined according to the output of the disparity counter 470.

In this way, the output of the disparity counter 470 and the 8-bit binary data of the D-type latch 453 serve as an address input to the ROM, and the data to be sent with a "+" pulse and "-" by this address. Data to be sent in pulses is output and stored in the buffer 331, respectively.

The buffer 454 provides a "+" pulse transmission position, and the buffer 455 provides a "-" pulse transmission position. The 6-bit " + " and "-" pulse data stored in this way are converted into serial data again as shown in FIG. 6 and transmitted to the T1 relay transmission system through the bipolar driver 340 which is a bipolar transmitter. In addition, the appropriate frame bits are generated by the gates 407 and 408 of the frame generator 323 and inserted into the transmission data at the final output stage.

The first phase synchronizer loop 315, the frame counter 320, and the bipolar driver 340 among the transmission apparatuses are not included in the scope of the present invention because general circuits used in a general transmission system may be used as they are.

5 is a detailed view of the receiver 350. The transmitter 310 receives a signal transmitted through the T1 relay transmission system, and the received signal is transmitted through a bipolar receiver 341 which is a bipolar receiver. The reduced data signal is first supplied to the clock recovery and frame synchronizer 321 to perform clock reproduction and frame synchronization necessary for the reception operation.

는 제2버퍼 컨트롤러(326)에 인가되어 버퍼제어에 필요한 타이밍이 생성된다. 한편 상기 "+"(308) 및 "-"(309)용 전송선로의 데이타는 카운터(541),(542)로 구성된 제2버퍼 컨트롤러(326)에 의해 버퍼(551∼554)로 구성된 제3 버퍼(333)에 6비트의 "+" 및 "-" 데이타별로 저장되며 이 두개의 6비트 데이타, 즉 12비트의 데이타는 PC86 디코더(336)에 있는 ROM(561)의 어드레스로 사용되어 송신한 8비트의 2진 병렬 데이타가 ROM(561)에서 재생되어 출력된다(제7도 참조).Frame sync bit

Is applied to the second buffer controller 326 to generate timing necessary for buffer control. On the other hand, the data of the transmission lines for the "+" 308 and the "-" 309 is a third buffer composed of buffers 551 to 554 by a second buffer controller 326 composed of counters 541 and 542. The buffer 333 stores six bits of " + " and "-" data, and these two six-bit data, i.e., 12-bit data, are used as the address of the ROM 561 in the PC86 decoder 336 and transmitted. 8-bit binary parallel data is reproduced and output from the ROM 561 (see Fig. 7).

This binary parallel data is stored in a fourth buffer 332 consisting of a buffer 555 and then synchronized with the received 1,544 Kbps clock, generated by the phase-locked loop 316 as shown in FIG. The original 2,048 Kbps serial binary data is reduced by the 2,048 Kbps clock.

In FIG. 5, 1CLK is a 1,544 Kbps clock reproduced from the 1,544 Kbps data inputted to the clock recovery and frame synchronizer 321, and 2CLK is 2,048 Kbps synchronized to the 1,544 Kbps generated by the second phase-locked loop 316. It is a clock.

Among the receivers, the second phase synchronization loop 316, the clock recovery and the frame synchronization unit 321, and the bipolar receiver 341 are not within the scope of the present invention because general circuits used in a general transmission system may be used as they are. Do not.

In the data transmission and reception of the transceiver, the polarity of the transmit bipolar pulse should be transmitted to the receiver as it is, which may be completely reversed according to the connection direction of the two-wire transmission line connecting the bipolar transmitter and the receiver, but it is checked only once when the transceiver is installed. This allows continuous use unless the transceiver connection direction is changed again.

In order to check the polarity when the transceiver is installed, a test switch 801 is separately placed on the transmitter 310 as shown in FIG. 8, and the data transmitted by operating the switch 801 during the polarity test is “1”. State and the receiving unit 350 checks this.

That is, the final data received by the receiver 350 is inverted by the inverter 805 and passed to the AND gate 806 to be applied to the monostable multivibrator 807, where the output of the multivibrator 807 is " If it is 1 ", it is displayed to the outside using the light emitting diode 808 so as to reverse the line connection direction of the receiver.

As described above, the present invention can transmit 2,048Kbps data of the European method to the existing T1 system used in Korea by using the PC86 code, thereby securing 64Kbps with the amount of B channel information and increasing the transmission capability of the existing transmission system. It has the advantage to make transmission error detection possible.

Claims (5)

In the multi-transfer matching method between a European primary multi-transmitter having a transmission rate of 2048 Kbps and a North American primary relay transmission system (T1 system) having a transmission rate of 1544 Kbps, a serial 2048 Kbps transmitted from the European primary multi-transmitter PC86 encoding step of converting 8-bit binary data into 1536Kbps parallel 6-bit ternary data using PC86 code, inserting 8Kbps frame data to generate 1544Kbps bipolar data, and the North American primary relay transmission. North America and Europe, comprising: a PC86 decoding step of reproducing 1544 Kbps bipolar 6-bit ternary data received from the system as 8-bit binary data, and simultaneously converting the frame data into 2048 Kbps serial data. First Multiple Transmission Matching Method In the PC86 encoding step of claim 1, the first multiplex transmission matching method in North America and Europe, which converts 8-bit 0 and 1 binary data into (-), 0, (+) ternary data. . A matching device that performs transmission and reception between a European primary multiplexer having a transmission rate of 2048 Kbps and a North American primary relay transmission system having a transmission rate of 1544 Kbps, wherein the European primary multiplexed signal of 8-bit binary data is 6-bit. Transmitting unit 310 converts the ternary data into a PC86 coded signal and transmits it to the North American primary relay transmission system, and the PC86 code signal of 6-bit ternary data transmitted from the North American primary relay transmission system. A first multiple matching device in North America and Europe, comprising a receiver 350 converting a bit binary data into a European first multiplex signal and transmitting the same to the European first multiplexer. 4. The first phase synchronizer loop 315 for generating a 1544 Kbps clock in synchronization with a 2048 Kbps clock inputted from the European primary multiplexer, and the European primary multiplexer. A first buffer 330 for storing data input at a transmission rate of 2048 Kbps from an 8-bit binary parallel data unit, and 6-bit 3 for the 8-bit binary parallel data output from the first buffer 330. PC86 encoder 335 for converting the binary data, the first buffer controller 325 to prevent the malfunction of the PC86 encoder 335 caused by the phase difference between 2048Kbps and 1544Kbps, and is output from the PC86 encoder 335 A second buffer 331 for converting the 6-bit ternary parallel data into serial data having a positive polarity and a negative polarity, and transmitting the same through the transmission lines 309 and 309, respectively; Frame bits every predetermined time by the output of the loop 315 The output of the frame counter 320 and the frame generator 232 and the second buffer 331 which are generated and inserted into the transmitted data and the output of the second buffer 331 determine whether the disparity of the next data to be transmitted is in the normal mode or the parent mode. Disparity counter 322 for controlling the PC86 encoder 335 and a bipolar driver 340 which is a bipolar transmitter for transmitting the output of the second buffer 331 to the North American primary relay transmission system. First multiplex transmission matching device in North America and Europe, characterized in that it comprises. 4. The receiver of claim 3, wherein the receiver 350 separates the 1544 Kbps bipolar 6-bit ternary data signal inputted from the North American primary relay transmission system into (+) polarity data and (-) polarity data. A bipolar receiver 341, a clock recovery and frame synchronizer 321 which receives an output of the bipolar receiver 341, recovers a clock of received data, and synchronizes frame bits, and the clock recovery and frame synchronizer ( A third buffer 333 for storing the output signal of 321 for each of (+) polarity and (-) polarity; and a PC86 decoder 336 for reproducing two outputs of the third buffer 333 as 8-bit binary parallel data. ), A fourth buffer 332 for converting and storing the output of the PC86 decoder 336 into 2048 Kbps serial data, and the third buffer 333 in synchronization with the clock recovery and frame synchronizer 321. And a second buffer controller 326 for controlling the fourth buffer 332. And a second phase synchronizer loop 316 for generating a 2048 Kbps clock in synchronization with the 1544 Kbps clock generated by the clock recovery and frame synchronizer 321. .

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