KR910007445B1 - Printer head pin driving circuit by dma method - Google Patents

Abstract

The circuit drives the head pins (H1-16) with the font data supplied from a microprocessor having a direct memory access function so that the high speed typing is performed without heavy load of the CPU. The circuit comprises a DMA controller (10) transmitting the data stored in the memory directly to the I/O device, a flip-flop (30) dividing a DMA acknowledge signal (DMA ACK) to two with the outer ready signal, a latch (20) latching the even data supplied from the controller with the output of the flip-flop as a clock signal (CLK), a latch (21) latching the odd data, and a trigger pulse generator (40) providing trigger pulse for driving the head pins with the data stored in the latches.

Description

DMA printhead pin drive circuit

1 is a circuit diagram of the present invention.

2A to 2E are timing charts for explaining the present invention.

* Explanation of symbols for main parts of the drawings

10: DMA control logic 20, 21: latch

30: J-K flip-flop 40: trigger pulse generator

H ₁ ... H ₁₆ : Printhead pin

Q ₁ ... Q ₁₆ : Printhead Driving Transistor

The present invention relates to a printhead pin driving circuit of a printer, and more particularly to a circuit for driving a printhead pin of an impact dot matrix printer at high speed without load on the CPU.

The impact dot matrix printer is a device for forming a font by driving printhead pins arranged in rows 1 to 2 in accordance with fonts according to the shape of a letter. A conventional method of driving printhead pins is to drive printhead pins. Using the output of the counter corresponding to the frequency as the interrupt request of the CPU, the interrupt terminal CPU reads the font data and directly drives the printhead pin. Such a method, however, has a disadvantage of slowing down the processing speed of the CPU because it puts a load on the CPU.

Accordingly, an object of the present invention is to drive printhead pins with font data using a microcomputer with a built-in DMA (Direct Memory Access) function, which transfers the data in the system's memory to the input / output device without the CPU. It is to provide a printhead pin driving circuit that can reduce the load on the CPU by performing the DMA method to achieve a high processing speed.

Hereinafter, the configuration and effect of the present invention will be described in detail.

The present invention includes a first means for checking an external ready signal to transmit a data available signal and a predetermined number of data, and storing the data transmitted from the first means to store the printhead pin. A second means for driving, a third means for dividing the data available signal to be supplied to the second means, and a fourth means for providing an output enable signal to the second means. do.

The first means according to the present invention uses a microcomputer with a built-in DMA function as a CPU, or is composed of a dedicated DMA controller. Hereinafter, in the present specification, the DMA control logic 10 is abbreviated.

)(Q)은 래치(20)(21)의 클럭단자(CLK)에 각각 연결되어 있다. 래치(20)(21)의 각각의 출력단에는 다수의 프린트헤드핀(H₁...H₁₆)을 구동시키기 위한 트랜지스터(Q₁...Q₁₆)가 연결될 수도 있다.The second means may be composed of at least two latches 20, 21, and the third means may be composed of at least one JK flip-flop 30, the output of the JK flip-flop 30. (

Q is connected to the clock terminals CLK of the latches 20 and 21, respectively. Transistors Q ₁ ... Q ₁₆ for driving a plurality of print head pins H ₁ ... H ₁₆ may be connected to each output terminal of the latches 20, 21.

)단자에 펄스를 제공하여 래치된 데이터가 트랜지스터(Q₁...Q₁₆)를 구동시키도록 한다.The fourth means may be constituted by a trigger pulse generator 40 for generating a triggered pulse, which is generated by the output of the JK flip-flop 30 and the data D ₀ ... D _7. Output enable signal of latches 20 and 21 immediately after latch is latched to latches 20 and 21

A pulse is applied to the terminal to cause the latched data to drive transistors Q ₁ ... Q ₁₆ .

Looking at the operation of the present invention configured as described above are as follows.

First, a CPU (not shown) passes a start address and a transfer count of data to be transferred to the DMA control logic 10. At this time, the DMA controller 10 checks the external ready signal READY (FIG. 2a) input to the DMA request terminal DMA REQ, and if it is in the radiated state, the DMA controller 10 outputs the data available signal (FIG. 2b). At the same time as the JK flip-flop 30 through the terminal (DMA ACK), one-byte data in the memory is transferred to the latches 20 and 21 to reduce the transfer count.

The data transmitted to the inputs of the latches 20 and 21 is latched by the JK flip-flop 30 to the first (even) byte in the latch 20 (figure 2d, and the next odd data transmitted is latched) 21) (Fig. 2c).

)에 공급된다.The printhead pins H ₁ ... H ₁₆ are driven by the turn-on action of the transistors Q ₁ ... Q ₁₆ immediately after being latched to the latches 20 and 21 by two data available signals. In order to be turned on for at least 200 ... 300 μs, the pulse (trigger 2e) triggered by the trigger pulse generator 40 is applied to each of the output enable terminals of the latches 20 and 21.

Is supplied.

)에 트리거된 펄스가 인가되면, 래치(20)(21)의 출력신호는 트랜지스터(Q₁...Q₁₆)의 베이스에 인가된 뒤 프린트헤드핀(H₁...H₁₆)을 구동하게 된다.Output enable terminal of latches 20 and 21

) If the pulse is applied, the latch 20, 21 output signal is a transistor (the back printhead pin (H ₁ ... H ₁₆₎ applied to the base of Q ₁ ... Q ₁₆₎ of the trigger to the drive Done.

The above-described process is repeated until the transfer count becomes 0. The CPU checks whether the transfer count is 0 or not and initializes the next block of data to be transmitted.

The present invention operating as described above transfers the data in the memory directly to the latch for driving the printhead pin without the CPU by using the DMA method, compared to the conventional method in which the CPU directly drives the printhead pin by an interrupt every time. By reducing the load on the CPU by running the drive has a feature that can perform high-speed processing.

Since the present invention assumes a printhead of 1 pin to 16 pins, only two latches and one divider circuit are shown in FIG. 1, but the present invention is not limited thereto. It can be seen that it may be composed of a divider circuit and a latch required for driving.

Claims (1)

A plurality of print head pins (H ₁ ... H ₁₆ ) are provided with a direct memory access controller 10 for transmitting data stored in the system memory of the printer to an input / output device directly without publishing a central processing unit. A printhead pin driving circuit using a DMA method, comprising: a flip-flop 30 for dividing a DMA activating signal (DMA ACK) generated by the direct memory access controller 10 by an external radiant signal into two; ; A latch 20 for temporarily storing and outputting even-numbered data among the data output from the direct memory access controller 10 by using the signal output from the flip-flop 30 as a clock signal CLK; A latch 21 for temporarily storing and outputting odd-numbered data; The output enable signal is provided to the latches 20 and 21 to simultaneously output the head pin driving data temporarily stored in the latches 20 and 21 to the head pins H ₁ ... H ₁₆ . A printhead pin drive circuit according to the DMA method, characterized by comprising a trigger pulse generator (40) for generating a trigger pulse.

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