KR910005467B1 - Date link matching system in electronic exchange - Google Patents

Abstract

The unit is to realize the level 1 function of the bearer system having level 1-level3 functions. The unit includes a terminal interface unit (320) for communicating data between terminals with certain transmission, a multiplexer and de-multiplexer (235) for matching the transmission speeds of the terminals and a time switch a parity checking unit (330) for adding the odd or even parity bit on the transmission data and for checking the parity bit of the received data, a dual control unit (340) for supervising the reference clock supply to the multiplexer/ demultiplexer and for transmitting error message to a teminal master (245), a loop- back test unit (315) for comparing the transmitting data and receiving data to check the error occured during the transmission and a terminal master connecting unit (310).

Description

Data link matching device of electronic exchange

1 is a functional configuration diagram of a data link of the present invention, in which FIG. 1a is a digital signal data link configuration via a digital switch block, and FIG. 1b is an interface device.

2 is a block diagram of an application within an exchange of a data link matching device according to the present invention.

3 is a functional block diagram of a data link matching device of the present invention.

4 is a timing diagram for converting 64 Kbps data and 56 Kbps data. FIG. 4A is a timing diagram of a transmitter data link. 4b is a timing diagram of a data link upon reception.

5 is a timing diagram of transmission rate conversion between a multiplexer and a demultiplexer matching circuit, and FIG. 5a is a timing diagram of a transmitter data link. 5B is a timing diagram of a receiver data link.

* Explanation of symbols for main parts of the drawings

200: redundancy device 240: data link matching device

201-232: Signal terminal 250: Time switch unit

245: signal terminal master 255: trunk unit

310: signal terminal master connection 315: loop back test control circuit

320: signal terminal connection unit 325: multiplexer and demultiplexer

340: redundancy control circuit

The present invention relates to a data link matching device among NO.7 common line signaling devices of an electronic switch, and in particular, a bearer system having a level 1-level 3 function in an electronic switching system using a data communication protocol having a hierarchical structure. The present invention relates to a data link matching device of an electronic exchange for realizing a level 1 function. In general, a signal data link is a bidirectional signal transmission path composed of two data channels operated at the same data rate, and is roughly divided into a digital signal data link and an analog signal data link. Since the analog signal data link matching device must perform a matching function with a modem, only the digital signal data link matching device is considered except in the present invention. The present invention has the object to provide a matching device for providing the digital signal data link function as described above with reference to the accompanying drawings as follows.

The digital signal data link matching device of the present invention is shown in FIG. 1, and FIG. 1 a shows a digital signal data link via a digital switch block, and FIG. 1b shows a digital signal data link via an interface device. The digital signal data link is composed of a digital transmission channel, a terminal device providing an interface to a digital switch and a signal terminal. The standard transmission rate is 64 Kbps (bit per sec).

Currently, the digital path having a transmission rate of 2,048 Kbps is used to operate at 64 Kbps using the 16th time slot. However, in the case of the 1,544 Kbps digital path, the operation at 64 Kbps or 56 Kbps depends on whether a clear channel is provided. It was made possible. 2 shows a data link matching device of the present invention. The data link matching device 240 is a 32-channel unit for data link output from each signal terminal 202-232 performing the level 2 function of the digital electronic switching system. After multiplexing to 2,048Nbps signal group, it is applied to the input terminal of the time switch unit 250, but under the control of the signal terminal master 245, through the desired trunk unit of the trunk unit 255, the interface of the digital electronic exchange. It performs Level 1 function to send signal message to counter exchange.

The data link matching device 240 is a physical data link 242a-242n of 64 Kbps connected to the signal terminals 201-232 and a 2 Mbps Pulse Code Modulation (PCM) connected to the time switch unit 250. It performs transmission rate matching function between highways and operates in conjunction with the signal terminal master 245 to improve the reliability and maintenance function of the system.

In addition, the data link matching device 240 is supplied with a reference transmission clock 241 of 64KHz 56KHz to the signal terminals 201-232 for the transmission rate matching function, and 32 64Kbps data links 242a-242n streams. And the multiplexing and demultiplexing functions between the PCM highway 251 of 2 Mbps and the data link matching device 240 from an arbitrary signal terminal 201-232 for performing a maintenance function of the system. It is possible to verify the abnormality of the apparatus by looping back only the corresponding channel in the step before being sent to the time switch unit 250 without passing through the time switch unit 250 for the output data. Active / Standby type redundancy device 200 is used for automatic switching in case of system failure and the addition and extraction of parity bits are performed for the integrity of transmitted data. It is done.

3 is a functional block diagram of the present invention, the signal terminal master connection portion 310 is a redundancy control circuit 340 and a loop back test control circuit 315 and a signal terminal master 245 for performing various maintenance functions of the apparatus. Provide communication function between

The redundancy control circuit 340 controls to selectively operate one of the boards of the thickness of the data link matching device 240, the supply state of the reference clock (56 / 64KHz) and the parity addition and extraction circuit 330 Parity bit reception status, frame synchronization from time switch and 2MHz clock reception status, reference clock supply status of multiplexer and demultiplexer 235, etc. are monitored to automatically switch to standby module when an error occurs. ) To report the transfer factor to the signal terminal master (45). At this time, the signal terminal master 245 takes necessary measures according to the switching factors.

In addition, the redundant switching between the operation and the standby (Active / Standby) module can be forcibly performed by the signal terminal master 245 and the loop back test control circuit 315 is transmitted under the command of the signal terminal master 245 N-signal is used to generate a signal that opens and closes a gate circuit that becomes a data path between a 2Mbps input link signal link and a 2Mbps output link signal link of a time switch so that a time slot and a receive time slot can be connected. By checking whether the data received and transmitted by the terminal is the same as the received data, check whether the data is correctly transmitted from 330 → 325 → 330, determine whether there is an error on the data link transmission path, and simultaneously detect the location of the error. have.

The pirithm bit addition and extraction circuit 330 performs a function of adding a piriti bit to the transmitted data or checking the piriti bit of the received data in order to detect and retransmit an error occurring during data transmission.

At this time, whether to use EVEN parity or ODD parity is configured to be hardware-selectable in the device as required by the system. The signal terminal connection unit 320 of FIG. 3 is responsible for providing various signals so that 32 signal terminals can transmit and receive NO.7 signal data at a specified transmission rate.

Since the signal terminals 201-232 physically transmit and receive data of 64 Kbps rate with the data link matching device 240, FIG. 4A when transmitting 56 Kbps data in the signal terminal as shown in FIG. 4A when transmitting and receiving 56 Kbps data. As shown in FIG. 6, dummy bits are added to valid data of 56 Kbps in the signal terminal, converted into 64 Kbps data, and transmitted to the data link matching device 240.

On the contrary, when the signal terminals 201 to 203 receive the data, they are configured to receive valid data of 56 Kbps rate from which the dummy bit is extracted from the 64 Kbps rate data as shown in FIG. 4B. According to the matter, the configuration of the flexware in the signal terminals 201-232 was changed to improve the ease of selection and the reliability.

Meanwhile, the signal terminal connection unit 320 supplies a 64/56 KHz clock signal necessary for performing such a function to the signal terminal, but may be 48 Kbps depending on the requirements of the system.

The logic circuit for clock generation is configured in the signal terminal connection unit 320 and generates a 64/56 KHz clock signal by the frame synchronization signal 253 and the 2 MHz signal 251 provided from the time switch 250. Supply to (201-232).

As described above, timing diagrams for mutual conversion to 64 Kbps data and 56 Kbps data are shown in FIGS. 4A and 4B.

The multiplexer and demultiplexer 325 performs a function of matching the transmission speeds of the signal terminals 201-232 and the time switch 250. The transmission speed of the signal terminals 201-232 is 64 Kbps, but the time switch 250 Since the transmission rate is 2,048 Mbps, the serial input data of 32 signal terminals are multiplexed into 32 channels so that the data of the signal terminal 201 is set to the time slot 0 of the input link terminal of the time switch 250, and the signal terminal ( The data of 202 is carried out in timeslot no. 1 so that the data of the last signal terminal 232 is loaded in timeslot 31 and transmitted.

In reverse operation, data is demultiplexed at the output link terminal of the time switch 250 such that the data of the timeslot 0 is transmitted to the receiving data link of the signal terminal 201 and the data of the timeslot 1 is the signal terminal. The data of timeslot 31 is transmitted to the received data link of 202, and so on to the received data link of signal terminal 232.

The rate matching function described above is performed by a 128 KHz clock (FIG. 5) made in the multiplexer and the demultiplexer 325.

The multiplexer is a circuit that multiplexes 32 signal links of 64Kbps speed transmitted by signal terminals into serial input data and converts them into parallel output data. The multiplexer is configured as a gate array to improve reliability. The demultiplexer is a data link. A circuit for demultiplexing the input data of 2,048 Mbps speed received by the contention device 240 to 64 Kbps, which is the reception speed of signal terminals, is configured as a gate array like the multiplexer.

The timing diagram of the matching circuit transmission speed conversion of the multiplexer and the demultiplexer 325 is shown in detail in FIG. 5.

As described above, the present invention compares the data transmitted / received by the signal terminal to determine whether an error occurs and at the same time detects the position of the error, thereby making it easy to maintain the system, and according to the requirements of the system. By changing the firmware configuration, it is possible to improve the ease of choice and reliability.

Claims (3)

In the common line signaling device of an electronic switch, a signal terminal connection unit (320) for transmitting and receiving data to and from the signal terminals (201 to 232) at a predetermined transmission rate, and the transmission rates of the signal terminal and the time switch (250) Matched multiplexer and demultiplexer 235, and even or odd parity bits are added to the transmitted data for detection of errors occurring during data transmission and retransmission of data, and parity added for checking parity bits of the received data. And redundancy that monitors the parity bit reception state of the extraction circuit 330, the parity addition and extraction circuit 330, and the reference clock supply state of the multiplexer and demultiplexer 325 and reports to the signal terminal master 245 when an error occurs. The control circuit 340 and the data transmitted from the signal terminals 201 to 232 compare with the received data to generate an error on the data link transmission path. A loop back test control circuit 315 for discriminating a fault and detecting an error occurrence position, and the redundancy control circuit 340 and the loop back test control circuit 315 and the signal terminal master to perform various maintenance functions. And a signal terminal master connection unit 310 for providing communication therebetween, before being transmitted to the time switch without passing through the time switch 250 for data output from the signal terminal to perform a maintenance function. The data link matching device of an electronic exchange, characterized in that only the corresponding channel is loop-backed to verify the abnormality of the device, and it is operated by redundancy of operation and standby type and is automatically switched in case of an error. 2. The data link matching device of claim 1, wherein use of even parity or odd parity is hardware-selected as necessary, and the parity is used as a source signal for maintenance of the device. According to claim 1, The reference clock is a signal required for accepting a data link of 64/56 Kbps according to the configuration of the signal network and whether or not to provide a clear channel is supplied to each signal terminal for each signal is converted to the corresponding transmission rate and 48Kbps And a data link matching device of an electronic exchange.

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