KR900010751Y1 - Timer operation playing circuit - Google Patents

Abstract

No content.

Description

Timer Regeneration Circuit

1 is a circuit diagram showing an embodiment of the present invention.

2 is a conventional circuit diagram.

* Explanation of symbols for main parts of the drawings

M: Memory MC: Grain Detection Control Circuit

S ₉ : switch C ₁₀ : capacitor

IC: Logic Control Circuit

The present invention relates to a timer operation reproducing circuit of a reproducing apparatus such as a CD (compact disc) or a cassette tape, in which a plurality of pieces of information are stored in a recording medium.

Conventionally, there is a cassette record tape as a recording medium on which a plurality of pieces of information, for example, music pieces, have been recorded. A reproducing apparatus for program reproduction of several pieces of music recorded on a cassette record tape in a predetermined order has been constructed as shown in FIG.

In FIG. 2, when the switch S ₁ is turned on, the power supply VDD of the "H" level is applied to the input terminal FF of the integrated logic control circuit IC, thereby outputting the flip-flop FF ₁ ( Q) becomes the "H" level, and the output terminal RM + of the logic control circuit IC becomes the "H" level. The transistors Q ₁ and Q ₂ of the motor drive circuit are turned on and the reel motor RM rotates in the forward direction and sends the tape quickly. When the switch S ₂ is turned on, the input terminal REW is at the "H" level and the output Q of the flip-flop FF ₂ is at the "H" level, so the output terminal RM- is at the "H" level. It becomes Then the transistors (Q _3, Q ₄₎ of the motor driving circuit (MD) is turned ON, and the reel motor (RM) is to reverse wind the tape again. When the switch S ₃ is turned on, the input terminal PLAY is at the "H" level, the output Q of the flip-flop FF ₃ is at the "H" level, and the output terminals RM + and (RM CONST) are respectively. It becomes the "H" level. As a result, the transistors Q ₁ and Q ₂ are turned on to rotate the reel motor RM forward and to turn on the output terminal transistor Q ₅ . Therefore, the reel motor RM rotates in the forward direction at a low speed and runs the tape at constant speed. When the switch S ₄ is turned on, the power supply VDD having the "H" level is supplied to the input terminal STOP, and each of the flip-flops FF ₁ to FF ₃ is reset, and all of the outputs Q are At the "L" level, therefore, the output terminals RM +, RM-, and RM CONST are also at the "L" level.

The multi-pressure inhibiting circuit MPH resets all flip-flops except for the flip-flop corresponding to the switch that is turned on first.

Next, the operation of the intermission detection (MQS) of several songs recorded on the cassette record tape will be described. When the switch S ₈ is turned on and the power supply VDD of the "H" level is applied to the input terminal PROGRAM, the counter C counts up one by one. When the switch S ₇ is turned on at this time, the data of the counter C is stored in the memory M, and the data of the counter C is reset. When this is repeated, the data of the counter C is stored in the memory M in sequence.

When the switch S ₅ is turned on while each data is stored in the memory M, the input terminal MQS START is at the "H" level, and this "H" level is the START terminal of the intermission detecting control circuit MC. Is applied to. The grain stem detection control circuit MC outputs the "H" level to the MQS OUT, and prohibits the input of the switches S ₁ to S ₃ . Then, the intermission detecting control circuit MC sets REW OUT to " H " level and reversely rotates the reel motor RM to wind the cassette record tape back to the beginning, and then read the first data of the memory M. Next, the intermission detecting control circuit MC sets FF OUT to " H " level, inputs information of the cassette record tape reproduced by the playback head PBH to SIGNAL IN, and reads the level of the playback signal. With or without the playback signal, the intermission detecting control circuit MC detects the intermission and sends the cassette tape as much as the contents of the data input to the DATA IN in the memory M. Next, the intermission detecting control circuit MC sets the PLAY OUT to " H " level, and puts the tape in the playback state. When the performance of this song is finished, the intermission detection control circuit MC reads the next data in the memory M. Next, the data is compared with the previous data, and REW OUT or FF OUT is set to the "H" level, and the intermission is detected, the tape is sent as fast as the difference of the compared data or the road is wound, and then the PLAY OUT is set to the "H" level. The tape is in a playback state. The above operation continues until all the data in the memory M are finished. When all the data has been decoded, the intermission detection control circuit MC outputs "L" to the MQS OUT and permits input of the switches S ₁ to S ₃ . When the switch S ₆ is turned on during the intermission detection, the power supply VDD of the "H" level is applied to the input terminal MQS STOP, and the intermission detection control circuit MC which inputs this to the STOP level sets the MQS OUT to the "L" level. The input of the switches S ₁ to S ₃ is allowed.

Next, the MQS timer operation reproduction will be described. When the timer regeneration switch S ₉ is set to ON and the set timer time elapses, the power supply VDD is changed from the "L" level to the "H" level. As a result, the timer terminal TIMER of the logistic control IC becomes “H” level for a moment due to the differential operation by the capacitor C ₁ and the resistor R ₁ . This " H " level pulse signal causes the intermission detection control circuit MC to set the TIMER OUT to " H " level, set the flip-flop FF ₃ , and outputs the " H " level from the output Q to reel. The motor RM is brought into the regeneration state. The power supply VDD is turned off during the timer set, and data stored in the memory M before the timer set is erased. Therefore, after the timer time has elapsed, the program cannot be played back and playback starts from the tape position immediately before the timer set.

In the above conventional timer operation reproducing circuit, when the timer is set, the data of the memory storing the intermission for program reproduction is canceled by turning off the power, and the program reproducing based on the memory cannot be performed after the timer set time has elapsed.

The present invention eliminates the above problems and provides a timer operation reproducing circuit capable of reproducing a program on the basis of data between pieces of music stored in a memory even when playback is started by a timer operation.

The timer operation reproducing circuit of the present invention comprises a storage means for programming a reproducing procedure of a recording medium in which a plurality of pieces of information have been stored in advance, reproducing means for reproducing according to the program of the storage means, and a timer operation by means of a timer operation. A timer control circuit for reproducing, the storage means for holding the contents of the storage means even when the power supply of the reproducing means is turned off, and the reproducing means in the reproducing state by the timer operation reproducing is the storage means. And control means for controlling playback according to the program stored in the program.

The present invention makes it possible to maintain the memory of the storage means during the timer control operation, so that the program can be reproduced after the timer set time of the timer control circuit has elapsed.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals are used to designate like parts in FIG. 2 and the description thereof will be omitted.

In FIG. 1, this embodiment is the connection point of the connecting through a diode (D ₁₀₎ the power supply VDD between the power supply terminal VDD ₁ of the logic control circuit (IC) and a diode (D ₁₀₎ and a power supply terminal (VDD ₁₎ A large capacity capacitor (C ₁₀ ) is connected between ground and ground. Capacitor C ₁₀ holds data in memory M of logic control circuit IC by its charging potential when power supply VDD is turned off.

The timer regeneration switch S ₉ is set to ON, and when the set timer set time elapses, the power supply VDD is changed from the "L" level to the "H" level. During this rise, the differential terminal operation of the capacitor C ₁ and the resistor R ₁ causes the timer terminal TIMER of the logic control circuit IC to be at the “H” level for a moment.

When the "H" level pulse signal is received and the TIMER IN becomes "H" level, the intermission detection control circuit MC checks the contents of the memory M. If the data is stored, the intermission detection control circuit MC stores the contents in the memory M after the intermission detection operation. The tape is played back in accordance with the intermission information, and if the data is not stored, the TIMER OUT is set to the "H" level, which sets the flip-flop FF ₃ to play the tape.

Even when such a power supply VDD is turned off and is at the "L" level, the charging potential of the capacitor C ₁₀ is applied to the power supply VDD ₁ of the logic control circuit IC, and the data in the memory M can be maintained as it is.

Therefore, after the timer set time has elapsed, the program reproduction according to the storage data of the memory M can be performed.

In addition, when the power supply VDD is turned off, the capacitor C ₁₀ that retains the memory contents of the memory M is large in capacity, and furthermore, if the logic control circuit IC is configured by C-MOS, the holding time is extremely long, and the normal timer setting is performed. Because it can cope with time enough, there is no practical problem.

Although the cassette record tape has been described in the above embodiment, the present invention is not limited to this, but it can of course also be realized in a recording medium such as a CD (compact disc).

As described above, according to the present invention, the program can be reproduced in accordance with the data between the songs stored in the memory even in the reproduction by the timer operation.

Claims (1)

Storage means M for programming reproduction of the recording medium on which a plurality of pieces of information have been recorded in advance; reproducing means MC, PBH, MD, RM for reproducing based on the program of the storage means M; and the reproducing means. In the timer operation reproducing circuit having a timer control circuit C ₁ , R ₁ , S ₉ which enables (MC, PBH, MD, RM) to regenerate timer operation by a timer operation, the storage means M Memory holding means (C ₁₀ ) which retains the stored contents even when the power supply is turned off, and the reproducing means (MC, PBH, MD) which are put into a regenerating state by the timer control circuits (C ₁ , R ₁ , S ₉ ). And RM has control means for controlling playback in accordance with a program stored in said storage means (C ₁₀ ).