KR900007909B1 - Method of selecting mode in automatic track detection - Google Patents

Abstract

A circuit comprises an automatic track detection control circuit (30) , shift registers (35,40), comprising a plurality of flipflops (FF1- FF10), for providing the delayed output in regular order, a plurality of gates for converting the outputs of shift registers into a long- time mode signal (EP1) and a regular-speed mode signal (SP1), and an output signal discriminator (50) for providing a mode decision signal (MS).

Description

Automatic mode selection of automatic track detection system

1 is a circuit diagram of the present invention.

2 is a control circuit diagram for automatic track detection of the present invention.

3 is an output waveform diagram of a shift register during a long time mode reproduction of a constant speed mode recording tape.

* Description of the main parts of the drawings

1: Low pass filter 2: Balance modulator

3,4: Band pass filter 5,6: Peak value detector

8,9: sample and hold unit 10: error signal detection unit

11,12 buffer 18 divider

21,22: Delayer 30: Control circuit for automatic track detection

35,40: shift register 45: logic signal control unit

스크루시버 오아케이트50: Output signal discrimination unit EXOR:

Scrubber Oakate

FF ₁ , FF ₂ , FF ₃ . Flip-flops O ₁ , O ₂ , O ₃ . Oagate

EP ₁ : long time signal SP ₁ : constant speed signal

HP: Head Switching Signal TP: Trajectory Determination Signal

25: Tape trajectory determination unit 15, 16, 17: Monostable multivibrator

The present invention relates to a method for automatically selecting a mode of an automatic track detection system in a recording / playback apparatus employing an automatic track finding system, which automatically selects a constant speed SP and a long time mode EP. will be.

In VTRs, the automatic track detection system records video and pilot signals in sequence on video tracks in order to ensure that the video head accurately tracks recorded tracks on tapes that have already been recorded. The capstan motor is controlled by the tape trajectory determination signal that detects the pilot signal, so that the video head accurately tracks the recording track, but the constant speed SP and the long time EP during recording and playback functions are separate switches. Since each mode is selected to be mixed with each mode on the video tape, the switch has to be switched to match the recorded mode during playback. Constant speed (SP) and long time (EP) It was necessary to switch to.

It is an object of the present invention to automatically select a mode for automatically switching the mode of a recording and playback device by generating a mode determination signal for distinguishing a long time mode and a constant speed mode during playback using a tape trajectory determination signal of an automatic track detection system. To provide a method, a rising edge of a headswitching signal is compared to a pilot signal recorded with a video signal on a video tape and a reference frequency, and a tape trajectory determination signal for capstan motor is reproduced as an input signal. The output of the shift register is output through the shift register according to the time and the falling edge, and the output of the shift register is output as the mode determination signal MS through the logic circuit, respectively, so that the mode of the recording / reproduction device VTR is It is automatically switched to the long time mode.

This will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of the present invention, the output of the tape trace determination signal TP of the automatic track detection control circuit 30 to which the head switching signal HP is applied is a flip-flop FF of the shift registers 35 and 40. ₁ ) (FF ₆ ) is configured to be applied to the input terminal (D), the clock signal of the shift register 35 is configured to be applied to the head switching signal (HP) and the clock signal of the shift register 40 is an inverter The head switching signal HP inverted in (I ₁ ) is configured to be applied.

The shift registers 35 and 40 are composed of five D-flip-flops FF _{1 to} FF _10, respectively, so that the locus determination signal TP is delayed by one clock every time the head switching signal HP is applied. After configured to be output to the output of the shift registers 35, 40 is configured to be output to the logic signal control section 45 consisting of the AND gate (A _{1 ~} A ₈ ) and the ora gate (O ₁ ~ O ₆ ) The long time mode signal EP ₁ and the constant speed mode signal SP ₁ output from the logic signal controller 45 are an inverter I ₂ , an end gate A ₉ to A ₁₂ , and an ora gate O ₇ (O ₈ ). ) Is configured to be applied to the output signal discrimination unit 50 composed of the flip-flop FF ₁ and output as the mode determination signal MS.

Here, the inverting of the inputs of the AND gates of the logic signal controller 45 is configured to combine the output signals of the shift registers 35 and 40 to output a constant logic signal.

EP ₁ : Long time signal, SP ₁ : Constant speed signal, EP / SP: Mode selection signal during recording, REC recording signal, PSW: Power on signal

FIG. 2 shows the automatic track detection control circuit 30 of FIG. 1, which is a known technology.

That is, the output of the error signal detection unit 10 is configured to be applied to the tape trajectory determination unit 25 so that the reference frequency of the reference frequency generator 14 can be converted into the output fed back by the control of the timing generator 20. The error signal detector 10 includes a pilot signal (low frequency signal) included in the high frequency signal (RF) applied from the video head through the low pass filter (1) in the reference modulator (2). The difference frequency is configured to be compared to the output of and is applied to the peak-to-peak detectors 5 and 6 through the band pass filter 3 and 4.

스크루시버 오아게이트(EXOR)의 출력이 지연기(21)(22)를 통하여 기준 주파수 발생기(14)의 기준 주파수가 출력되게 구성한 것이다.The tape trace determining unit 25 is configured such that the output of the OP amplifier 7 is output from the sample and hold units 8 and 9 to the buffers 11 and 12, and the constant speed mode signal PBH and the head switching signal. After the frequency divider 18 and the monostable multivibrator 15, 16, 17 are controlled by HP, the sample and hold unit 8, 9 is configured to be driven.

The output of the screwdriver orifice EXOR is configured such that the reference frequency of the reference frequency generator 14 is outputted through the retarders 21 and 22.

Referring to the operation of the automatic track detection control circuit 30 shown in FIG. 2 according to the present invention configured as described above, the recorded video tape has four pilot frequencies f _{1 to} f _{4 for} each field of the image. One signal is recorded sequentially, and the above four pilot signals are sequentially applied from the high frequency signal RF obtained from the head at the time of reproduction.

That is, it is selected according to the input signal of the reference signal PR ₁ (PR ₂ ) applied to the reference frequency generator 14 and is selected as f ₄ -f ₃ -f ₂ -f ₁ -f ₄ . Are output from the reference frequency generator 14 to the balance modulator 2 in the order of.

Therefore, when the pilot signal of the reference frequency generator 14, the reference pilot signal, and the high frequency signal RF applied from the head are applied through the low pass filter 1 in the balance modulator 2, 47 KHZ is balanced. The frequency signal of the component and the frequency signal of the 16 KHZ component are output, and the output signal is applied to the peak value detection section 5, 6 through the band pass filter 3, 4, and then the peak values of the two components are OP amplifiers. It is compared in (7).

At this time, in order to appropriately change the order of the reference frequencies applied, the recording frequency is applied in reverse order to the order in which the recording frequencies are applied, and the reference frequency is output by delaying a predetermined time (2 to 4 ms) for output. When f ₁ ) is applied, the difference frequency of the reference frequency (f ₄ ) that is delayed for a certain time is 47 KHZ, and this signal component is applied to the non-inverting terminal (+) of the OP amplifier (7) to output high potential. (H output) is obtained, and the sample is held by the low potential (L output) of the single-safety multivibrator 16 in a timing of 2 to 4 ms, and then held to maintain the track determination signal (H level) of the tape for one field. do.

That is, the output of the peak detection unit 5, 6 is applied with a difference frequency of 16 KHZ to the inverting terminal (-) of the OP amplifier 7 and a difference frequency of 47 KHZ to the non-inverting terminal (+). The output of the capstan motor is controlled by the sample and hold section 9 through the buffer 12 for each field.

In addition, the reference frequency output, which was conducted at the time of constant speed reproduction, is obtained by delaying the head switching pulse (HP) for 2-4 ms. If the output of the OP amplifier 7 is sampled and held within this time, a pilot obtained from the video head is obtained. An output that determines the order of frequency components and reference frequency components can be obtained. When the output of the single-safety multivibrator 16 is in a low potential state, it is a point of time controlled by a signal that judges the path of the tape. It is possible to compare the difference signal accurately by the output.

The track determination signal TP of the tape supplied to the shift registers 35 and 40 in the automatic track detection control circuit 30 is "H" or "L" level when the head tracks the normal track of the tape. When the head is out of the normal track (e.g. when playing a constant speed (SP) recording tape for a long time (EP)), the status signal changes to L → H or H → L level. The status signal changes every field or two to three fields of the recorded video signal.

The transition (L → H or H → L) of the tape trace determination signal TP has regularity, and according to the present invention, the tape trace is determined for each track of five fields to determine the mode.

For example, if the tape trace determination signal TP is generated as H × L × H or L × H × L, it is determined that the long-term mode (EP) recording tape is reproduced by the constant speed mode SP, and HH ×× LL × If it occurs at x HH or LL x HH x LL, it is judged that the constant speed mode (SP) recording tape is reproduced by the mode EP for a long time. Where x is don't care.

As described above, the automatic track detection control circuit 30 outputs different tape trajectory determination signals TP according to the recording and playback modes of the tape, and the tape trace determination signals TP are shift registers 35 and 40. Is applied to the input terminal D of the flip-flop FF ₁ (FF ₆ ), and as shown in FIG. 3, the head switching signal HP is the flip-flop FF _{1 to} FF of the shift register 35. ₅ is applied to the clock terminal ▷ of the shift register 40 and then inverted by the inverter I ₁ and applied to the clock terminal ▷ of the flip-flops FF _{6 to} FF ₁₀ of the shift register 40.

Accordingly, the shift register 35 composed of _five D-flip flops FF _{1 to} FF ₅ reads and shifts the tape trajectory determination signal TP at each falling edge of the head switching signal HP. In the shift register 40 composed of two D-flip flops FF _{6 to} FF ₁₀ , the tape trajectory determination signal TP is read and shifted at each rising edge of the head switching signal. The outputs Qa _{1 to} Qa ₅ (Qb _{1 to} Qb ₅ ) of 40 are applied to the logic signal control unit 45.

As such, the output relationship of the shift registers 35 and 40 to the head switching signal HP and the trajectory determination signal TP is illustrated in FIG. 3, and the waveform diagram of FIG. 3 is a constant speed mode. (SP) It is a case where the recording tape is reproduced by the long time mode EP, and at this time, the trajectory determination signal TP is assumed to be output as HH ×× LL ×× HH, and × is indicated as “L”.

In this way, in each flip-flop FF _{1 to} FF ₅ of the shift register 35, the outputs Qa _{1 to} Qa ₅ which are sequentially delayed by the head switching signal HP and the trajectory determination signal TP are obtained. The outputs Qb _{1 to} Qb ₅ are also obtained from the pull-flops FF _{6 to} FF ₁₀ of 40, and the outputs Qa ₁ to FF _{10 to} the flip flops FF _{1 to} FF ₁₀ of the shift registers 35 and 40. Qa ₅ ) (Qb _{1 to} Qb ₅ ) is logically multiplied at the AND gates A _{1 to} A ₈ of the logic signal controller 45 and is ORed at the OR gates O _{1 to} O ₆ to provide the constant speed signal SP ₁ . And output the long time signal EP ₁ to the output signal discriminating unit 50.

First, a long period of time The mode signal (EP ₁₎ are AND gates (A ₁₎ (A ₂₎ (A ₅₎ (A _6), the logical product of the shift register 35, 40 output the Iowa gate (O ₁₎ (O in ₄₎ end to be outputted through the Iowa gate (O ₂₎ after the logical sum by a gate (a _1), the inverted output of the output (Qa ₁₎ and the flip-flop (FF ₂₎ flip-flops (FF ₁₎ (Qa ₂ ) and the output Qa ₃ of the flip-flop FF ₃ are ORed to obtain the outputs of Qa ₁ · (Qa ₂ ) · Qa ₃ , and the inverted flip-flop FF ₁ (FF) at the AND gate A ₂ . ₃₎ output (Qa ₁₎ (Qa ₃₎ and a flip-flop (FF ₂₎ output (Qa ₂₎ the by Qa ₁ · Qa ₂ · obtain the output of the Qa _3, and the aND gate (a ₅₎ (a ₆ OR of the ) in the aND gate (a ₅₎ based on the same method as described above to obtain an output of ₁ · Qb Qb Qb · _{2 3} in the aND gate (a ₆₎ is obtained the output of the Qb Qb ₁ · ₂ · ₃ Qb.

The output of the AND gate A ₁ (A ₂ ) is logically summed from the ora gate O _{1 to} the outputs of Qa ₁ · Qa ₂ · Qa ₃ + Qa ₁ · Qa ₂ · Qa ₃ and the AND gate A _5. The output of (A ₆ ) is ORed from the oragate (O ₄ ) to the outputs of Qb1, Qb2, Qb3 + Qb ₁ , Qb ₂ , Qb _{3, and} the output of the oragate (O ₁ ) (O ₄ ) The long time mode signal after being logically summed to the output of Qa ₁ Qa ₂ Qa ₃ + Qa ₁ Qa ₂ Qa ₃ + Qb ₁ Qb ₂ Qb ₃ + Qb ₁ Qb ₂ Qb _{3 at} the gate O ₂ EP ₁ ) to be output.

Therefore, the logic of the long time signal EP ₁

_{EP 1 = Qa 1 · Qa 2} · Qa 3 + Qa 1 · Qa 2 · Qa 3 +

₁ · ₂ · Qb Qb Qb Qb ₃ + ₁ · ₂ · Qb Qb ₃

It is defined as.

In addition, the logic of the constant speed signal SP ₁ is also the same as the logic expansion of the long time signal EP ₁ described above, and the gates of the AND gate A ₃ (A ₄ ) (A ₇ ) (A ₈ ) and the oragate ( From O ₃ ) (O ₅ ) (O ₆ )

₁ = ₁ · Qa Qa ₃ SP · ₅ + Qa Qa Qa ₁ · ₃ · ₅ + Qa

Qb1, Qb3, Qb5 + Qb1, Qb3, Qb5

Will be defined as

In this way, the long time mode signal EP ₁ and the constant speed mode signal SP ₁ output from the logic signal controller 45 are applied to the output signal discrimination unit 50 to control the mode determination signal MS together with another input. Done.

That is, the output signal discrimination unit 50 is composed of an AND gate A _{0 to} A ₁₂ , an ora gate O ₇ , O ₈ , a flip-flop F ₁₁ , and an inverter I ₂ . ₁ ) The mode determination signal MS is controlled according to the input of the constant speed mode signal SP ₁ , the mode switching signal EP / SP, the recording signal REC, and the power signal PSW. ) When selecting, the mode selection signal (EP / SP) becomes "H", when recording, the recording signal (REC) becomes "H", and when the powder is 'on', the power signal (PSW) becomes "H".

Therefore, the output terminal (Q) output of the flip-flop (FF ₁₁ ) appears according to the mode switching signal (EP / SP) input at the first powder 'on', and in the recording mode, the long time signal (EP ₁ ) or the constant speed signal (SP) is displayed. ₁ ) Irrespective of the mode switching signal (EP / SP) input state, the output state of the flip-flop (FF ₁₁ ) is input, and in the non-recording mode, the long time mode signal (EP ₁ ) and the constant speed mode signal (SP ₁ ) are input. According to the output state of the flip-flop (FF ₁₁ ) is determined, it is possible to select a long time mode (EP) and a constant speed mode (SP).

I.e., when the five clocks after the change in the case of the locus judgment signal (TP) in the waveform as three help generate Qa ₁ · Qa ₃ · Since _{Qa 5 + Qb 1 · Qb 3} · Qb 5 the "H" state constant speed The mode signal ( SP ₁ ) is applied to the output signal discrimination unit 50 in the "H" state to output the outputs of the AND gate A ₁₂ and the OA gate O ₈ to the "H" state, thereby reducing the flip-flop FF ₁₁ . The set terminal R is operated to output the output terminal Q of the flip-flop FF ₁₁ , that is, the mode determination signal MS to "L" and change the constant speed SP.

As described above, in the recording and reproducing apparatus employing the automatic track detection system, when switching the time mode switching signal (EP / SP) into a long time signal and playing back a tape recorded with a constant speed mode, By outputting the mode determination signal (MS) to automatically switch to constant speed playback, there is an advantage that the function of the VTR can be improved by automatically switching the mode and the constant speed mode for a long time during playback.

Claims (1)

In the recording and reproducing apparatus, in which the automatic track detection control circuit 30 outputs different tape track determination signals TP according to the recording and playback modes of the tape, the tape track observation signal TP is flip-flop. The output is sequentially delayed by the head switching signal HP applied to the input terminal D of the shift registers 35 and 40 composed of (FF _{1 to} FF ₁₀ ) and applied to the clock terminal. the output of the shift register 35, 40 are aND gates (a ₁ ~A ₈₎ and the gate Iowa (O ₁ ~O ₈₎ by Tung a logic signal control unit 45 the mode signal (EP ₁₎ for a long time with constant speed consisting of to be output to the modal signals (SP _1), and with the extended period of time both de signal (EP ₁₎ and the constant-speed-modal signal (SP ₁₎ is the mode switching signal (EP / SP) and recording signal (REC) and pawooeo signal (PSW) AND gate (A ₉ ~A _12), Iowa gate _{(O 7) (O 8)} , an inverter (I _2), flip-flat The mode automatic selection method of automatic track detection system which (FF ₁₁₎ to be applied to the configured output signal determining unit 50 controls the modal determination signal (MS).

Images