KR880000821Y1 - External image input characteristic averaging apparatus for a tv - Google Patents
External image input characteristic averaging apparatus for a tv Download PDFInfo
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- KR880000821Y1 KR880000821Y1 KR2019850007857U KR850007857U KR880000821Y1 KR 880000821 Y1 KR880000821 Y1 KR 880000821Y1 KR 2019850007857 U KR2019850007857 U KR 2019850007857U KR 850007857 U KR850007857 U KR 850007857U KR 880000821 Y1 KR880000821 Y1 KR 880000821Y1
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- transistor
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- series resonant
- resonant circuit
- output
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/06—Driving or adjusting arrangements; combined with other driving or adjusting arrangements, e.g. of gain control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/22—Continuous tuning of single resonant circuit by varying inductance and capacitance simultaneously
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H2231/00—Applications
- H01H2231/036—Radio; TV
Abstract
내용 없음.No content.
Description
제1도는 종래 장치의 개략회로 구성도.1 is a schematic circuit diagram of a conventional apparatus.
제2(a)도는 본 고안 장치의 회로도.2 (a) is a circuit diagram of the device of the present invention.
제2(b)도는 본 고안 장치의 또 다른 회로도.Figure 2 (b) is another circuit diagram of the device of the present invention.
제3(a)도, 제3(b)도는 입력신호들의 특성 곡선도.3 (a) and 3 (b) are characteristic curve diagrams of input signals.
본 고안은 외부영상 입력단자를 갖는 TV수상기에서 안테나로부터 수신된 영상신호와 외부영상 기기장치로부터 입력되는 영상신호의 주파수 특성차를 보상하기 위한 특성 평균화 장치에 관한 것이다.The present invention relates to a characteristic averaging device for compensating for a frequency characteristic difference between a video signal received from an antenna and a video signal input from an external video device in a TV receiver having an external video input terminal.
종래에는 제1도와 같이 단지 TV수상기에 선택 스위치(SW)를 설치하여 안테나로 수신된 영상신호와 외부입력 영상신호를 절환하도록 하였으나, 제3(a)도, 제3(b)도와 같이 입력되는 영상신호의 특성 곡선이 다르므로 TV수상기의 화질이 좋지 않게 된다던가 또는 화면 색상의 과포화 상태를 유발하게 되어 연관 소자들의 열화를 초래한다는 단점이 있었다.Conventionally, as shown in FIG. 1, only a selection switch SW is installed in a TV receiver to switch an image signal received from an antenna and an external input image signal. Since the characteristic curve of the video signal is different, the image quality of the TV receiver is not good or the supersaturation of the screen color is caused, which causes the deterioration of related elements.
본 고안은 이러한 종래의 단점을 없이하도록 선택 스위치에 연동 스위치 등의 관련회로를 설치하여 안테나 영상신호와 외부 입력 영상신호를 논리값 "0", "1"로서 구분하도록하여 입력신호에 따른 보상용 특성평균화 장치를 제공하는 것을 목적으로 하며, 첨부된 도면을 참조하면서 본 고안의 구성, 작용 효과를 설명하면 다음과 같다.The present invention provides a compensation circuit according to an input signal by installing an associated circuit such as an interlock switch in a selector switch so as to eliminate the above-mentioned disadvantages. An object of the present invention is to provide a characteristic averaging apparatus, and the construction and operation effects of the present invention will be described with reference to the accompanying drawings.
스위치(SW)에 연동되는 논리발생장치(1)를 설치하고 논리발생장치(1)의 출력을 에미터 접지된 트랜지스터(TR1)의 베이스에 연결하되, 트랜지스터(TR1)의 콜렉터를 저항(R6), 콘덴서(C1) 및 코일(L1)로 구성된 직렬공진회로(2)의 저항(R6)과 콘덴서(C1)의 접속점에 연결하고, 입력영상신호를 트랜지스터(Q1)와 트랜지스터(Q2)를 통하여 영상처리회로(3)에 연결하되 직렬공진회로(2)를 트랜지스터(Q1)와 트랜지스터(Q2)사이에 삽입 연결하여된 구성이다.Install a logic generator 1 interlocked with the switch SW and connect the output of the logic generator 1 to the base of the emitter grounded transistor TR 1 , and connect the collector of the transistor TR 1 to a resistor ( R 6 ), the connection of the resistor (R 6 ) and the capacitor (C 1 ) of the series resonant circuit (2) consisting of a capacitor (C 1 ) and a coil (L 1 ), and the input video signal to the transistor (Q 1 ) Is connected to the image processing circuit 3 through the transistor Q 2 and the series resonant circuit 2 is inserted between the transistor Q 1 and the transistor Q 2 .
이러한 구성의 작용 효과는 제2(a)도를 참조하면, 논리발생장치(1)는 "1", "0"의 제어출력을 가지며 이 제어 출력은 외부영상입력 선택시 논리"1", 안테나 수신신호를 선택시 논리"0"로서 출력된다. 스위치(SW)에서 선택된 영상입력신호는 트랜지스터(Q1)에서 임피던스 변환되어 그 출력이 저항(R3)에 나타나게 되며 전류제항저항(R4)을 거쳐 완충증폭용 트랜지스터(Q2)의 베이스에 가해져 저항(R5)으로 출력되어 영상 처리회로(3)에 공급되게 된다.Referring to Fig. 2 (a), the effect of such a configuration is that the logic generator 1 has control outputs of "1" and "0", and this control output is a logic "1" when selecting an external image input, an antenna. When the received signal is selected, it is output as logic "0". The image input signal selected by the switch SW is impedance-converted in the transistor Q 1 so that its output appears in the resistor R 3 and passes through the current limiting resistor R 4 to the base of the buffer amplification transistor Q 2 . Is applied to the image processing circuit 3 and output to the resistor R5.
여기서 트랜지스터(Q1)의 에미터 출력과 트랜지스터(Q2)의 베이스 입력사이에 코일(L1), 콘덴서(C1), 저항(R6) 및 스위칭 트랜지스터(TR1)로 형성되는 색부반송파 트랩회로를 연결하였다.The emitter of the transistor (Q 1) emitter colors formed of the output transistor coil between the base inputs of the (Q 2) (L 1) , a capacitor (C 1), a resistance (R 6) and a switching transistor (TR 1) subcarriers The trap circuit was connected.
제어출력이 논리 "0"인 경우 즉, 안테나 입력신호를 선택한 경우 트랜지스터(TR1)는 오프하게 되고 직렬공진회로(2)의 저항(R6)이 비교적 큰 값으로서 색부반송파 트랩의 효과를 갖지 않는 정도로 설정하므로서 입력신호가 주파수 특성의 변화없이 트랜지스터(Q2)의 베이스에 가해지도록 한다.When the control output is logic "0", that is, when the antenna input signal is selected, the transistor TR 1 is turned off and the resistance R 6 of the series resonant circuit 2 is a relatively large value, which does not have the effect of color carrier trapping. By setting it to a degree not being set, the input signal is applied to the base of the transistor Q 2 without changing the frequency characteristic.
한편, 외부영상신호를 수신하여 논리발생장치(1)의 제어출력이 논리"1"인 경우는 트랜지스터(TR1)가, 온하게되며 트랜지스터(Q2)의 베이스 입력단에는 코일(L1), 콘덴서(C1), 트랜지스터(TR1), 콜랙터, 에미터간 포화저항(=0Ω)으로 형성되는 직렬 공진 트랩회로가 만들어지게 되어 영상신호중 색부반송파(fc)신호가 감쇄하게 된다. 이때 감쇄의 정도를 -6dB 수준으로 하기위한 댐핑저항(R1)이 사용되게 된다.On the other hand, when the control output of the logic generating device 1 is logic " 1 " by receiving an external video signal, the transistor TR 1 is turned on and at the base input terminal of the transistor Q 2 , the coil L 1 , The series resonant trap circuit formed by the condenser C 1 , the transistor TR 1 , the collector, and the emitter saturation resistance (= 0Ω) is made to attenuate the color carrier (fc) signal of the image signal. At this time, the damping resistance (R 1 ) to set the degree of attenuation to -6dB level is used.
이리하여 입력의 선택여부에 관계없이 동일한 특성의 신호를 영상 및 색처리에 가해줄 수 있게 되므로서 회로 구성의 간략화 및 최적의 화질 재생이 가능하게 된다.In this way, the signal having the same characteristic can be applied to the image and the color processing regardless of the input selection, thereby simplifying the circuit configuration and reproducing the optimum image quality.
또한 제2(b)도를 참조하면, 논리발생장치(1)의 출력을 다이오드(D1)를 통하여 코일(L1), 콘덴서(C1) 및 저항(R4)으로 이루어진 직렬 공진회로(2)에 연결하되 직렬 공진회로(2)에 저항(R3)을 병렬 연결하고, 직렬 공진회로(2)를 트랜지스터(Q1)와 트랜지스터(Q2)의 사이에 병렬접속하여 된 구성을 알수 있고 이러한 구성의 작용효과는, 스위치(SW)에서 선택된 신호는 트랜지스터(Q1)에서 임피던스 변환되어 그 출력이 저항(R3)에 나타나게 된다. 여기서 R1, R2는 바이어스 저항 이다.Referring also to FIG. 2 (b), the output of the logic generator 1 is connected to a series resonant circuit consisting of a coil L 1 , a capacitor C 1 , and a resistor R 4 via a diode D 1 . 2) but the resistor R 3 is connected to the series resonant circuit 2 in parallel, and the series resonant circuit 2 is connected in parallel between the transistor Q 1 and the transistor Q 2 . The effect of this configuration is that the signal selected at the switch SW is impedance-converted at the transistor Q 1 so that its output appears at the resistor R 3 . Where R 1 and R 2 are bias resistors.
안테나로부터 수신된 신호를 선택하여 그 제어출력이 논리 "1"인 경우 다이오드(D1)의 캐소우드 전압이 애노우드보다 높게되어 다이오드(D1)가 오프 상태에 있게되며 코일(L1), 콘덴서(C1) 및 저항(R4)으로 구성되는 색부반송파 트랩용 직렬 공진회로는 비작동되게 된다. 따라서 저항(R3)에 나타난 영상신호는 그대로 트랜지스터(Q2)의 베이스에 가해서 에미터측의 저항(R5)으로 출력되어 색처리회로(3)에 가해지게 된다.When selecting the received signal from the antenna of the control output is a logical "1", the diode (D 1) the cathode voltage is higher than the anode of the diode (D 1) is to be in the OFF state, and the coil (L 1), The series resonant circuit for the color carrier trap consisting of the capacitor C 1 and the resistor R 4 is deactivated. Therefore, the image signal represented by the resistor R 3 is applied to the base of the transistor Q 2 as it is, and is output to the resistor R 5 on the emitter side and applied to the color processing circuit 3.
한편, 스위치(SW)에서 외부영상입력을 선택한 경우, 논리발생장치(1)의 출력의 신호는 논리"0"인바 다이오드(D1)의 캐소우드는 접지로 되고, 애노우드는 전원전압(B+)이 12V인 경우,의 전압이 다이오드(D1)의 바이어스 저항(R6)을 거쳐 애노우드에 가해지므로 다이오드(D1)가 온하게 된다. 따라서 코일(L1), 콘덴서(C1), 저항(R4)으로 형성되는 색부반송파 트랩회로는 다이오드(D1)의 온 저항인(RD)와 직렬로 접속되어 접지된 상태로 되게 되므로서 -6dB 감쇄된 특성으로 나타난다.On the other hand, when the external image input is selected by the switch SW, the signal of the output of the logic generator 1 is the logic "0", the cathode of the diode D 1 is grounded, the anode is the power supply voltage (B + ) Is 12V, The voltage across the bias resistor (R 6) of the diode (D 1) is applied to the anode so that the diode (D 1) is turned on. Therefore, the color carrier carrier trap circuit formed of the coil L 1 , the capacitor C 1 , and the resistor R 4 is connected in series with the on-resistance RD of the diode D 1 to be grounded. -6 dB attenuated.
이와같이 입력의 선택 여부에 따라 가변 주파수 특성을 갖는 회로를 사용하므로서 입력신호의 주파수 특성을 보상하여 항상 일정한 출력 주파수 특성을 갖도록 하므로서 색처리 회로구성의 간략화 및 최적의 화질 재생이 가능하게 된다.Thus, by using a circuit having a variable frequency characteristics according to the selection of the input to compensate for the frequency characteristics of the input signal to always have a constant output frequency characteristics, it is possible to simplify the color processing circuit configuration and optimum image quality reproduction.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850007857U KR880000821Y1 (en) | 1985-06-28 | 1985-06-28 | External image input characteristic averaging apparatus for a tv |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850007857U KR880000821Y1 (en) | 1985-06-28 | 1985-06-28 | External image input characteristic averaging apparatus for a tv |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870001370U KR870001370U (en) | 1987-02-20 |
| KR880000821Y1 true KR880000821Y1 (en) | 1988-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850007857U KR880000821Y1 (en) | 1985-06-28 | 1985-06-28 | External image input characteristic averaging apparatus for a tv |
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| KR (1) | KR880000821Y1 (en) |
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1985
- 1985-06-28 KR KR2019850007857U patent/KR880000821Y1/en not_active IP Right Cessation
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| KR870001370U (en) | 1987-02-20 |
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