KR870000499Y1 - Electronic lock - Google Patents

Abstract

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Description

Electronic lock

1 is a block diagram for explaining the present invention.

2 is a circuit diagram of the present invention.

3 is a waveform diagram of each part of the present invention,

FIG. 3 (a) is a waveform diagram shown at point a in FIG.

FIG. 3 (b) is a waveform diagram shown at point c in FIG.

FIG. 3 (c) is a waveform diagram shown at point b in FIG.

FIG. 3 (d) is a waveform diagram shown at point d in FIG.

FIG. 3 (e) is a waveform diagram at point e of FIG.

4 is a truth table of the shift register (4) in the present invention.

5 is a truth table of the counter 7 in the present invention.

6 is an operational waveform diagram of the counter 7 in the present invention.

* Explanation of symbols for main parts of the drawings

1: Signal selection button of "1" 2: Signal selection button of "0"

3: input circuit part 4: shift register

5: comparison circuit 6: password setting switch

7: counter 8: solenoid drive unit

9: End circuit part N ₁ -N ₃ : NAND gate

I ₁ -I ₆ : Inverter D ₁ -D ₁₂ : Diode

X ₁ -X ₈ : Exclusive OR gate S ₁ -S ₈ : Password setting switch

R ₁ -R ₁₀ : Resistor C ₁ -C ₃ : Capacitor

The present invention relates to an electronic lock device in which the lock is released only when the lock information is released by comparing the information for unlocking the lock with a preset password by inputting a signal for unlocking the lock. .

Conventional electronic lock device uses a circuit element having a variety of characteristics, not only its circuit configuration is complicated, but also brought about factors such as lower reliability, higher cost,

In addition, there has been a problem in that the number of wirings connecting the key and the lock main body increases, so that installation during installation is not easy.

In consideration of this, the present invention simplifies the circuit configuration and reduces costs by simplifying the circuit configuration, and also greatly improves the reliability of the product by greatly simplifying the number of wires between the key and the lock body. When described in detail with the accompanying drawings as follows.

1 is a block diagram of the present invention, which includes an input circuit section 3 for converting a signal input from a signal selection button 1 of " 1 " and a signal selection button 2 of " 0 " A counter (7) for counting the pulse signal and checking the eighth pulse signal, a shift register (4) for inputting the pulse signal in serial and outputting in parallel (Parallel), and a secret designation number A password setting switch section 6 comprising switches S ₁ -S ₈ , a comparison circuit section 5 for comparing the output of the shift register 4 with a password setting signal, the comparison circuit section 5, and a counter It consists of a solenoid drive unit 8 which is driven to unlock when the output signals of (9) coincide with each other.

If described in detail with reference to Figure 2 the actual effect of the present invention configured as described above.

First, when the signal selection button 1 of " 1 " and the signal selection button 2 of " 0 " are pressed at the same time to reset the entire circuit portion, the input circuit section 3 is connected through the diodes D ₁ and D ₂ . Since a low signal is input to one input terminal of the NAND gate N _{2 in the} inside, and a high signal is normally input from the output terminal of the inverter I ₁ to the other input terminal thereof.

A high signal is output to the output terminal of the NAND gate N ₂ , and this signal is passed through the capacitor C ₁ and the resistor R ₆ so that a waveform as shown in FIG. 3A appears at the connection point a. Become,

Such a waveform is converted into a waveform as shown in (c) of FIG. 3 through an inverter I ₁ and appears.

This waveform is again converted into a waveform as shown in FIG. 3 (b) through the inverter I ₂ so that the respective reset terminals Reset ₁ and Reset _{2 of the} shift register 4 and the counter 7 are performed. ) And (RE), the entire circuit portion is in a reset state as shown in FIGS. 4 and 5.

At this time, since the input signals of the NAND gate N ₁ are all in a low state, a high signal state appears in the output terminal thereof, and the rear end circuit state is not changed. On the other hand, the data signal terminal DATA ₁ of the shift register 4 has no relationship between the high state and the low state as shown in FIG. 4 when the reset signal is in the high state, and thus has no effect on the circuit. .

A NAND gate (N ₂₎ when the former circuit to the reset sequence of the PW previously set in a state of "1" of the signal selection button (1) and the signal selected in the "0" key (2) pushing the steps described above, Since the high state signal is always input to the input terminal, there is no change in the rear circuit portion thereof.

On the other hand, when the input signal appearing at the input terminal of the NAND gate N ₁ is pressed one of the signal selection button 1 of " 1 " and the signal selection button 2 of " 0 " Since the terminal that is not pressed is in a high state, the high signal appearing at its output terminal has a waveform as shown in (d) of FIG. 3 through a resistor (R ₄ ) (R ₅ ) and a capacitor (C ₂ ). d).

Such a waveform is converted into the signal waveform shown in FIG. 3 (e) through a known Schmitt trigger circuit consisting of inverters I ₃ , I ₄ and resistor R ₇ to convert the shift register 4 and the counter ( It is input to each clock terminal (Clock ₁ ), (Clock ₂ ) and (CK) of 7).

At this time, the shift register 4 distinguishes the signals of "0" and "1", and if the signal is "0", the key 2 is selected). The shift register 4 has a low level at the data signal terminal DATA ₁ of the shift register 4. When the status signal is applied to distinguish the "0" signal, and in the case of the "1" signal (the key 1 is selected), the data signal terminal DATA ₁ continues to maintain the high signal state so that the clock pulse is input. Is input as a signal of "1".

In this way, once eight pulses are input to the shift register 4, the least significant bit is output to the most significant bit output terminal Q _{A1 at} its output terminal Q _D2 and each Exclusive OR gate (X ₁ -X). ₈ ) is input to one input terminal, the other input terminal is configured to be applied to the power supply (B ⁺ ) through the password setting switch (S _1- S ₈ ) and the resistor (R _1- R ₈ ),

When the input terminal signals of the exclusive OR gates (X _1- X ₈ ) coincide with each other, a low signal is outputted to the output terminal thereof, and this signal appears at the connection point f through the diodes D ₁ -D ₈ . .

On the other hand, when the eighth input pulse is applied to the counter 7, a high signal pulse is output to the output terminal Q _{8 thereof} , and the high pulse is converted into a low signal through the inverter I ₅ .

Therefore, since the output terminal signal of the comparison circuit unit 5 and the signal through the inverter I ₅ both appear low, the signal appearing at one input terminal of the NAND gate N ₃ is the resistor R ₁₀ and the diode D ₄ . Goes low via

This signal is passed through a NAND gate N ₃ , a capacitor C ₃ , a resistor R ₉ , and an inverter I ₆ , the solenoid drive circuit section 8 of which the waveform as shown in FIG. 3C is known. Is applied to the solenoid inside of it and the lock is released.

If any of the outputs of the shift register 4 does not match the signal state of the password setting switch (S ₁ -S ₈ ), the signal appearing at the output of the exclusive OR gate (X ₁ -X ₈ ) is high. Become,

This high signal appears at the junction f through the diodes D ₁ -D ₈ and the single-ended signal of the NAND gate N ₃ continues to maintain the high signal state, so the solenoid drive unit 8 is not driven and the lock is locked. The device will not open.

The present invention operated as described above can simplify the configuration and simplify the process and reduce the cost, as well as greatly simplify the number of wiring between the key and the lock body, there is an advantage that the construction is easy.

Claims (2)

In the electronic lock device, the input circuit unit 3 is connected thereto so as to convert the signal input by the operation of the signal selection button 1 of "1" and the signal selection button 2 of "0" into pulses, A counter 7 for countering the number of pulses input from the input circuit section 3 and outputting when the eighth pulse is input and a shift register 4 for inputting a pulse signal in series and outputting in parallel, respectively, A comparison circuit section 5 for comparing the signal of the password setting switch section 6 with the output signal of the register 4 is connected to the output terminal of the shift register 4, The output terminal of the comparison circuit section (5) and the counter (4) is configured to be connected to the solenoid drive unit (8) for driving to open the lock when their output signal coincides. The method of claim 1, wherein the diode "1" of the signal selection button (1) and "0" of the signal selection button (2) input circuit portion (3) so as to reset all the circuit when turned on at the same time a (D _1, D ₂ ), an NAND gate (N ₁ , N ₂ ), a capacitor (C ₁ ), a resistor (R ₆ ) and an inverter (I ₁ , I ₂ ) An electronic lock device characterized in that.