KR850000956B1 - Muting circuit - Google Patents

Abstract

The circuit detects the tuning state (i.e. proper tuning, mistuning and slight mistuning) of the local oscillator of the television tuner. The tuning detecting circuit receives a pair of oppositely phased signals from an automatic fine tuning circuit, and generates an output signal indicating the tuning state of the local oscillator. A synchronization detecting circuit, receiving synchronizing signals and flayback pulses, determines whether the synchronization is maintained. This circuit generates an outut signal indicating the synchronization of the synchronizing signals and the flyback pulses.

Description

Operation status detection and processing circuit

1 is a circuit diagram showing one embodiment of the present invention.

2 (a) to 2 (i) are operating waveform diagrams for explaining the operation of the circuit of FIG.

3 and 4 show filter characteristics of the detection circuit section.

5 is a diagram showing channel frequency bands in voice multiple broadcasting.

* Explanation of symbols for main parts of the drawings

A: Sync detection circuit B: Synchronous detection circuit

C: voice noise detection circuit D: noise detection rectifier circuit

E: Logic Circuit F: Indicator

G: switching circuit H: audio signal muting section

The present invention relates to an operation state detection and processing circuit used in color television receivers and the like.

In a color television receiver, there are cases in which various operation conditions of the receiver are judged and appropriate responses are made accordingly. For example, voice muting is as follows.

As the muting means for the audio signal, a means for FM detecting the intermediate frequency signal and shorting or opening the audio signal line in accordance with the detection output level is common. However, in a television receiver, when such a muting means is used, there are times when harmonic components generated when FM detection of an intermediate frequency signal are mixed as beating disturbances on the screen. Therefore, there are cases where a means for suppressing such high frequency components is taken, but the circuit configuration is complicated and expensive.

An object of the present invention is to provide an operation condition detection and processing circuit suitable for detecting various operation conditions of the television receiver and coping with the detection results thereof, and particularly suitable for obtaining muting operation.

Embodiments of the present invention will be described below with reference to the drawings.

1 shows a configuration used for a color television receiver capable of receiving voice multiple broadcasts, in which (A) is a detection circuit in a tuned state to which a detection output from an automatic frequency tuning circuit (commonly referred to as an AFT circuit) is input. This is referred to as a tuning detection circuit hereinafter. This tuning detection circuit A obtains an output indicating an unsynchronized state when the tuned state, the tuned frequency is shifted toward the higher side, or the lower side.

(B) is a synchronization detection circuit into which a so-called flyback pulse from a flyback transformer and a horizontal synchronization signal are input. This synchronization detection circuit B can take the logic of both inputs.

(C) is a voice noise detection circuit, has a unique pass frequency band, and detects noise in a frequency band that should be essentially a no signal. Therefore, the intermediate voice frequency signal is input to the input terminal.

Next, (D) is a noise detection rectification circuit, which detects and rectifies the output of the voice noise detection circuit C and converts it into direct current.

(E) is a logic circuit. The logic circuit E is a circuit which performs information processing on the outputs of the above-described tuning detection circuit A, the synchronization detection circuit B, and the noise detection circuit C.

This logic circuit E controls the indicator F in accordance with the processing result and allows the display of the tuning state, the tuning state, and the complete non-tuning state. The logic circuit E can also control the muting switching circuit G according to the processing result.

The muting switching circuit G can mute the audio signal according to the control input from the logic circuit E and the control input from the noise detection circuit D. In addition, the sensor operates in response to the output of the synchronization signal detecting circuit B. FIG.

Next, the internal structure and connection structure of each circuit are demonstrated concretely.

The tuning detection circuit A has input terminals 1 and 2, and the first and second detection outputs AFT-1 and AFT-2 (see also FIG. 2a) are input. The condenser 3 is connected between the input terminals 1 to 2. The input terminals 1 and 2 are connected to the bases of the transistors Q ₁ and Q ₂ via the resistors 4 and 5, respectively. The bases of the transistors Q ₁ and Q ₂ are connected to the anodes of the diodes 6 and 7, respectively, and the transistors Q ₁ are common to the diodes of the diodes 6 and 7. , (Q ₂ ) is connected to the common emitter. The collectors of the transistors Q ₁ and Q ₂ are connected to the bases of the transistors Q ₃ and Q ₄ via the resistors 8 and 9, respectively, and these transistors Q ₃ and Q, respectively. ₄ ) the emitter is grounded, each collector is connected to the power supply line 12 via resistors 10 and 11, respectively, and each collector is again connected to the NAND circuit 55 forming a logic circuit E. It is connected to the 1st, 2nd input terminal.

In the first and second detection outputs (Fig. 2a) input to the synchronization detecting circuit A, the output of the center point (frequency position of f ₀ ) of the S-curve is obtained when in the synchronized state. Transistors Q ₁ , Q ₂ and transistors Q ₃ , Q ₄ are “off”. Therefore, the first and second input terminals of the NAND circuit 55 are at a high level, and the output of the circuit 55 is at a low level. 2 (d), 3 (b), and 3 (c) show the outputs of the transistors Q ₃ and Q ₄ , that is, the input waveforms of the NAND circuit 55.

The synchronization signal detecting circuit B has a flyback pulse input terminal 15 and a horizontal synchronization signal input terminal 16. The horizontal synchronous signal input terminal 16 is connected to the base of the transistor Q ₅ via a capacitor 17 and a resistor 18 in series. The base of the transistor Q ₅ is grounded through the parallel circuit of the resistor 19 and the capacitor 20, and the emitter is also grounded. The flyback pulse input terminal 15 is connected to the base of the transistor Q ₆ via a resistor 21. The base of this transistor Q ₆ is connected via a resistor 22, the emitter is connected to the collector of the preceding transistor Q ₅ , and the collector is connected to the power supply line 12 via a resistor 23. do. Again, the collector of this transistor Q ₆ is connected to the base of transistor Q ₇ via a resistor 24. The capacitor 25 is connected between the base and the emitter of the transistor Q ₇ , and the emitter is connected to the power supply line. The collector of this transistor Q ₇ is grounded via a resistor 26 and connected to the first input terminal of the NAND circuit 56.

The synchronization signal detecting circuit B takes the logic of the flyback pulses of the input terminals 15 and 16 and the horizontal registration signal. When both input signals are present, the transistors Q ₅ and Q _{6 are present} . , Q ₇ is turned "on", and the collector potential of transistor Q ₇ is at a high level. If either the flyback pulse or the synchronous signal is missing, the " on " operation of the transistor Q ₇ cannot be obtained, and the collector potential becomes the earth potential (low level). (The collector potential of the transistor Q ₇₎ the synchronization signal detection circuit (B) of the output is the same as shown in claim 2 (c) Fig.

The voice noise detection circuit C has a voice intermediate frequency signal input terminal 30. The input terminal 30 is connected to the base of the transistor Q ₈ via a resistor 31 and a capacitor 32. The connection point of the resistor 31 and the capacitor 32 is grounded through the capacitor 33. The base of the transistor Q ₈ is grounded via a resistor 34 and connected to the power supply line 12 via a resistor 35.

In the side circuit of the transistor Q ₈ , unique filter characteristics are set.

The emitter of the transistor Q ₈ is connected to one end of the coil 38 and the capacitor 39 via the parallel circuit of the resistor 36 and the capacitor 37. The other end of the coil 38 and the condenser 39 is grounded. The collector of the transistor Q ₈ is connected to the power supply line 12 via the resistor 40 and at the same time to the base of the transistor Q ₉ via the capacitor 41. The base of the transistor Q ₉ is grounded through the resistor 42 and the reverse diode 43.

The transistor Q ₉ forms a noise detection rectifier, and the emitter is connected to the power supply line 12 via the parallel circuit of the resistor 44 and the capacitor 45. Again, the collector of this transistor Q ₉ is connected to the second input terminal of the NAND circuit 56 via a resistor 46.

The voice noise detection circuit (C) and the noise detection rectification circuit (D) are circuits for discriminating when the noise is mixed into a place where the signal should be essentially no signal.

When there is no noise, transistor Q ₈ is " off ". Base bias of the transistor when (Q ₉₎ is a transistor (Q ₉₎ are set to "off". Transistor (Q ₁₃₎ to review here is, if the "on" setting transistor (Q ₈₎ is "On" doeyeo that the DC component may be added to the base bias of the transistor (Q ₉₎ transistors (Q ₉₎ is "off" Maintain state.

Next, when noise is determined, the transistor Q ₈ is turned on. As a result, the output DC of transistor Q ₈ is added and transistor Q ₉ is “on.” However, in this case, it is a condition that transistor Q ₁₃ described later is “off”, for example, transistor Q _13. Is in the "on" state, the noise is input and transistor Q ₈ is not "on" even if transistor Q ₈ is "on".

When transistor Q ₉ is "on" and its collector potential is at low level, the second input terminal input level of NAND circuit 56 is as shown in FIG. 2 (f).

The collector of transistor Q ₉ is connected to the diode 48 via a resistor 47. The connection point between the diode 48 and the resistor 47 is connected to the power supply line via the capacitor 49. The anode of the diode 48 is connected to the base of the transistor Q ₁₀ and simultaneously connected to the first input terminal of the AND circuit 50 via the diode 50 in the forward direction.

The transistor Q ₁₀ is " on "" off " during muting, the collector is grounded, and the emitter is one end of the slider 53 provided in the variable resistor 52 for voice control via the switch section 51. You can connect to The transistor Q ₁₀ may be connected to the power supply line 12 via a switch unit 51. When transistor Q ₁₀ is " on " the slider is grounded and the audio signal is muted.

Next, in the logic circuit E, the output terminals of the NAND circuits 55 and 56 are connected to the first and second input terminals of the NOR circuit 57. The output terminal of the NAND circuit 56 is connected to the first input terminal of the NAND circuit 58. The output terminal of the NAND circuit 58 is connected to the first and second input terminals of the NAND circuit 66 and to the first and second input terminals of the NOR circuit 59. The output terminal of the NOR circuit 59 is connected to the first and second input terminals of the NOR circuit 60, and the output terminal of the NOR circuit 60 is connected to the NAND circuit (63) via resistors 61 and 62. And the second input terminal of 58).

The loops of the NAND circuit 58, the NOR circuit 59, and 60 have time constants, and a capacitor 63 is connected between the input and output terminals of the NOR circuit 60.

The output terminal of the NAND circuit 66 is connected to the second input terminal of the NOR circuit 67. The output terminal of the NOR circuit 57 is connected to the first input terminal of the NOR circuit 67.

The output terminals of the NOR circuits 57 and 67 are connected to the bases of the transistors Q ₁₁ and Q ₁₂ via the resistors 68 and 69, respectively. The collector of the transistor (Q _11), (Q ₁₂₎ the emitter and the emitter grounded, the transistor (Q ₁₁₎ of the is connected to the power line (12) in through the resistance 70 and the green light-emitting element 71 in series, The collector of the transistor Q ₁₂ is connected to the power supply line 12 via the resistor 72 and the red light emitting elements 73 and 74.

The output terminal of the NOR circuit 57 is connected to the base of the transistor Q ₁₃ via a resistor 75. The transistor Q ₁₃ and the emitter are grounded, and the collector is connected to the base of the previous transistor Q ₉ .

The present invention has been implemented as described above, and the signal waveform of the operation description of this circuit can also be displayed as shown in FIG. The circuit according to the present invention includes various features.

First, from the characteristics of the tuning, this circuit collects and processes various muting information, whereby the display of the tuning status and the actual muting operation can be obtained.

For example, assume that the reception state was the frequency section F _{1 in} FIG. At this time, in the AFT detection unit, as shown in FIG. 2 (a), the tuning point of the S-curve corresponds. Thus transistors Q ₁ -Q ₄ are "off". In the sync signal detecting circuit B, if a normal sync signal is obtained, the transistor Q ₇ is turned off.

As a result, the first and second input terminals of the NAND circuit 55 are high level, as shown in Fig. 2 (b) and Fig. 2 (c), and their output is shown in Fig. 2 (d). As "0". The first and second input terminals of the NAND circuit 56 are high level, and their output is "0" as shown in the second (g) diagram. This causes the output of NOR circuit 57 is "1" and the transistor (Q ₁₁₎ is the "on" to emit light with a light-emitting element 71 of the green.

In addition, since the output of the NOR circuit 57 is "1", the transistor Q ₁₃ is turned "on". This means forcing the transistor Q ₉ to remain "off".

Forcing transistor Q ₉ to "off" must stop the muting operation due to this noise even if noise is detected, for example, when in the reception state of this frequency section F ₁ . That is, if a normal tuning detection output is obtained and a normal tuning signal is obtained, the screen is normal, and even if noise is detected at this time, it is not good to mute the voice completely. In this case, therefore, the muting caused by noise is forcibly stopped. 2 (e) is an output of the synchronization signal detection circuit. 2 (f) is an output of the noise detection circuit.

However, even in the above state, when one of the synchronization signals is missing, for example, the transistor Q ₇ is turned "on". As a result, a wire path of the base of the transistor Q ₁₀ , the diode 50, and the resistor 26 is formed, and muting is performed.

When the reception state is in the frequency section F ₁ as described above, the operation in the logic circuit E will be described again. As described above, it is assumed that the outputs of the NAND circuits 55 and 56 are "0", and the output of the NOR circuit 57 is "1". Here, the loops of the NNAD circuit 58, the NOR circuits 59, and 60 will be described.

In this case, the first input terminal of the NAND circuit 58 is fixed at " 0 ". This means that even if " 0 " or " 1 " is input to the second input terminal of the NAND circuit 58, the output is " 1 ". Therefore, the output of the NOR circuit 59 is "0" and the output of the NOR circuit 60 is "1".

The output of the NAND circuit 66 is "0". Here, the first input terminal of the NOR circuit 67 is "1", the output thereof is "0", and the transistor Q ₁₂ is "off".

Next, the case where the first input terminal of the NAND circuit 58 is fixed to "1" is described. In this case, the output of the NAND circuit 58 changes to "1" or "0" in response to the input of "0" or "1" to the second pressure terminal, thus the NAND circuit 58 and the NOR circuit. The loops of (59) and (60) obtain an oscillation operation. With such an oscillation operation, the output of the NAND circuit 66 also obtains an oscillation output of "0" "1." Even if an oscillation output is obtained here, As long as the first input terminal of the NOR circuit 67 (output of the nore circuit 57) is "1", the output of this NOR circuit 67 is "0".

In the above fact, if the reception state is in the frequency section F ₁ shown in Fig. 2 and a normal tuning detection output is obtained, green light is emitted in the display system. FIG. 2 (h) shows the green lighting rod. In the muting system, the muting operation for noise is forcibly stopped. However, if there is a missing synchronization signal, a muting operation is obtained. In particular, forcibly suppressing muting operation due to noise in the reception state is a characteristic part of the embodiment.

Next, a description will be given of the case where the reception state becomes the frequency section F ₁ or F ₂ shown in FIG. In this case, in order to change the state of the detection output input to the input terminals 1 and 2, the logic level of the first and second input terminals of the NAND circuit 55 is "0, 1" or "1, 0." To change. As a result, the output of the NAND circuit 55 becomes "1". Therefore, the output of the NOR circuit 57 becomes "0".

Therefore, in the frequency section F ₂ or F ' ₂ , the transistor Q ₁₃ is turned off so that the muting operation is always possible, that is, when the noise is present and the transistor Q ₈ is turned on, its output is turned on. base potential rises, and the transistor (Q ₉₎ by a direct current level minutes transistor (Q ₉₎ is "on". due to this and the transistor (Q ₁₀₎ 'on "is the take mu routing.

When no noise is detected and one of the synchronization signals (flyback pulse or horizontal synchronization signal) is missing, the transistor Q ₇ is "off" and the collector potential is lowered. In this case, a loop of the base diode 50 of the transistor Q ₁₀ and the resistor 26 is formed, and the transistor Q ₁₀ is turned on. Therefore, muting is applied even when the synchronization signal is lost.

On the other hand, the display system will be described as follows. It is assumed that there is no noise and the synchronization signal is obtained normally. Since the first and second input terminals of the NAND circuit 56 are all at the high level, the output thereof is "0". Therefore, since the first input terminal of the NAND circuit 58 is fixed to "0", the output is " This results in 1 ". The output of the NAND circuit 66 is" 0 "and the output of the NOR circuit 67 is" 1 "so that the transistor Q ₁₂ is" on ". Therefore, the frequency range F ₂ or If the reception state of the section of F ' ₂ and no noise is detected and the synchronization signal is normal, the red light emitting elements 73 and 74 light up, and muting is not performed. Indicates a lit diode.

Next, a description will be given of the case where either the first input terminal or the second input terminal of the NAND circuit 56 becomes "0" in the above-mentioned frequency section, and both input terminals become "0". do. In this case, the output of the NAND circuit 56 becomes "1". In this case, oscillation outputs of the NAND circuit 58, the NOR circuit 59, and 60 appear at the output of the NOR circuit 67 to repeat "0" and "1". In this case, of course, muting is at stake. And the enemy's light emitting element will blink.

In the above fact, first, when the reception state is in the frequency section F ₂ or F ' ₂ shown in FIG. ₂ , the synchronization signal is present, there is no noise, muting is not performed, and the enemy light emitting element blinks. In this state, when there is noise or a missing synchronization signal, the enemy light emitting device blinks and muting is applied.

Next, the case where the reception state is in the frequency section F ₃ or F ' ₃ shown in FIG. In this case, since there is noise and no synchronization signal, transistor Q ₁₀ is "on" and muting is applied. Also in the display system, the output of the NAND circuit 55 is "1", and the output of the NAND circuit 55 is also "1". Therefore, the oscillation output is obtained from the NOR circuit 67, and the enemy flashes continuously.

Embodiments of the present invention have the following features in that unnecessary muting is suppressed.

The detection output of the S-curve characteristic is applied to the first and second input terminals by the output of the automatic frequency tuning circuit, and according to the detection output, the first frequency section F ₁ , quasi-tuning in the tuning range. A second frequency section F ₂ , F ' ₂ in the range was obtained, and the third frequency section F ₃ , F' ₃ in the set range was identified. A synchronization detection circuit which obtains the same output as in the case, takes a logic with a horizontal synchronization signal, a flyback signal, and obtains an output in which both of these synchronization signals are present or discriminated from each other, and an intermediate audio signal Noise detection and rectification means, the tuning detection circuit, tuning detection circuit, noise detection and rectification means having a function of detecting and rectifying the noise outside the band of the sound intermediate frequency, and obtaining an output for determining the presence or absence of noise. Is output, and when the output of the tuning detection circuit is an output corresponding to the first tuning frequency section, the driving circuit for the light emitting element of the first color is driven and corresponding to the second tuning frequency section. In the case of the output, the driving circuit for the light emitting element of the S color is continuously driven, and in the case of the output corresponding to the second frequency section, the second circuit is logically determined together with the output of the synchronous detection circuit and the noise detection circuit. A logic circuit for intermittently driving a driving circuit for a light emitting element of a color is provided. Therefore, the reception condition of a television receiver can be judged easily.

Embodiments of the present invention have the following characteristics in that the reception conditions are easy to understand.

Since it has the so-called S-curve characteristic, which is the output of the automatic frequency tuning circuit, a detection output is applied to the first and second input terminals, and according to the detection output, the first frequency section F ₁ , in the tuning range, is quasi. The second frequency section F ₂ , F ' ₃ in the tuning range was obtained respectively, and the third frequency section F ₃ , F' ₃ in the tuning range was identified. A synchronization detection circuit that obtains the same output as when, a synchronization detection circuit that obtains the output of identifying the presence or absence of both of these synchronization signals by taking the logic of the horizontal synchronization signal and the flyback pulse, and the intermediate sound frequency signal. Noise detection and rectifying means for inputting a noise output having a function of detecting and rectifying out-of-band noise of a voice intermediate frequency and obtaining an output for determining the presence or absence of noise; and the tuning detection circuit, a synchronous detection circuit, and a noise detection means. And the outputs of the rectifying means are input, and they are logically determined so that the output of the caught detection and rectifying means is free of noise only when the output of the tuning detection circuit A is an output corresponding to the first tuning frequency section. And muting forced stop means for forcibly setting to obtain the same judgment output as the output obtained. Therefore, there is no unnecessary muting operation.

In the embodiment according to the present invention, the noise detecting circuit C and the noise detecting circuit D have the following features as good detection functions related to muting.

That is, parallel resonant circuits are provided between the input and output terminals of these circuits by the capacitors 37, 39, coils 38, and the like. The impedance Z of this parallel resonance circuit is

t-1

Becomes However, C ₁ : capacitance of the capacitor 37 C ₂ : capacitance of the capacitor 39 L: inductance of the coil 38 accordingly

t-2

to be. Here, if L and C ₁ and C ₂ are selected so that f ₁ is twice the horizontal sync frequency (approximately (31.5 kHz) and f ₂ is lower than that, then a series-parallel resonance circuit (transistor Q ₁ and base to collector In Fig. 4, the dashed line indicates the frequency characteristic when C ₁ is omitted (trap and trap only).

FIG. 1 shows the characteristics of the total frequency up to the collector output of transistor Q _{9 in} which the high pass filter and the low pass filter by the capacitors 33 and 32 are combined.

As can be seen from this characteristic diagram, the input of the transistor Q ₉ is mainly composed of frequency components of approximately 10 kHz to 22 kHz and 40 kHz or more. Therefore, the circuit detects the noise components of the 10kHz-22kHz, 40kHz and higher frequency bands. Therefore, it is possible to suppress the generation of harmonic components that are likely to occur during detection without increasing the cutoff frequency more than necessary. In addition, in order to detect a noise component near an actual voice band, a squelch circuit capable of realizing a voice muting substantially corresponding to the noise that is audible to a hearing problem is provided.

It is effective to have a muting function in voice multicasting because of having the above-described unique filter characteristics. The frequency spectrum of the voice intermediate frequency signal in voice multiple broadcasting is standardized as shown in FIG. That is, the frequency band of the main channel is 0kHz-15kHz, and the frequency band of the subchannel is 16kHz-47kHz. Therefore, the filter characteristic is responsive to the noise component located between the main channel and the subchannel and the noise component located near the upper limit of the band of the subchannel.

As described above, the noise detection and rectification means has a characteristic filter characteristic that responds to noise between the two voice signal frequency bands and near the upper limit of the upper band. Therefore, it is not necessary to increase the cutoff frequency of the voice signal detector more than necessary, and it is possible to prevent the screen bead interference due to the generation of high frequency components during detection. In addition, in order to detect noise in the vicinity of the voice signal band, it is an excellent noise detection means capable of muting operation corresponding to the noise level that is a hearing problem. As an application of such a circuit, an optimum frequency band for each broadcast is changed by controlling a trap circuit "on" and "off" using a mode identification signal for voice multicasting and non-voice multicasting (normal broadcasting). May be set.

The embodiment of the present invention has the following features in the operation of noise detection and its setting as described above, and can perform an extremely effective operation when receiving voice multiple broadcast.

Between the noise detection circuit to which the first and second channel signals having the first and second frequency bands of the lower side and the upper side are input, and provided in the noise detection circuit, and between the first and second frequency bands. A filter having a pass band of a frequency band of? And a frequency band near the upper limit of the second frequency band; and a detection rectifier circuit for "on" "off" controlling the switching transistor according to the level of rectifying the detection output of the noise detection circuit. It is a good muting means which is provided with a simple and does not give unnecessary harmonics to other signals.

As described above, the present invention can provide an operation condition detection and processing circuit suitable for detecting various operation conditions of a television receiver and coping with the detection results, and particularly suitable for obtaining muting operation.

Claims (1)

A detection output having a so-called S-curve characteristic, which is an output of the automatic frequency tuning circuit, is applied to the first and second input terminals, and according to the detection output, the detection frequency is adjusted to the first frequency section and quasi-tuning range in the tuning range. A tuning detection circuit for obtaining an output in which the second frequency section in the second frequency section is identified and obtaining the same output as in the first frequency section in the third frequency section in this pair range, and a horizontal synchronization signal. , A synchronous detection circuit which takes the logic of the flyback pulses and obtains the output of identifying the presence or absence of both of the synchronous signals, and an intermediate voice frequency signal, and an out-of-band noise of the voice intermediate frequency. Noise detection and rectification means for detecting and rectifying the signal, and having a function to determine the presence or absence of noise, and an output of the tuning detection circuit, the synchronous detection circuit, the noise detection and rectification means. And outputs the same judgment output as the output obtained when the noise detection and rectifying means determine that the output of the noise detection and rectifying means is no noise only when the output of the output of the tuning detection circuit corresponds to the first tuning frequency section. And muting forced stop means forcibly setting to obtain an operation condition detection and processing circuit.

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