KR830002281A - I/O device control method - Google Patents

I/O device control method Download PDF

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Publication number
KR830002281A
KR830002281A KR1019790003174A KR790003174A KR830002281A KR 830002281 A KR830002281 A KR 830002281A KR 1019790003174 A KR1019790003174 A KR 1019790003174A KR 790003174 A KR790003174 A KR 790003174A KR 830002281 A KR830002281 A KR 830002281A
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KR
South Korea
Prior art keywords
input
control device
output device
control
output
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Application number
KR1019790003174A
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Korean (ko)
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KR850000561B1 (en
Inventor
미네가즈 마루오까
다쯔시 히로다니
Original Assignee
고바야시다이유우
후지쯔으 가부시기가이샤
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Application filed by 고바야시다이유우, 후지쯔으 가부시기가이샤 filed Critical 고바야시다이유우
Priority to KR7903174A priority Critical patent/KR850000561B1/en
Publication of KR830002281A publication Critical patent/KR830002281A/en
Application granted granted Critical
Publication of KR850000561B1 publication Critical patent/KR850000561B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)

Abstract

내용 없음No content

Description

입출력장치의 제어방식I/O device control method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음This content is subject to disclosure, so the full text is not included.

제1도는 본 발명을 적용할 수 있는 시스템의 블록도.1 is a block diagram of a system to which the present invention can be applied.

제2도는 제1도에 표시하는 것과 같은 시스템에 있어서의 종래의 제어 정보와 데이터의 흐름을 나타내는 도.Fig. 2 is a diagram showing a flow of conventional control information and data in a system such as that shown in Fig. 1;

제3도는 본 발명의 1실시예의 제어 정보와 데이터의 흐름을 나타내는 도면이다.3 is a diagram showing the flow of control information and data according to an embodiment of the present invention.

Claims (1)

중앙 제어 장치, 채널 제어 장치, 주 기억 장치, 입출력 장치 제어장치 및 채널 제어장치와 복수개의 입출력장치 제어 장치를 접속하는 공통버스를 가지고, 상기 중앙 제어장치 및 채널 제어장치에서 주 기억 장치를 액세스하는 것이 가능하며, 또 상기 채널 제어장치는 상기 중앙 제어장치의 지령에 의하여 공통버스인터페이스 제어에 의하여 복수개의 입출력 장치제어 장치를 통하여 각각 이것에 대응하는 입출력 장치를 제어하는 시스템에 있어서 입출력장치 제어장치의 버스감시회로에 각각 시간 감시 회로를 설치하고 주 기억장치와 입출력장치 제어장치가 채널제어장치를 통하여 데이터 전송 동작을 행할 때 정상시의 채널제어장치는 입출력 장치 제어장치에 대하여 확인의 응답 신호를 송출하고 또 채널제어 장치가 잘못을 검출하였을 경우, 이 입출력 장치 제어 장치는 상기시간 감시 회로에 의하여 상기 응답신호의 송출정지를 검출하고, 이것에 의하여 이 입출력 장치 제어장치에 대응하는 입출력장치의 애드레스 정보와 장해의 내용과를 채널 제어장치를 경우하여서 중앙제어 장치로 보고 하도록 구성되어 진것을 특징으로 하는 입출력장치의 제어방식.It has a central control unit, a channel control unit, a main storage unit, an input/output unit control unit, and a common bus connecting the channel control unit and a plurality of input/output unit control units, and accesses the main storage unit from the central control unit and the channel control unit. In addition, the channel control device is a system for controlling the input/output device corresponding to each of the input/output device control devices through a plurality of input/output device control devices by common bus interface control according to the command of the central control device. When each time monitoring circuit is installed in the bus monitoring circuit and the main memory device and the input/output device control device perform data transmission operation through the channel control device, the channel control device in normal condition sends a response signal of confirmation to the input/output device control device. In addition, when the channel control device detects an error, the input/output device control device detects the transmission stop of the response signal by the time monitoring circuit, and thereby the address of the input/output device corresponding to the input/output device control device. A control method of an input/output device, characterized in that it is configured to report the contents of information and obstacles to the central control device in the case of a channel control device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed according to the contents of the initial application.
KR7903174A 1979-09-14 1979-09-14 Control method for i/o devices KR850000561B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR7903174A KR850000561B1 (en) 1979-09-14 1979-09-14 Control method for i/o devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR7903174A KR850000561B1 (en) 1979-09-14 1979-09-14 Control method for i/o devices

Publications (2)

Publication Number Publication Date
KR830002281A true KR830002281A (en) 1983-05-23
KR850000561B1 KR850000561B1 (en) 1985-04-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR7903174A KR850000561B1 (en) 1979-09-14 1979-09-14 Control method for i/o devices

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Publication number Publication date
KR850000561B1 (en) 1985-04-26

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