KR830002257B1 - Synchronizer of TV receiver - Google Patents

Abstract

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Description

Synchronizer of TV receiver

The accompanying drawings are block diagrams of one embodiment of a television receiver according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a television receiver for receiving television signal mixed scan lines and image synchronization pulses, and a plurality of image planes configured to form one image. Between a scan line oscillator for generating power within a condition, a reference signal induced by the received scan line sync pulse and the scan line oscillator signal, and a reference signal for controlling the frequency and phase of the scan line sync pulse and the scan line oscillator, or one of them A device for supplying a scan line synchronization signal connected to a scan line oscillator circuit adapted to generate a control signal in accordance with a phase relationship of? And a scan line oscillator connected to the scan line oscillator for generating pulses of an image frequency from the scan line oscillator signal Frequency minutes A circuit, an apparatus for supplying a pulse generated due to said frequency division circuit connected to an image comparison stage for comparing the phase of the received pulse according to the frequency of the received image synchronization pulse and the divider pulse, and a given phase relationship A device for determining the time during which is not present in the comparison stage between the above comparison, a device for supplying a received image synchronization pulse connected to the frequency division circuit for resetting, and an image deflection output stage. Between the connected image synchronous control stage and the external synchronous operation mode suitable for supplying the dispensing pulse to the image output terminal and the external synchronous operation mode suitable for supplying the signal or the received image synchronization pulses from the image output terminal. Control phase that is capable of switching on the If not, the video control stage is adapted to switch from the internal sync mode to the external sync mode, and to switch from the external sync mode to the internal sync mode when a given phase relationship in the image comparator exists for a predetermined period. And a synchronizing device comprising a video control stage, and a frequency divider circuit, etc., to which a received video synchronizing pulse is supplied for resetting.

In such a television receiver, as soon as the scanning line oscillator enters the synchronous state, the frequency divider pulses always have an image frequency, so frequency division is performed. It is usually done fairly quickly after the receiver is switched on. The exact phase of the image frequency pulse applied to the image output stage is related to the phase of the image synchronization pulse generated from the transmitter, the phase received by the television receiver, and the phase received by the television receiver is formed as a coincidence gate. Secured by a stage, the relevant device for determining the time can be formed as an integrator or a counter.

When the signal applied to the comparator stage has a given phase relationship, the so-called internal synchronous mode is as if the divider pulse is applied to the video output stage where it is placed for the purpose of image (vertical) deflection. It is only used for comparison and cannot reach the frequency divider circuit. Therefore, in the internal synchronization mode, external interference and noise do not interfere with the operation of the image synchronization circuit device.

When the signal applied to the comparator does not have a given phase relationship, the external synchronous signal is applied to the image output terminal as much as possible via a forming circuit such as a synchronized oscillator and formed into one counter to reset it. The frequency divider must be reached and this phase condition is established in the comparison stage. This phase condition occurs immediately after the receiver is switched on or when a given phase relationship condition is lost for some reason, for example interference. After the divider is reset by the received image synchronizing signal, the divider pulse returns to the correct phase.

A given phase relationship can be formed as a result, since the control stage can switch from an external synchronization mode to an internal synchronization mode. However, it is desirable to delay this conversion in order to achieve a given phase relationship with certainty over the number of image periods or to distinguish normal television transmission signals from other television signals. It is different from the number specified in the television device. Our patent specification No. 1,445,456 describes a device for making and using periodically occurring gating pulses until it is confirmed that the incoming sync pulses are normal pulses while one gating pulse occurs. The conversion is delayed. In the opposite case, the device remains in external synchronization mode. It is evident that the effect of the anti-noise requirement is that the period of the external synchronous mode must be made as short as possible before the change can occur.

Signals that occur during the generation of the internal sync mode are not used in many air devices because one image sync pulse has been lost due to interference, and are instructed to switch to the external sync mode immediately with a given phase relationship. In some successive cases, only when a given phase relationship is lost, the image synchronizing circuit arrangement determines that the divider resets the external synchronization pulses and determines that the divider pulses are carried to the output stage. On the other hand, all interferences cause vertical instability of the displayed image because the continuous image plane periods do not coincide.

Therefore, the delay in switching the external synchronous mode is a particularly desirable feature after switching on the receiver when the in-phase look has not yet occurred.

However, the delays mentioned above are often made quite long. The last pulse of the preceding pulse train does not occur immediately after the new sync pulse train at the appropriate frequency receives the first pulse and is expected. This phase change occurs at camera switching in the receiver or transmitter, resulting in a constant loss of a given phase relationship even though a normal sync signal is received. Most video synchronization circuits are based on the principle of division and consist of comparison stages as already described by experience. However, since the internal sync mode is already activated before the change, no operation is changed before the above mentioned delay is completed. This results in an incorrect phase position of the signal applied to the image output stage and causes image deflection. In response to the image blanking pulse, a horizontal black bar is continuously displayed on the imager tube screen of the receiver, a portion of the image is displayed on the bar, the rest is displayed below and the bar is fixed. Black bars do not appear at the end of the delay, during which time the image is accurate. The image synchronizing circuit device has a re-established synchronization by recognizing a new phase position of the received image synchronizing pulse.

The phenomenon described above does not matter much if its duration is very short. This is not because of interference-free requirements. The above-mentioned patent specification has a time interval of 16 image periods of 0.32 seconds for an image frequency of 50 Hz. Although the delay is reduced to eight cycles, or 0.16 seconds, experience shows that the black bars described above are inconvenient. It is an object of the present invention to reduce the above mentioned delay and to achieve this object the present invention provides a television receiver of the type described with the following features. The image control stage is adapted to be switched from the internal synchronous mode to the external synchronous mode under the control of the scan line oscillator control circuit, and then between another reference signal derived from the scan line sync pulse and the scan line oscillator signal, or between one of them. The phase of is different from the given phase relation.

It is apparent that according to the invention the above mentioned delay can be virtually reduced when exhausted. Therefore, it can be maintained when used without being affected by interference and noise. The image synchronizing circuit apparatus can provide unnecessary criteria for this purpose and this information can be obtained by specifying from the scanning line oscillator control circuit.

The scanning line oscillator control circuit includes a scanning line coincidence detector for determining when the scanning line synchronizing pulse and another reference signal occur at the same time or not, and the television receiver according to the present invention when the pulse and the signal do not occur at the same time. The output of the scan line oscillator control circuit is applied to the external synchronization mode to switch the image control stage.

The image plane control stage is adapted to be operated by switching from one synchronization mode to the other synchronization mode under the command of the mode selection circuit, and the received image plane synchronization pulse is provided so that the frequency division circuit is reset. The television receiver according to the present invention in which the mode selection circuit is in a state for instructing the image plane control circuit to be in the internal synchronization mode when the pulses applied to the image plane comparison stage occurs simultaneously for a predetermined period of time is different from the scan line synchronization pulse. And when the reference signal or any one of them does not occur at the same time, the mode selection circuit is in a state for instructing the image plane control circuit to be in an external synchronization mode.

The television receiver as described above is characterized by being in a state for commanding the image plane control circuit so that the mode selection circuit is in the external synchronization mode immediately after switching on. The television receiver according to the present invention, which consists of a bistable element that receives the set pulse from the image plane comparison stage when the mode selection circuit does not exist for a predetermined period of time in the image plane comparison stage, The bistable element is characterized by receiving a set pulse derived from the scan line oscillator control circuit when it differs from its given phase relationship between any other reference signals. The television receiver image plane control stage according to the present invention comprises a switch for applying a received image sync pulse or one of signals derived therefrom and a divider pulse to an image plane output stage, wherein the switch is the bistable. Operation is controlled by the output signal of the device.

The present invention provides an equivalent device for using an integrated semiconductor body in which the above-mentioned television receiver and circuit elements are mixedly connected.

In the figure, reference numeral 1 denotes an antenna on which a television signal can be received. This signal is supplied to the signal stage 2, in which it is amplified and processed in order to apply an appropriate signal in a known manner to each of the image display tube and the loudspeaker (not shown). When a video signal is supplied to the synchronizing separation stage 3, a composite synchronizing signal appears at its output stage.

This signal contains, for example, a scan line synchronization pulse having a scan line repetition frequency of 15.625 or 15.705 Hz, which is supplied to the input terminal of the AND gate 4. A smoothing circuit supplied to the first phase discriminator 5 of the gate 4 and acting as a controllable switch, the output terminal of which is formed via the resistor 6 together with the resistor 6 to form a first low pass filter. Connected to (7). The scan line synchronization signal is also supplied to the input terminal of the AND gate 8, and its output signal is supplied to the second phase discriminator 9, which also acts as a controllable switch, whose output terminal is modulated via a resistor 10 2) is connected to a circuit (7) forming a regional pass filter. The voltage generated by the operation of the circuit 7 is supplied to a voltage regulated scan line oscillator 11 for adjusting the frequency and phase or one of them.

The oscillator 11 generates a sawtooth waveform signal having a frequency twice the scan line frequency when it is nominal. The sawtooth signal is supplied to the pulse generator 12 as it is inverted into a pulsed signal, the initial end of which is traced to the pulse generated in the manner described so far and generated in accordance with the voltage supplied to the generator 12. As soon as is generated, it is generated simultaneously with the rising end of the sawtooth wave. The signal of the generator 12 is supplied to the frequency divider circuit 13 so that its frequency is divided into two so that the output signal has a scan line frequency. One of the output signals of the divider circuit 13 is supplied to the switches 5 and 9 as a reference signal, and the remaining output signals of the divider circuit 13 are supplied to the driver and the scan line output terminal 14. Although not shown, the output stage 14 supplies the scan line frequency current to the horizontal deflection coil in the image display tube.

The scan line flyback pulses appearing at the output stage 14 are supplied across the windings of the line transformer, to the input terminal of the end gate 15, and the remaining input terminals of the division circuit 13 supply the reference signal. Is connected to the output terminal of). The output terminal of the gate 15 is connected to the input terminal of the or gate 16 and its output terminal is connected to the input terminal of the gate 4 and the controllable switch 17. The pulse generator 18 converts the signal of the oscillator 11 into a pulsed signal having a scanning line frequency, the initial end of which is the initial stage of the oscillator signal while the tracking end is generated immediately according to the voltage supplied to the generator 18. Occurs along the end. The pulse signal generated by the generator 18 is supplied to the remaining input terminals of the gate 16. The switch 17 is a phase discriminator, which is also supplied with a reference signal from a suitable output terminal of the frequency divider circuit 13, and its output voltage is a low pass filter which generates a voltage supplied to the above-mentioned pulse generator 12 ( 19) is smoothed.

The scanning line synchronization and deflection circuit arrangement described herein is described in more detail in patent application 48,654 / 78 (PHN 899), which has not been published except for components 8, 9 and 10. The circuit arrangement includes two control loops for controlling the signal generated at the output terminal of the gate 16 and the signal supplied to the gate 4 for generating the gate pulse for keying the scan line synchronization pulse. The phase discriminator 5 operates only for a short period of time between the syringes. The gate pulse is located in a substantially similar fixed form with respect to the end of the reference signal derived from the oscillator signal. The adverse effect of the phase change occurring at the output stage 14 is virtually compensated for by the change in the shielding time of the switch mounted thereon. The position of the initial end of the gate pulse depends on the shielding time of this switch, whereby the position of the tracking end depends on the voltage supplied to the generator 18. The voltage can be adjusted and alternately induced from the control voltage supplied to the oscillator 11.

The scan line flyback pulses generated from the output terminal 14 are supplied to one input terminal of the scan line coincidence detector 20, and the scan line sync pulses induced from the sync separation terminal 3 are supplied to the other input terminal. The output terminal is connected to the input terminal of the AND gate 8. The function and operation of this part of the scanning circuit device, such as the scanning line, is described in a slightly different embodiment in patent application No. 40632/76 and German patent application No. 751163 already filed by the present applicant.

The phase discriminator 5 operates only when the synchronization condition of the oscillator 11 is achieved. Because the resistor 6 has a relatively high value, the sensitivity is low, the time constant of the first low pass filter is formed by the resistor 6 and the network 7 is long. The oil phase discriminator 5 supplies a relatively small current to the filter. It is more important that it is due to the output pulse induced from the end gate 4. Both conditions significantly reduce noise but involve some synchronization. If the detector 20 detects an asynchronous state, the second phase discriminator 9 is activated by the output signal of the AND gate 8. Resistor 10 has a relatively low value. The phase separator 9 is provided by the resistor 10 and the network 7 and supplies a large amount of current to the second low pass filter having a relatively short time constant. The AND gate 8 therefore does not receive a gate pulse and the operation of the phase discriminator 9 is not stopped.

In other words, it's working for the whole syringe. In such a case, the control loop is quickly extinguished because of the wide synchronous inlet range, and then the limited range is controlled by the phase discriminator 5.

The output signal derived from the scanning line oscillator 11 is supplied to the frequency dividing circuit 21, and its frequency is divided to about 625 or 525 lines per image, for example. When the oscillator 11 has its nominal frequency, after the frequency of the scanning line synchronizing circuit device described above is synchronized, the frequency of the output signal of the divider 21 is imaged such that the television receiver is normalized to 50 or 60 Hz, for example. Match to frequency. This condition is typically reached after a shorter period of time than one imaging period, for example 20 or 16.7 microseconds.

The image synchronization pulses present in the composite synchronization signal useful as the output of the synchronization separation stage 3 are obtained by the image synchronization separation stage 22 in a known manner. The image frequency pulses obtained by the divider 21 must have a fixed phase associated with each of the separated image sync pulses shown at the output terminal of the sync separation stage 22. Both the divider pulses and the image sync pulses are applied to the image matching terminal 23, and its output terminal is connected to the counter 24. The output terminal of the counter 24 is connected to the input terminal of the or gate 25, and the other input terminal is connected to the output terminal Q of the mode selection circuit 926. The image synchronizing pulses displayed at the output terminal of the separating terminal 22 are induced from the image oscillator 27 and the gate 25 and the input terminal and circuit of the AND gate 28 through the switch 32 controlled by the output signal. It is applied to the input terminal of (26).

The video oscillator 27 is a free-running oscillator that generates a fundamental frequency lower than the video frequency. It is continuously triggered by the received image sync pulses, whose signal has the phase and frequency of these pulses. This signal is applied to any one of the selector contacts of the controllable switch 29 and the rest of the selector contacts are connected to the output terminal of the divider 21 while the main contact of the switch 29 is connected to the image output terminal 30. Connected. Although not illustrated, the image output terminal 30 supplies an image frequency current to a vertical deflection coil in the image display tube.

Either of the divider pulse or the image oscillator pulse is applied as a control signal to the image output terminal 30 depending on the position of the switch 29. The operation derived from the divider pulse is already referred to as internal synchronous mode. In addition, the operation derived from the image oscillator pulse is described as an external synchronization mode. The position of the switch 29 is controlled by the output signal derived from the or gate 25. The output signal derived from the switch 29 is applied to a pulse generator 31 having two output terminals, one of which is connected to the input terminal of the end gate 28 and the other to the circuit 26. It is connected to the input terminal of. The generator 31 can be triggered by the output signal derived from the or gate 25. The output terminal of the AND gate 28 is connected to the reset terminal R of the divider 21 and to the input terminal of the circuit 26. As a result, the output terminal of the scan line matching detector 20 is connected to the input terminal of the circuit 26.

Imaging and deflection circuit arrangements incorporating parts indicated by reference numeral 21 to bolt 32 exclude the already mentioned connection between scan line coincidence detector 20 and mode selection circuit 26 that are not shown in the published patent specification. Is similar to the device described in our Patent Application No. 1,445,456. Except for the connection mentioned above, the operation of the device is as follows.

The counter 24 calculates the number of inconsistencies that occur between the pulses applied to the coincidence stage 23. If the inconsistency becomes a predetermined number, for example 1, after being in equilibrium, the counter 24 leads logic 1 to the or gate 25. It is assumed that there are two states corresponding to the two girds of operation, the mode selection circuit 26 is still in the state of the internal synchronization mode and its output is logic (0). In this state, the output signal of the OR gate 25 conducts the switch 32 and places the switch 29 in a position such that a pulse generated by the oscillator 27 is applied to the output terminal 30 (external synchronizer). It becomes the logic (1) to set. The pulse generator 31 generates two series gating pulses, both of which have the same repetition ratio as the image frequency divided by an integer such as 16, and each pulse has approximately one image period. have. The output from orgate 25 is applied to set a generator 31 that generates a primary gating pulse and applies it to the AND gate 28. Since the synchronous pulse is generated during the generation of the first gating pulse, the output signal of the AND gate 28 becomes logic 1 and resets the divider 21, during which the mode is selected to correspond to the operation in the external synchronous mode. The circuit 26 is set, the output signal of which becomes the logic 1 and the output signal of the five hundred and twenty five retains the logic 1.

When the incoming television signal is a normal television transmission, the in-phase state remains unchanged inside the coincidence stage 23 during successive video cycles, so that the output signal of the counter 24 has a logic (0) do. After the generation of the gauging pulse, e.g. after a given number of image periods such as 16, a second gating pulse is generated by the pulse generator 31 and the pulse is applied to the selection circuit 26. The coincidence of the sync pulse and the divider pulse is closed while the second gating pulse is generated, and the pulse sets the mode selection circuit 26 in a state corresponding to the operation of the internal synchronous mode, and its output signal is logic (0). Becomes As a result, the output signal of the or gate 25 becomes the logic (0), and the divider pulse generated from the divider 21 is supplied to the output terminal 30, so that the switch of the switch 29 is determined and the switch 32 is It is open and the image motion and pulses are no longer applied to the AND gate 28. These pulses and the first gating pulses derived from the generator 31 applied to the gate 28 do not affect the divider 21.

When the incoming television signal is not a normal television transmission call, the mismatch state is closed by the coincidence stage 23 and the counter 24 while the second gating pulse is generated. The mode selection circuit 26 is maintained in a state corresponding to the state of the gates 25 and 28 and the operation of the external synchronization mode as long as the operation states of the switches 29 and 32 are not changed. While the first gating pulse is generated, the output signal of the AND gate 28 becomes logic 1 and resets the divider 21 to start a cycle of 16 new video cycles, after which the incoming signal is a normal signal. Determine whether or not.

After switching, the receiver on the mode selection circuit 26 enters a state corresponding to the external synchronization mode immediately or after 16 image cycles. The output signal thereof and the output signal of the or gate 25 become the logic (1). The switch 32 is energized while the pulse generated by the oscillator 27 is supplied to the output terminal 30 via the switch 39. The generator 31 is triggered to generate a first gating pulse while the output signal of the AND gate 28 changes to logic 1 and the divider 21 is reset. The coincidence state is made in the coincidence stage 23 after switching as described above during the second gating pulse operation by the operation of the internal synchronization mode if the received television signal is a normal signal.

If no image synchronization pulses are noise or interference or one of the reasons is not useful for the output terminal of separation stage 22, there is no matching in matching stage 23 and logic 1 is counter 24. After the delay time determined by the orifice 25 will be applied to the or gate 25 as a result the device will result in the operation of the external synchronous mode and reset during each occurrence of the first gating pulse. The device is ready to operate normally when the sync pulse reappears, while the image oscillator 27 oscillates at the natural frequency, causing it to "roll over" in the vertical direction unless the indicated video shift pulse is present. .

After the above mentioned delay is completed, the apparatus is in a state of being performed before the sync pulse disappears. In other words, if the device operates in an internal synchronization mode, a divider pulse is applied to the image output stage 30. When switching cameras in a receiver or transmission station, such as after channelization may occur as a result of phase jumps occurring in the image synchronization pulses, which is countered by the counter 24 to logic 1 as described above. This results in a horizontal black bar appearing on the screen of the imager until it is introduced into the operation of the external synchronization mode. The purpose of the connection of the scan line coincidence detector 20 and the mode selection circuit 26 is to shorten the delay in order not to be adversely affected by the provided noise protection characteristics.

While the normal synchronous operation is performed, the scan line coincidence detector 20 does not apply a signal to the AND gate 8 or the mode selection circuit 26. If the phase jumps occur in series of image sync pulses as mentioned above, it is clear that similar jumps are occurring in the scan line sync pulses. The inconsistency is detected by the scan line coincidence detector 20 as a result, and the detector selects a mode selection circuit for causing the output signal to be logic 1 regardless of the phase difference in which one signal exists in the coincidence stage 23 ( Switch the wideband phase discriminator 9 to readjust the scan line equivalent circuit arrangement during application to 26). If the inconsistency state is less than 16 detected by the image matching stage 23 and the counter 24 at this time, the output signal of the counter 24 becomes logic (0). The or gate 25 maintains the logic 1 even when the divider circuit 21 is reset due to the operation of the external synchronization mode, during which the gating pulse is started. After a relatively short time, the scan line synchronization loop obtains its synchronization state, and the scan line coincidence detector 20 is positioned off by the phase discriminator 9 to control a wide range and detects the coincidence state. In the meantime, no information is sent to the mode selection circuit 26, thereby maintaining a state corresponding to external synchronous mode operation. This state remains unchanged until the generation of a subsequent second gating pulse, regardless of whether the image synchronization circuit is switched to internal mode operation while the determination is made as above.

After the receiver is switched, i.e., when the synchronous circuit device is still in the synchronized state, the mode selection circuit 26 is in a state corresponding to the operation of the external synchronous mode, i.e., with its output signal being logic (1). In the device. The command from the scan line coincidence detector 20 as described above has no effect on the image synchronization circuit arrangement. If one or more of the image synchronization pulses during a normal reception period are lost, for example because they are indistinguishable from noise, the scan line synchronization pulses are normally received and processed, and one or more mismatch conditions affect this operation. The strike is counted by the counter 24 even if there is no scan line coincidence detector 20, and detected by the coincidence stage 23. It is evident from the already mentioned that the delay induced by the counter 24 necessary for satisfactory noise protection is maintained since it is virtually reduced whenever it is not beneficial. If the opposite condition occurs, i.e., if the image synchronization pulses are satisfactory in reception, on the other hand, if several scan line synchronization pulses are missing, the frequency of the scan line oscillator 11 and the frequency of the divider pulse change. However, the signal supplied to the image output terminal 30 has an appropriate image frequency by causing the scan line coincidence detector 20 to immediately operate the image synchronization circuit device by the operation of the external synchronization mode.

The scan line coincidence detector 20 is not located at any fixed place in the scan line oscillator control circuit, and instructions therefrom can be sent to the mode selection circuit for the purpose of reducing the delay induced by the counter 24. When a mismatch exists in the coincidence detector 20, a large current is supplied to the circuit 7, resulting in a large ripple voltage shown there. This voltage, which is substantially reduced in the scan line in-phase state, can be used for the mentioned command. The same can be done when the operation of the scan line oscillator control circuit is not stopped by the gate pulse.

The advantage of connecting to the mode selector circuit 26 is that it is possible to use components in an integrated circuit, for example a Mullard type TDA 2576. However, it can also be used for other devices that are not configured such as mode selection circuits. The connection of either scan line coincidence detector 20 or circuit 7 can be connected to switches 29 and 32 to produce similar results.

Some of the features described above are not essential to the invention. As a scan line oscillator 11 having a scan line frequency, it can be used as a divider 21 which divides or alternately by a number such as 312.5 or 262.5, respectively, and is doubled before being divided by 625 or 525 respectively. Similarly, a free-running oscillator 27 can be nested between the switch 29 and the image output stage 30, which oscillator is divided by the received image sync pulse or via the switch 29. Synchronized by a pulse. Such a device is actually described in our patent specification number 1,445,456 mentioned above, wherein the divider is not immediately reset when the device is switched to the operation of the external synchronization mode. This is due to the fact that a pulse generator similar to generator 31 in this application is not triggered by an output signal of a gate similar to orgate 25 herein.

The accompanying drawings include an embodiment of a mode selection circuit 26. The AND gate 33 receives the separated image synchronization pulses generated from the generator 31 and the separating end 22, and the second gating pulses generated by the pulses generated from the division circuit 21. The output terminal of the gate 33 is connected to the reset terminal of the flip-flop 34 whose output terminal Q is connected to the input terminal of the or gate 25. The output signals of the AND gate 28 and the scan line coincidence detector are applied to each input terminal of the or gate 35 whose output terminal is connected to the set terminal of the flip-flop 34. If the circuit 26 realized in this way is as described, i.e. if the input signal of the AND gate 33 is matched, it is reset (Q = Q), and if the input signal of the or gate 35 appears, it is set ( It will be readily understood that the function of Q = Q) can be achieved. The scan line match detector 20 is well known in the art and thus is not described in detail. A possible embodiment is shown in our patent serial number 1,512,045.

Claims (1)

Scan line oscillator suitable for reception of television signal mixed scan lines and image synchronization pulses, and for oscillating in a synchronized state with a plurality of image planes suitable for forming one phase, and having a frequency such as scan line frequency or integral multiple. 11) and a scan line oscillator control circuit 5, 6, 7, 9, 10 configured to generate a control signal depending on the phase relationship between the scan line synchronization signal pulse and a reference signal for controlling the phase or frequency of the scan line oscillator. 20, a frequency divider circuit 21 connected to the apparatus for providing a reference signal derived from the scan line oscillator signal and the received scan line sync pulses, and the scan line oscillator for generating pulses of an image frequency from the scan line oscillator signal. ) And the phase of the received pulse according to the frequency of the received image sync pulse and divider pulse. A device for supplying a pulse generated by the frequency division circuit connected to the image comparison stage 23 for comparison and for determining the time during which no given phase relationship exists within the comparison stage between being compared there A device 24, a device 32 for supplying a received image synchronization pulse connected to the frequency division circuit for resetting, and an image deflection output terminal 29 are connected to the image deflection output terminal 30, and an image output terminal. Controllable to switch between the internal synchronous operation mode, which is suitable for supplying the dispensing pulses to the external synchronization mode, and the external synchronous operation mode, which is suitable for supplying the received signal or the received image synchronization pulse from the image output stage. However, when the given phase relationship does not exist for a predetermined period, the image control stage switches from the internal synchronization mode to the external floating mode. And an image control pulse which is adapted to be switched from an external synchronous mode to an internal synchronous mode when a given phase relationship in the image comparison stage is present for a predetermined period of time, and a received image synchronous pulse to reset. In a television receiver suitable for a receiver containing a synchronizing device composed of a frequency divider rotation, etc., another reference signal derived from the scan line synchronization pulse and the scan line oscillator signal is obtained by the image control stage 29. Televisions characterized in that they are adapted to switch ceramics from the internal synchronous mode to the external synchronous mode under the control of the scanning line oscillator control circuits 5, 6, 7, 9, 10, and 20 when the phases are different from the given phase relationship. Synchronizer of the receiver.

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