KR830001850B1 - receiving set - Google Patents

Abstract

No content.

Description

receiving set

1 is a block diagram showing an embodiment of a receiver according to the present invention.

FIG. 2 is a block diagram showing an embodiment of the delay circuit shown in FIG.

The present invention starts the scanning operation when the electric field strength is weak under the influence of the start signal depending on the electric field strength of the received transmitter to tune the receiver to the next tuning data every time from the tuning data group stored in the memory circuit. The present invention relates to a receiver having a search tuning circuit.

The receiver of the above-described type is already known in the art, and the searching operation of such a receiver is started when the electric field strength of the transmitter with which the receiver is tuned is reduced below a predetermined value. When used in the above, there is a drawback that in some situations, the decrease in electric field sensitivity (by vehicle noise, etc.) occurs very frequently.

Accordingly, the present invention aims to prevent such a situation.

The receiver according to the present invention is characterized by having a delay circuit for delaying the generation of the start signal with respect to the occurrence of the field strength signal reduction.

According to the present invention, the search operation is not immediately initiated at the time of decreasing the field strength, or is searched by the state of the field strength, e.g., the duration of the field strength reduction, or the progression depending on the frequency of the field strength reduction or the duration and frequency thereof. The number of operations is limited so that good sound reproduction is possible.

The invention will be explained in more detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, an antenna signal is supplied to an input terminal 1 of a high frequency and mixing section 3 of a receiver, and a signal generated from the oscillator 7 is transmitted to a high frequency and mixing. Supply to the input terminal 5 of the unit (3). The intermediate frequency signal supplied to the intermediate frequency amplifier 11 is derived from the output terminal 9 of the high frequency and mixing section 3.

The oscillator 7 constitutes a part of the frequency synthesizing circuit, and divides the divisor of the quasi cycle 15 which divides the frequency of the signal generated from the oscillator 7 and supplied to the work terminal 17 of the divider 15. The frequency synthesizing circuit is tuned by supplying tuning data in the form of digital code to be adjusted to the input terminal 13 of the divider 15. The signal whose frequency is determined by the oscillation frequency and the divisor of the quasi cycle 15 is obtained from the output terminal 19 of the splitter 15. This signal is compared with the jumble signal supplied from the jumble oscillator 23 in the phase detector 21, and these two input signals are derived from the control signal output terminal 25 of the phase detector 21 to control the oscillator 7. The control signal supplied to the signal input terminal makes the frequency and phase equal to each other. This allows the receiver to tune to the frequency determined by the tuning data.

The tuning data supplied to the input terminal 13 of the divider 15 is supplied from the output terminal 29 or 31 of the memory circuit 33. In other words, the tuning data from these output terminals is coupled to the input terminal 13 of the divider 15 through the gate circuit 35 or 37.

The memory circuit 33 has two circular memories 39 and 41, each of which has a tuning data group, and each output terminal 29 in response to a clock pulse supplied to the input terminal 42. ), (31) can supply different tuning data each time. By properly selecting the tuning data group, the data receiver can be tuned to a transmitter having the same characteristics as a plurality of transmitters transmitting the same program.

By the gate circuits 35 and 37, it is possible to select which cyclic memory, i.e., from which tuning data group, is to be supplied to the frequency divider 15 from the cyclic memory. This is done by a switching signal coming from the switch closed in the switch 43 or 45 of the control apparatus 47. In such a case, since the signal is supplied to the AND gate 49 through the OR gate 48, the reception condition signal corresponding to the logic value 1 is supplied to the upper (third) input terminal of the AND gate 49. In this case, the clock pulse generated by the clock signal generator 51

Next, an aspect in which the reception condition signal is detected at the output terminal of the AND gate 53 will be described. When receiving the transmitter signal, the intermediate frequency amplifier 11 supplies the intermediate frequency signal to the amplitude detector 54 and the frequency detector 55. The amplitude detector 54 has an output terminal 57, from which the intermediate frequency signal rectified is supplied to the input terminal 59 of the delay circuit 61 of the type which depends on the state of the electric field strength. This delay circuit 61 does not delay the rising edge of the signal at the output terminal 57 of the amplitude detector 54. In descent

The logic signal indicated as the letter a is generated at the output terminal 63 of the delay circuit 61. Signal a has a logic value 1 if the received transmitter has sufficient field strength and is within the bandwidth of the intermediate frequency amplifier 11. When the receiver is an FM receiver, this bandwidth is large, and upon reception of the transmission signal, the signal a becomes the logic value 1 very quickly.

The signal a appearing at the output terminal 63 of the delay circuit 61 is supplied to the input terminal 71 of the limiter 73 through an integration circuit composed of the resistor 67 and the condenser 69. The limiter 73 sends a logic signal b from the output terminal 75 and supplies it to the inverting input terminal of the AND gate 77. This signal b is slightly delayed with respect to signal a as a whole.

Thus, the AND gate 77 generates a signal ab ', which is the AND gate over a short period immediately after the occurrence of each forward direction edge in the signal a because of the inversion in the input terminal of the AND gate 53. The 53 is made impossible to transmit, thereby causing the AND gate 49 to become impossible to transmit so that the search operation of the receiver is stopped during this short period. The frequency detector 55 has two output terminals 81 and 83, on which output signals from which unwanted high current components are removed. The level and the way these signals are opposite

The AND gate 94 generates a logic signal ac, which is supplied to the inverting input terminal and switch 95 of the AND gate 53, which switch 95 is the output terminal 96 of the frequency detector 55. ) Is installed in the low-frequency signal path of the receiver to the playback device 97.

When the transmission signal received while the search operation is suspended by the signal ab 'has the appropriate frequency, the logic signal ac received by the AND gate 94 becomes the logic value 1, and this signal is the AND gate ( 53), the AND gate 49 remains untransmittable. In such a case, the audio channel is established via the switch 95. If the received transmitter does not have an appropriate frequency, the signal ac remains at a logic value of 0, and the search operation is started again immediately after the signal ab 'becomes a logic value of 0.

The AND gate 53 generates a logic signal ac '(ab') '= a' + bc ', which is a reception condition signal, which provides a sufficient electric field strength and an appropriate frequency as described above. The search tuning operation of the received transmission signal is stopped. This is initiated by the undelayed forward edge of signal a.

When the electric field strength decreases below a predetermined value, the resumption of the search operation is started again by the negative edge of the signal a generated when the signal a becomes from the logic value 1 to the logic value 0. In such a case, the output signal a '+ bc' of the AND gate 53 becomes a logic value of 1, and the clock pulse for causing the search operation to perform the search operation because one of the switches 43 and 45 is still closed. Transmitted via 49. As described above, the falling edge of the signal a is delayed with respect to the instant when the electric field strength of the received transmitter is reduced and becomes below a predetermined value.

Moreover, of course, if necessary, the receiver is tuned to the tuning data other than the tuning data obtained from the memory circuit 33. This is illustrated as a cut line in FIG.

The receiver of the present embodiment is provided with a frequency synthesizing circuit having a variable divider, but of course, another type of frequency synthesizing circuit may be used as an alternative.

Several functions that may be performed simultaneously in the receiver of this example may continue to be performed if the receiver has a microprocessor.

The above-described search assistant circuit is particularly good for an FM radio broadcast receiver, and in particular, the field of use, which is not good for a vehicle receiver, is not limited to this. For example, the receiver of the aircraft can be improved by this search tuner circuit.

Moreover, it is apparent that the function according to the present invention can be performed by combining the combination of the gate, the detection circuit and the limiter in a number of forms other than those described above. The subtractive condition signal or composite portion thereof may, for example, be combined with other signals supplied to the AND gate 49 and the OR gate 48 as an alternative.

As a frequency detector, it can be used as any type of detector that can accurately determine frequency data without requiring a means to limit the bandwidth.

If necessary, the memory circuit of the receiver may include one or more groups of tuned data.

In the case of using a delay depending on the state of the electric field strength in the start signal, the above-mentioned pause and start again are not necessarily necessary at the time of receiving a transmission signal having an unnecessary frequency, and thus can be omitted. Therefore, only the inverted signal of the signal a can be used as the reception condition signal.

Further, the falling and rising edges of the signal a can be processed by several circuits, and this can be supplied as start and stop signals, respectively, to the start-stop memory for generating a receive condition signal.

FIG. 2 shows an embodiment of the delay circuit 61 in the embodiment of FIG. 1, and in FIG. 2, elements corresponding to those in FIG. 1 are shown with the same numerals. The input terminal 59 of the delay circuit 61 is supplied with an electric field strength dependent signal, which is converted into a logic signal P by the limiter 10, and this signal P is provided at a sufficient electric field strength for good reception. The logic is 1, and if the electric field strength is not sufficient, the logic value is 0.

The logic signal P is supplied to the command input terminal 103 of the first counter 105 through the inverter 102, and also the set input terminal 107 of the flip-flop 109 and the set input of the first counter 105. It is supplied directly to the terminal 113. The 117 clock pulses generated by the clock signal generator are supplied to the input terminal 115 of the first counter 105 having four output terminals 119, 121, 123, and 125.

When the non-signal P is a logic value of 1, the first counter 105 is maintained in a set state through the input terminal 113, and the counting operation is performed by the inverted signal P at the command input terminal 103. It is stopped. In such a case, each of the output terminals 119, 121, 123, and 125 of the first counter 105 becomes a logical value of zero. These output terminals are connected to the input terminals of the AND gates 127, 129, 131, and 133, respectively, and the output terminals of these AND gates are connected to the input terminals of the OR gate 135, and the OR gate 135 ) Output terminal is connected to the reset input terminal 137 of the flip-flop (109). Ta

When the signal P becomes a logic value 0 as a result of the decrease in the electric field strength, the first counter 105 is no longer blocked by the signal of the logic value 1 in the forget terminal 105 and the input terminal is no longer blocked. Since the reset signal at 113 becomes the logic value 0, the first counter 105 starts counting. When the logic value is 0 over a sufficiently long period of time, the output terminals 119, 121, 123, and 125 of the first counter 105 have periods τ, 2τ, 4τ, 8τ, and 16τ. Later, it becomes a logical value of 1, in which case τ is chosen to be a value between about 100 m seconds and 400 m seconds, and preferably about 200 m seconds is particularly large. At this time, this about 200 m second can be corresponded to four clock pulses.

AND gates 127, 129, 131, and 133 are operated by a second counter 141, and now the second counter 141 is estimated to have a coefficient of -1,0,1 or 2. . When the counter value of the counter 141 is -1, the output terminal 143 and the output terminal 145 of the counter 141 become the logic value 1, while the output terminal 147 becomes the logic value 0. If the counter value of the counter 141 is 0, the output terminals 143, 145, and 147 are logical values. If the counter value of the counter 141 is 1, the output terminals 145 are logical values. 1, and the output terminals 143 and 147 become logical values 0, and when the counter value of the counter 141 is 2, the output terminals 145 and 147 of the counter 141 become logic values 1 And the output terminal 143 becomes logical value 0.

The output terminal 143 of the second counter 141 is connected to the other input terminal of the AND gate 127 and the inverting input terminal of the AND gates 129, 131, and 133. The output terminals 145 and 147 of the second counter 141 are the first and second input terminals of the AND gate 149 and the inverting second input terminal of the AND gate 151, and the AND gate ( 153 is connected to the inverting first input terminal and the inverting second input terminal, the output terminal of the AND gate 149 is connected to the right input terminal of the AND gate 133, and the output terminal of the AND gate 151 is the AND gate 131 ) And the output terminal of the AND gate 153 is connected to the right input terminal of the AND gate 129.

As a result, when the count value of the first counter 141 is -1 and the output terminal 110 of the counter 105 is a logic value 1, the output terminal of the AND gate 127 is a logic value 1. When the count value of the second counter 141 is 0 and the output terminal 121 of the first counter 105 is a logic value 1, the output terminal of the AND gate 129 is a logic value 1. When the count value of the second counter 141 is 1 and the output terminal 123 of the first counter 105 is a logic value 1, the output terminal of the AND gate 131 is a logic value 1, and the second counter 141 is used. AND is 2, and if the output terminal 125 of the first counter 105 is logical 1, then AND

As a result, the output terminal of the OR gate 135 becomes the logic value 1 after the periods τ, 2τ, 4τ, 8τ, and 16τ, respectively, in response to the count value of the second counter 141 after the signal P becomes the logic value 0. Since the input terminal 107 of the flip-flop 109 is already 0 because the signal P is at a logic value of 0, the output terminal 139 of the flip-flop 109 has a signal P having a logic value of 0. The logical value becomes 0 after the periods τ, 2τ, 4τ, 8τ, and 16τ. Therefore, the start of the search operation is delayed over a period depending on the count value of the second counter 141.

When the signal P becomes the logic value 1 again, since the first counter 105 stops through the input terminal 103 and resets to zero through the input terminal 113, the input terminal of the flip-flop 109 ( 137 becomes a logic value 0, and the input terminal 107 becomes a logic value 1. The output terminal 139 becomes the logical value 1 immediately when the signal P becomes the logic value 1, and can be stopped without delaying the search operation at all.

If the signal P stays at a logic value for a period shorter than x? (Where x is determined by the count value of the second counter 141), the output terminal 139 of the flip-flop 109 causes the logic to stay at one. Therefore, the search operation is not started.

As described above, the influence of the electric field strength of the transmitter is considered next according to the influence of the state of the P signal on the count value of the second counter 141 which determines the delay at the start of the search operation.

The second counter 141 has an up coefficient input terminal 157 and a down coefficient input terminal 161. The up coefficient input terminal 157 is connected to an output terminal of the AND gate 159, and an AND gate 159. ) Is connected to the output terminal 140 of the flip-flop 109, the down coefficient input terminal 161 is connected to the output terminal of the AND gate (163). (When the inverting input terminal of the AND gate 159 connected to the output terminal of the AND gate 149 is a logic value of 1, that is, when the second counter 141 reaches the maximum coefficient value (2 in this example), The output terminal of the AND gate 159 cannot be set to 1, so that the count value of the second counter 141 cannot be increased any more, and the second counter 141 reaches the minimum count value (-1 in this example) and this is not possible. When the output terminal 143 of the second counter 141 is set to the logical value 1, the output terminal of the AND gate 163 cannot be set to the logical value 1, and the count value of the second counter 141 is less than or equal to that. Not reduced.

Whether the second counter 141 performs the up coefficient or the down coefficient is determined by the signal coming from the output terminal 165 of the operation switch device 167. The input terminal 169 of the time switch device 167 is used. ) Is connected to the output terminal 139 of the flip-flop 109 through the condenser 171 and to the switch 176 through the condenser 173 and the delay circuit 175. The input terminal 169 of the switch 167 is grounded through the resistor 174. Switch 176 is an on / off switch for the power supply of the receiver. The output terminal 165 of the time switch 167 is directly connected to the left input terminal of the AND gate 159, and is also connected to the left input terminal of the AND gate 163 through the inverter 177.

After the forward edge is generated at the input terminal 169 of the time switch device 167, the elapsed signal a becomes the last logical value 1, and the signal P brings a decrease in the electric field strength over a duration longer than × τ. For a period between 1/2, and 4 minutes, preferably about 2 minutes, the cigar switch device 167 keeps its output terminal 165 at a logic value of 1. The second counter 141 resets. The signal is reset to zero by the signal at the input terminal 179. This signal is passed through the switch 176, which is immediately closed when the receiver is switched on, through the delay circuit 175, and through a differential network having a capacitor 183 and a resistor 185. This occurs when a constant voltage is supplied to the reset input terminal 179 of 141 for a short time.

Within one minute after the time switch device 167 is set in the logic 1 state, the signal at the output terminal 140 of the flip-flop 109 changes from a logic value of 1 to zero. In other words, each time the electric field strength within 2 minutes becomes insufficient over a period longer than Xτ, the count value of the second counter 141 increases by 1, between the moments at which the signals P and a change from logic 1 to 0. The period is increased.

When the flip-flop 109 is not reset within 2 minutes after the flip-flop 109 is set, the output terminal 165 of the time switch device 167 becomes a logic value of 0, and the AND gate 163 for controlling the down coefficient operation is inverted. 177 is activated.

The signal from the inverter 188, which forms a pulse from the positive output pulse of the monostable multivibrator 189, is connected to the AND gate 163 through a differential network comprising a capacitor 186 and a resistor 187. It is supplied to the input terminal of. The monostable multivibrator 189 is activated by the falling edge of the output signal of the time switch device 191. The time switch device 191 receives an output signal of the OR gate 193, and one input terminal of the OR gate 193 has an inverter 177 through a differential network including a capacitor 195 and a resistor 197. Is connected to the output terminal of the OR gate 93, and the other input terminal of the OR gate 93 is connected to the output terminal of the AND gate 199, and the AND gate 199 is connected to the output terminal of the inverter 177. And the other input terminal thereof is coupled to the output terminal of the inverter 188.

The switch device 191 responds to the edges of the outputs of the differential networks 195 and 197 to generate an output of logic value 1. This constant edge portion is generated when the output signal of the inverter 177 becomes +. This edge portion is supplied to the time switch device 191 through the OR gate 193. The output of the time switch device 191 is maintained at a logic value 1 over a period of 1 to 10 minutes, preferably 3 minutes. After that, when the output of the time switch device 191 becomes a logic value 0, the monostable multivibrator 189 started by the time switch device 191 generates a + pulse, and the + impulse is an inverter 199. Is reversed by-pulses, and the forward trailing edge of the e-pulse causes the counter value of the counter 141 to be reduced by one, while the time switch device 191 through the AND gate 199 and the OR gate 193. The switch device 191 supplies a pulse to the down coefficient input terminal 161 of the counter 141 every three minutes as long as the P signal becomes equal to one, so that the time switch device 167 is restarted. Generates an output signal 0, which causes the output signal to remain at logic value 1 via the inverter 177 and associated input terminals of AND gates 163 and 189. As a result, the count value of the counter 141 is reduced to the minimum count value minus one, which causes the AND gate 163 to become impossible to transmit again due to the signal supplied from the output terminal 143 of the counter 141.

In the case of using a delay circuit that depends on the state of electric field strength in a car radio, the search characteristic of the radio itself is advantageous and automatically adapts to the speed of the car. In other words, the reduction in field strength has a duration that is inversely proportional to the speed of the vehicle. In high speed driving of a vehicle, the delay circuit itself adjusts itself to a shorter start delay time in low speed driving.

In the above-described embodiment, only the decrease in the electric field strength causing the search operation, that is, the decrease in the electric field intensity having a duration longer than the adjusted start delay time Xτ affects the start delay time. This start-up delay time increases when the electric field strength decreases two or more times every two minutes, and decreases when the electric field strength does not decrease two or more times every 5, 8 and 11 minutes. Alternatively, considering the duration and frequency of the decrease in field strength in the above-described manner, it may alternatively be advantageously suitable for automotive radios.

Although the above-described circuit for recognizing the state of the electric field strength signal uses the same element as for delaying the start signal, this is not an absolute requirement, and these two operations, namely, the operation of recognizing the electric field strength signal state and The operation for delaying the start signal may be performed in individual circuits as necessary.

Claims (1)

A search tuning circuit for tuning the receiver every time from the current tuning data to the next tuning data from the tuning data group stored in the memory circuit 33 to the start signal (a '+ bc') according to the electric field strength of the received transmission signal. An AND gate 49 and a clock signal generator 51 for starting a search operation under influence, wherein the receiver is generated when the start signal is very weak in the electric field strength of the received transmission signal. A start delay circuit having a time delay that is adjustable to delay the generation of a start signal according to the action of the time delay, and the time delay increases within a fixed time interval after the search operation progresses to the first present time delay abnormal value The time delay causes the predecessor intensity to be attenuated to the pre-determined level of revelation for a period of time beyond the delay, while the pre-set above for the period of time beyond the second existence time delay. And a field strength response control circuit (141-199) configured to be reduced to a value less than or equal to the second present time delay after a second consecutive fixed time interval not decreasing below one level.

Images