KR820001580B1 - Conference call circuit using reversible analog to digital converter - Google Patents

Abstract

At the moment of establishment of communication connections in a telephone system sum signals are formed from individual signals from the various points in communication. The sum signals are transmitted back to the various communicating points. The system has a memory in which, in the case where a connection already exists, the digital signals in an output register are jointly memorised with their retransmission from subscriber units. The memorising time can be adjusted to the processing time of a communication group in a central unit and used for the formation of sum signals.

Description

Linked call circuit using reversible digital-to-analog converter

1 is a schematic block diagram of the present invention.

The present invention relates to a circuit arrangement for converting an analog signal (particularly a PAM signal) into a digital signal (particularly a PCM signal) and a digital signal into an analog signal for a subscriber station in telecommunication equipment.

Transmitters that transmit analog signals include assigned signal output devices that provide digital signals that occur periodically and repeatedly within a pulse frame. The receiving device has an assigned signal receiving device for receiving an analog signal and receiving a digital signal. Analog-to-digital transducers operating according to the iterative principle include a counter, an intermediate register that can be controlled by the counter's counting signal, and a digital-to-analog converter and digital-analog connected to the output side of the intermediate register. And a comparator for comparing the analog signal output by the converter with the analog signal to be converted into a digital signal. The counter controls the output of the counter position with respect to the intermediate register as its output signal, and delivers the digital signal to be converted into an analog signal from the input register of the signal receiving device to the digital-to-analog converter within the specific counter position. It is designed to give. Within another particular counter position, the counter effectively operates the digital-to-analog converter to convert the analog signal into a digital signal.

In addition, the input of the output register of the signal output device is connected to the register of the intermediate register.

Finally, the output of the input register is connected to the setting input of the register stage of the intermediate register according to German Patent No. 2,534,109, which corresponds to US Pat. No. 4,056,820 referred to herein. Thus, the circuit arrangement according to German Patent No. 2,534,109 requires only one analog-digital transducer per subscriber location. This transducer is used twice within each pulse frame or slot of the control impulse that determines the subscriber station. Not only are analog-digital transducers possible with conventional designs, but also to convert analog signals into digital signals and output their digital signals, and to accept and convert digital signals to be converted into analog signals. In terms of circuit design, the device is relatively inexpensive because it only requires an input register and an output register.

If the subscriber stations are a component of the telecommunications equipment in which a conference call can be made between the individual subscribers, the aggregate signal is transmitted to the individual subscribers. These summed signals consist of the individual signals of several associated subscribers, which are assumed to be converted into analog signals at the subscriber station when the subscriber station operates in a digital manner.

These summation signals are formed centrally, or in one of the subscriber stations if the subscriber stations are connected in a looped system.

If the summation is formed centrally but the summation signal consists of all the individual signals of subscribers participating in the linkage call, the circuit cost of the set of linkages used for the summation includes the signal allocation of the receiving subscriber's own. The sum signal, which is not being done, is cheaper than when it is required to be transmitted to individual subscribers.

In a closed circuit system, the incoming summation signal usually includes its own signal allocation.

Such self-signal assignments in the received summation are sometimes confusing, so they are removed according to known methods (German Patent No. 2,445,092), whereby the self-signal assignments are no longer transmitted but also stored and stored in subsequent pulse frames. Or subtract from the sum signal received in the slot.

The object of the present invention is to design a circuit arrangement according to German patent P2,534,109, which can provide the requirements for such deletion while also carrying out this deletion. The components of this circuit are widely used and require little additional components.

This objective was solved ingeniously by providing a circuit arrangement that is a component of telecommunications equipment in which a summation signal is formed from individual signals of all associated subscriber stations and is transmitted to the stations in order to generate a linked call. In the case of a connected call, a storage device is installed in which the digital signal located in the output register is transmitted from the subscriber station and stored at the same time. The storage time of the storage device can be adapted to the processing time of the central linkage set used for summation formation.

The circuitry also has a second input register connected to the output side of the storage device to receive the storage contents after the storage time has elapsed. The input register is restored by the counter to the digital-to-analog converter to cause the first input register to send its contents to the digital-to-analog converter.

The input register also has the function of a subtractor to form a differential signal from the analog signal delivered by the digital-to-analog converter in response to the transfer by the first and second input registers. This subtractor sends an analog signal to a receiver that accepts an analog signal.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The upper part of the figure shows a transmitter for providing an analog signal and the subscriber station Tn with a receiver for receiving an analog signal is schematically illustrated in the lower part. This subscriber station will be a component of the telecommunications equipment in which a summation signal is formed from all signals of all the subscriber stations in order to generate a linked call. These summation signals are transmitted to the subscriber station.

The transmitter of the subscriber station Tn is connected to the capacitor Co via the low pass filter Lp1 and the switch S2. One input of the comparator (analog comparator) Cp is connected to this capacitor.

The counter CE is a 1-n counter as an additional part of the circuit arrangement shown. The counter input e of this counter is connected to the pulse generator CL.

The counter CE supplies the operation signal to the intermediate register ZR, which will not be described in detail here. This register consists of eight registers in the form of a flip-flop, with eight bits given per PCM word. From the input register Reg1, which is a part of the receiving device of the digital signal coming on the line PCMan, the intermediate register is capable of receiving such signals in its intermediate register stage.

The intermediate register can output these digital signals to a digital-to-analog converter (DAC). The output register Reg2 is an additional part of the circuit device shown. This output register is a component of the signal output device (Sab) that can receive digital signals in the form of PCM words from the register stage of the intermediate register (ZR). The outgoing line (PCMab) is connected to the serial output of the output register. The circuit arrangement described is thus highly related to the circuit of German Patent No. 2,534,109, which is hereby incorporated by reference.

There is also a storage device in the circuit arrangement shown, which is a cycling storage device in which the shift registers Sch 1 to Sch 3 are connected in series. The input of the first shift register (sch 1) is connected to the output of the AND element (U1), one input of the AND element (U1) is connected to the outgoing line (PCMab), and the other input is the recovery signal (K). Can be connected, but the recovery signal appears when the connection is an associated connection.

The outputs of shift registers Sch 1-Sch 3 are respectively connected to the other inputs of AND elements U 2 -U 4.

Recovery signals VZ1, VZ2, and VZ3 are connected to the remaining inputs of each AND element. The outputs of AND elements U2-U4 are coupled by OR element Od.

The duration of the shift registers Sch 1 to Sch 3 as the shift pulse T is applied depends on how long the storage time should be.

The number of successively valid ones of the shift registers Sch 1 to Sch 3 is determined by the recovery of the AND elements U 2 and U 4. The storage time adjusted in this way is coincident with the processing time for forming a summation signal from the individual signals of additional linking subscribers in the center, which in this example is 1, 2 or 3, including the processing time of the exchange.

The second input register Reg12 is an additional component of the circuit arrangement shown. The serial input of (Reg12) is connected to the output of the OR element (Od), and its parallel output (not shown) is connected to the register terminal of the intermediate register (ZR) just as in the case of the first input register (Reg1). have.

Finally, the circuit arrangement shown includes a subtraction device Sub in the form of a differential amplifier D.

The non-inverting input of the differential amplifier is connected to the output of the digital-to-analog converter (DAC).

The output of the differential amplifier is connected to the first terminal of the capacitor (C) via the impedance (R1) and the switch (S1).

The other terminal of the capacitor is grounded. The connection between the first terminal of capacitor (C) and the inverting input of the differential amplifier is made via impedance (R2). This input of the differential amplifier D is also connected to the output of the differential amplifier D via impedance R4 and grounded through impedance R3.

The terminal of the opposite side of the differential amplifier output of the impedance R1 is connected to the second input of the comparator Cp, and is connected to the low pass filter Lp2 through the switch S3. This low pass filter is connected to a receiver of the subscriber station Tn which accepts an analog signal.

The operation of the circuit device will now be described in the case of a linked call.

In this case, the recovery signal is continuously connected to the input K of the AND element U1. Assuming three additional subscriber stations in addition to subscriber station Tn participate in a cooperative connection or call, a continuous signal is connected to the recovery input VZ3 of AND element U4, resulting in three shift registers (Sch 1)- (Sch 3) All are valid for the signal provided from the AND element U1. Therefore, the processing time for forming the aggregated signal of the associated subscriber is considered.

The pulse sequence frequency and the counter CE of the timing pulse given by the pulse generator CL are designed so that each counter output signal is generated at a specific period in each counter output during operation. This period coincides with the period in which the digital signal appears on the lines PCMan and PCMab of the telecommunication system. This period may have a duration of 125 μs, for example. This value corresponds to the pulse frame duration of a typical telecommunication switching system in PCM.

Now assume that an analog signal is output from the subscriber station Tn first. The analog signal is converted into a digital signal and output through the signal output device Sab, the output register Reg2 and the outgoing line PCMab.

Assuming that the counter CE has just been in an output position that does not emit a counter output signal from any output, the output signal a1)-(is now generated by the counter signal reaching the input e from the pulse generator CL. In a15), the counter output appears continuously.

When the counter output appears at the output a3, the switch S2 is closed so that the analog signal sent by the transmitter of the subscriber station Tn can reach the capacitor Co via the low pass filter Lp1. The voltage corresponding to the instantaneous amplitude of each analog signal appears on the capacitor Co, thus generating a PAM signal. When the counter output signal appears at output a4, the register stage of the intermediate register is cleared. And switch S2 is opened again. As a subsequent counter output signal appears at counter outputs a5 to a14, the register stage of the intermediate register is directly and continuously affected on the one hand and on the other hand to cancel the effect of the output signal of the comparator Cp. Are affected. Accordingly, the analog output signal supplied to the comparator Cp by the digital analog converter DAC connected to the resistor stage is converted and gradually adjusted to the amplitude of the analog signal stored in the capacitor Co.

This conversion process is a known process, also referred to as a tterative process (see, for example, FIG. 1 of German Patent No. 2,315,986, US Patent No. 3,234,544, and German Patent No. 2,534,109, referred to herein). I will not explain the process anymore. When the last counter output signal appears at the output (a15), the information of the register stage of the intermediate register (ZR) is transferred by the signal output device (Sab) to the output register (Reg2) and transmitted again through the line (PCMab) exiting therefrom. do. Although not shown, this information may for example reach a linkage set installed on a switchboard and form a summation signal with digital signals from other linkage subscribers there.

The digital signal output from the register Reg2 of the subscriber station Tn, on the other hand, enters the storage device via the AND element U1. This storage device is formed of shift registers Sch 1 to Sch 3 for the operation under consideration. The digital signal then passes through these shift registers and reaches the second input register Reg12 of the circuit arrangement shown via the AND element U4 and the OR element Od.

Since the storage time of the shift register consisting of (Sch 1)-(Sch 3) is adjusted to be equal to the processing time of the summation formation by the associated set as mentioned, when transferred to the second input register (Reg12), the register (Reg12) The digital signal at is already summed from the center to the digital sum signal and reaches the first input register Reg1.

When the next counting cycle of the counter CE starts, the register contents of the intermediate register ZR are erased by the counter output signal of the output a1. The digital signal in the second input register Reg12 is transferred to the intermediate register ZR when the output signal appears at the output a2 ', and is thus converted into an analog signal by the digital-to-analog converter DAC. This analog signal reaches the capacitor C with the switch S1 closed as the counter output signal follows the counter output a2 ". In the case of a single call or connection, the counter outputs a2 'and (a2" ) Does not emit any signal.

When a subsequent counter output signal appears at the counter output a2, the switch S1 is opened again and now the digital signal in the first input register Reg1 is transferred to the intermediate register ZR. This digital signal represents a sum signal.

When the counter output signal appears at the counter output a3, the switches S2 and S3 are closed. The individual analog signal connected to the inverting input of the differential amplifier via impedance (R2) and stored in capacitor (C) is subtracted from the analog sum signal that is still output at the output of the digital-to-analog converter (DAC) at that point. Lose.

This summation signal is connected to the non-inverting input of the differential amplifier (D).

The resulting signal reaches the receiver of the subscriber station Tn, which receives the analog signal via the closed switch S3 and the low pass filter Lp2. Thus, as desired, an analog signal containing only the allocations of the remaining three associated subscribers has been delivered to this receiving device.

When the counter output signal appears at the counter output a3 ', the capacitor C is discharged through the switch S4.

Although various partial variations may be proposed by those skilled in the art, it is to be understood that such embodiments are all readily suitably within the scope of the present invention.

Claims (1)

The transmitter has an assigned signal output device (Sab), the receiver has an assigned signal receiver, and the analog-to-digital transducer has a counter device (CE), an intermediate register (ZR), and a digital-to-analog converter (DAC). And an analog comparator (Cp), and the signal receiving device has an input register (Reg1), and the input of the output register (Reg2) of the assigned signal output device is at the register end of the intermediate register, and its output is It is connected to the register stage setting input, the second input register (Reg12) is connected to the outputs of the memory devices (Sch 1) (Sch 2) (Sch 3), and the subtractor (Sub) is connected to the digital-to-analog converter. Linked call circuit using reversible digital-to-analog converter, characterized in that the presence.

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