KR790000819B1 - Keved agc circuit - Google Patents

Abstract

A keyed AGC circuit was composed of a repeating pulse generator(57) having a longer continuous period than the shortest pulses in a synchronous signal, an amplitude response circuit connected to a video signal, a peak detection circuit(40-44) having an equal time constant to the respective peak detection of the synchronous signal, and an output filter circuit connected to a switching circuit to produce the determined voltage of AGC by a variable current.

Description

Automatic gain control circuit optional

1 is a circuit diagram of a television receiver incorporating an automatic gain control circuit constructed in accordance with the present invention.

2 is a representative waveform diagram of a composite video signal.

3A, 3B, and 3C are circuit diagrams that allow for the selection of one of the various aspects of the present invention.

The present invention relates to an automatic gain control circuit (AGC), and more particularly to a selective automatic gain control circuit of a television. The automatic gain control circuit of the present invention is suitable for fabrication using integrated circuit technology.

As used herein, the term integrated circuit refers to a single semiconductor device or chip that is an equivalent circuit composed of active and passive circuit devices coupled together.

Automatic gain control circuits are commonly used in television receivers to derive control voltages for the receiver's radio frequency (RF) and intermediate frequency (IF) amplifier stages. This control voltage acts to change the gain of the amplifier stage inversely in accordance with the sync pulse component level of the detected video signal in order to supply a detected video output signal with a constant peak amplitude. The sync pulse component of the video signal is then used to separate and synchronize the horizontal and vertical oscillators respectively associated with the horizontal and vertical sweep circuits of the receiver.

A conventional method in a television receiver has been to extract the automatic gain adjustment signal by extracting the synchronous pulse component of the peak level during the horizontal (line) retrace period. Although peak detectors are used, they are so sensitive to shock noise that a device is provided to gate the automatic gain control circuit only during relatively short horizontal retrace pulses, so that the impact noise occurring in video signals during the remaining prescan period is automatically corrected. It does not affect the operation of the gain control circuit.

The peak detector includes a capacitor and the AGC potential appears across the capacitor. Some conventional automatic gain adjusting devices require a long time of automatic gain adjusting time to reduce the influence of the pulse width. However, the time taken by the automatic gain control circuit according to the change of the received television signal repulse was undesirably long for such an apparatus.

The automatic gain control circuitry responds quickly to fading, for example due to signal reflections from passing aircraft, and also when the tuned channel changes from a strong incoming signal to a weak incoming signal or vice versa. It is desirable to have a rapid response to changes in the received television signal level. Slow response times result in fading or irregular flutter of the screen, as the aircraft passing over the head causes the level to change at frequencies of hundreds of cycles per second. In order to improve this point, the pulse differentiation circuit was conventionally used so as to have a constant amplitude pulse of a relatively short period which shows the magnitude | size of a synchronous pulse beyond a reference level, for example. This differential technique produces high peak currents for a given response rate that places an unreasonable demand on the automatic gain control capacitors being used. In addition, high peak auto gain control currents create a wave form in the video, which sometimes results in distortion of the synchronization information during the auto gain control switching pulse interval, causing a temporary decrease in gain, sometimes referred to as "glitch". .

Another reason for increasing AGC circuit response is to eliminate vertical attenuation. Vertical attenuation occurs when the AGC loop gains undergo extensive changes during the vertical blanking period. These extensive changes are caused by the differential pulse widths of the vertical and equalizing pulses. Typically, the AGC device filters the video signal due to increased impact noise and thermal noise generation and is reversed for the first 1 to 2 microseconds of each sync pulse. Therefore, the 5 microsecond period horizontal sync pulses have about 3 microseconds to compensate for the charge lost from the AGC filter capacitors during the prescan and return portions of the previous 63 microsecond signal. Equalization pulses (about 2 1/2 microseconds) take only about 1 microsecond of charge time, while relatively long vertical pulses contribute about 15 microseconds of charge time (full horizontal switching time). Thus, the AGC loop gain varies by approximately 15 due to the bipartite pulse width. Because of the instantaneous response of the device, this loop gain change can overshoot the AGC voltage and also cause a voltage decay during the vertical blanking period. This vertical attenuation can lead to incomplete vertical sync information causing deadlocks and vertical jitter.

According to the present invention, a type having synchronous signal components including various pulse durations and a repetitive pulse generator that is coincident with the synchronous pulse in time is supplied to the automatic gain control circuit. Repetitive pulses have a longer duration than pulses of the shortest duration of the sync signal pulses. Also included are synthetic video signal supplies and amplitude sensitive circuitry comprising a synchronous signal pulse. The amplitude sensitive circuitry responds to video signals for maintaining an initial conduction state for the first polarity of the video signals with respect to the threshold level and also for modifying video excitation of the opposite polarity with respect to the threshold level. Answer The peak detector circuit is coupled to the amplitude sensitive circuitry to detect modified video signal excursions, and the peak detector exhibits a certain amount of time suitable for peak detection of respective sync signal pulses of different periods. The switching device is coupled to the repetitive pulse generator and the peak detection circuit, while the repetitive pulses are generated, to supply a variable current determined by the amplitude of the detected signal represented by the peak detection circuit and also to the repetitive pulse generator and the peak detection circuit. Combined. Also included is an output signal circuit arrangement coupled to the switching arrangement for representing the automatic gain adjustment voltage determined by the variable current represented by the switching arrangement.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Referring to FIG. 1, the dotted rectangle 14 represents a single semiconductor integrated circuit chip. A plurality of contact areas or terminals are arranged on the outer surface of the chip 14, through which external coupling can be made in several circuits on the chip. Combined with current technology and design theory, a video signal processing channel is included on chip 14, which includes first and second intermediate frequency amplifiers 17 and 18, third and fourth intermediate frequency amplifiers 26 and 28, and video detectors. 30, a first video amplifier 32 and a second video amplifier 34.

In a television receiver using chip 14, the modulated carrier television signal is received by antenna 8 and coupled to tuner 12. As is known, tuner 12 includes a radio frequency amplifier and a frequency converter to convert the received radio frequency signal into an intermediate frequency signal.

The intermediate frequency signal derived from tuner 12 is coupled to the first intermediate frequency amplifier 17 through terminal 3 of chip 14. The signals from the first intermediate frequency amplifier 17 appear in the tuning filter 20 and are externally coupled to the chip 14 at terminal 6, and the first intermediate frequency amplifier is coupled to the second intermediate frequency amplifier 18. The amplified intermediate frequency scenes are coupled to an acoustic detector (not shown) via terminal 9 and an external second frequency selective filter circuit 22. The signals from the frequency selective filter circuit 22 are coupled to the third and fourth intermediate frequency amplifiers 26 and 28 coupled in series via terminal 11.

The amplified intermediate frequency output of the fourth intermediate frequency amplifier 28 is applied to the detector stage 30 as a bidet. The signal output of detector 30 is amplified in first video amplifier 32 and then coupled to second video amplifier 34. The output of the second video amplifier 34 is coupled to other external amplifiers (not shown) of the chip 14 via terminal 16 for amplification of the video signal prior to being applied to the appropriate control electrodes of the cathode ray tube. The second video amplifier 34 also supplies signals for the synchronous separation circuit of the receiver (not shown) located outside the chip 14.

In FIG. 1, a selective automatic gain adjustment circuit, shown as 38, is included in integrated circuit chip 14. Circuit 38 includes an apparatus for supplying sync signal components of a video signal from the output of second video amplifier 34. For this purpose, resistors 39 and 36 are coupled to a signal amplitude sensitive circuit comprising transistor 40 from amplifier 34. Resistor 41 is coupled between the collector of transistor 40 and a constant voltage (+ A) of, for example, about 6 volts. The emitter of transistor 40 is coupled to a reference potential point or ground through resistor 42 and its base is coupled to resistor 39. Transistor 40 operates to act as an amplifier when the voltage present at its base drops below a threshold level of approximately 1 volt. For all voltages above the threshold level of approximately 1 volt, transistor 40 acts as a switch and remains saturated.

It is coupled in series to a first charging circuit voltage source (+ A) comprising a resistor 41, a diode 43 and a capacitor 44. The time constant of this charging circuit is short in proportion to the widths of the sync pulses (including the horizontal, vertical and equalization pulses). The junction of resistor 41 and diode 43 is directly coupled to the collector of transistor 40. Capacitor 44 and diode 43 constitute a peak detector circuit for detecting the voltage at the collector of transistor 40.

For example, switching devices for supplying flyback voltage pulses derived from a transformer associated with the horizontal deflection circuit of the receiver include a pulse generator 57. A transistor 47 with a base coupled to the pulse generator 57 via a resistor 46 and chip terminal 1 is included in the switching device. Zener diode 45 (eg, 6 1/2 to 7 1/2 volt Zener) is coupled between terminal 1 and ground. The switching device also includes PNP transistors 50 and 51. The emitter of transistor 50 is coupled to the base of transistor 47 and the base of transistor 50 is coupled to the emitter of transistor 51. The base of transistor 51 is coupled to the common terminal of diode 43 and capacitor 44 and the collector of transistor 51 is coupled to a reference conductor or ground. Diode 52 is also included in the switching device and coupled to ground from the collector of transistor 50. The output filter circuitry, including capacitor 53, is coupled to the emitter of transistor 47 through resistor 48 and chip terminal 2. The time constant of the output filter circuit device is long in proportion to the time constants of the peak detection circuits 40, 41, 42, 43 and 44. A discharge device comprising a diode 33 and a resistor 48 is coupled in series between the output filter capacitor 53 and the capacitor 44. The current leakage device including transistor 49 is coupled to the common terminal of resistor 48 and capacitor 53. Transistor 49 includes a collector coupled to the common terminal of capacitor 53 and resistor 48, an emitter coupled to ground, and a base coupled to the common terminal of the collector of diode 52 and transistor 50.

The first shock noise protection circuit, shown as 84, is coupled to the automatic gain control circuit 38. Capacitor 58 is coupled between the common terminal of resistors 36 and 39 and the base of transistor 59.

Resistor 5 is coupled from the ground to the common terminal of capacitor 58 and the base of transistor 59. The collector of transistor 59 is coupled to a positive voltage source (+ B) of 11 volts, for example. The emitter of transistor 59 is coupled to the base of transistor 60 and the collector of transistor 60 is coupled to a power supply (+ B).

The emitter of transistor 60 is coupled to the base of transistor 63 through resistor 62. Capacitor 61 is coupled between the base of transistor 60 and the reference source or ground. The emitter of transistor 63 is coupled to ground and the collector of transistor 63 is coupled via a resistor 64 to the common terminal of diode 43 and capacitor 44 (eg to the base of transistor 51).

The output of the automatic gain control circuit 38 appears at terminal 2 of the integrated circuit chip 14. An automatic gain adjustment transfer device 54 is coupled to terminal 2 and provides an automatic gain adjustment voltage to adjust the gain of the first and second intermediate frequency amplifiers 17 and 18. In addition, the automatic gain control transfer device 54 supplies a voltage to the automatic gain control delay circuit 55, which supplies a delayed automatic gain control signal to the tuner 12 and couples the received signal to the integrated circuit chip 14 at terminal 7. When the predetermined level determined by the variable resistor 56 is reached. The automatic gain adjustment delay circuit 55 is coupled to the tuner 12 through terminal 10 of the integrated circuit 14.

The above-described automatic gain adjustment circuit supplies a charging current to the automatic gain adjustment capacitor 53 to increase the gain adjustment voltage when the gains of the R-F and I-F signal amplification chains are reduced. An automatic gain adjusting circuit embodying the present invention for use in an apparatus in which the automatic gain adjusting capacitor is discharged to reduce the signal gain of the apparatus will be described with reference to FIGS. 3A, 3B, and 3C.

Circuit 38 of FIG. 1 has two general operating modes. The first or synchronous mode of operation occurs when the select pulses appear at terminal 1 in time coincidence with the sync tips of the video information coupled to the base of transistor 40. A control mode of operation or an out-of-lock mode occurs when the select pulses at terminal 1 do not coincide in time with the sync pulses of the video information at the base of transistor 40. Circuit 38 responds differently for each operating mode, and for nonsynchronous and non-locking modes, circuit 38 has a separate response for noise protection.

Referring to FIG. 2, the composite video signal supplied from the second video amplifier 34 and appearing at the base of the transistor 40 is shown as the closest definition to the horizontal line 87.

This device is suitable for color video signals containing burst components. Representative values below suppression levels 85,86 and 87 are present for proper gain conditions in the R-F and I-F signal amplifier chains. Four horizontal sync pulses 90 appearing from the left side of the shown signal green, approximately 5 microseconds wide, above black level 91. The horizontal blanking period 92 is associated with these pulses, respectively. The variable signal occurring between the blanking periods contains information or video signal identity (the time magnitude is conveniently reduced during the video portion to show the remaining width).

At the end of the four horizontal sync pulses, the video signal returns to the black level for vertical retrace. The vertical blanking period 94 begins with six assimilation pulses 93, each of which is 2 1/2 microseconds wide and repeats with a double horizontal ratio. These assimilation pulses need to have accurate time of vertical ghost and continuous field. Serrated vertical sync pulse 95 follows the assimilation pulse. The total duration 99 of the vertical synchronization pulses is three horizontal lines or approximately 190 microseconds each with a vertical synchronization pulse width of approximately 30 microseconds. Each tooth between the vertical sync pulses (orientated or downward in FIG. 2) is about 2 1/2 microseconds during the period. Another moving picture pulse sequence 96 is supplied, which is followed by a horizontal sync pulse 97 of 5 microsecond periods, which continues to appear until the vertical blanking period 94 ends. After the end of the vertical blanking period, the active scan returns and the synthesized signal containing the information or video component and the vertical retrace and sync pulses for each horizontal line continues for another field.

The three sync pulse widths appear in the video signal, which is the so-called 5 microsecond horizontal sync pulse 2 1/2 microsecond equalization pulse and 30 microsecond sawtooth vertical sync pulse. Representative signal voltage values present at the base of transistor 40 include sync pulse tip 85 at a value of a DC voltage of approximately 0.8 Volts above ground potential during normal operation. The white level 86 has a value of about 7 volts higher than the ground potential, and the signal corresponding to the zero carrier wave level 87 is about +8 volts above the ground potential.

Referring back to circuit 38 of FIG. 1, the signal applied to the base of transistor 40 during operation of the synchronous mode can enter three different voltage regions, which represent the total signal gain of the device under three different conditions. . When the sync tips at the base of transistor 40 are at voltages above 1 volt approximately above ground potential, the signal gains of the R-F and I-F devices are considered to be very low. That is, the video suppression excursions appearing at terminal 16 are considered to be below the effective operating range of the synchronous separator and the video amplifier. When the sync tips at the base of transistor 40 are at a suppression between 0.7 volts and 1 volt approximately above ground potential, the video information at terminal 16 is considered to be in normal condition. When the sync tips at the base of transistor 40 are below 0.7 volts above ground, the signal gain of the R-F and I-F devices is considered large.

During the synchronous mode, if the signal gain is too low, the voltage at the base of transistor 40 will be greater than 1 volt and transistor 40 remains saturated. Thus, the collector of transistor 40 is in the ground potential neighborhood. The switching pulse is applied from the pulse generator 58 to the base of the transistor 47 during each horizontal retrace period and operates to supply current through the resistor 46 to the common terminal of the base of the transistor 47 and the emitter of the transistor 50. Since transistor 40 is saturated, virtually no voltage appears across capacitor 44. Since the base of transistor 51 is actually a ground potential, transistors 50 and 51 are biased at high conduction and produce a maximum current (i.e., the emitter current of transistor 50 is substantially equal to the total current supplied through resistor 46). Therefore, transistor 47 is effectively turned off and no charging current is supplied to the automatic gain regulating capacitor 52.

The collector current of transistor 50 is coupled to diode 52, which acts as a current amplifier in combination with transistor 49, which current gain has a gain determined by the relative zeroes of devices 49,52. Where the two devices are geometrically similar, the collector current of transistor 49 is actually equal to the current of diode 52. Diode 33 is reverse biased due to the voltage drop across the base emitter junctions of transistors 50, 51 and 47. Transistor 49 thus operates to discharge capacitor 53. As the voltage across capacitor 53 decreases, the resulting increase in I-F (and R-F) signal gain will compensate for the incomplete signal condition present at terminal 16. Under these conditions, a constant leakage current of approximately 500 microamperes is applied to capacitor 53 by transistor 49 during each synchronization interval. Pulse generator 57 was chosen to provide a constant current of at least 500 microamps.

Therefore, since the constant current to the emitter of transistor 50 is reflected in the emitter of transistor 49, transistor 49 will draw current from capacitor 53 during each switching period regardless of the voltage across capacitor 44. Transistor 49 thus supplies such an outflow current during each switching pulse period, even under the correct RF and IF gain conditions, and the charging current is supplied by transistor 47 as the outflow current that maintains charging of capacitor 53. When the voltage at capacitor 53 leaks to approximately 2V _BE , the device is operating under the maximum signal gain condition, reaching the minimum threshold voltage needed to operate the automatic gain regulating transfer device 54.

If the aggregate signal gain of the device (IF and RF amplifier) is correct, the voltage excursion of the sync tips at the base of transistor 40 will be less than 1 volt and transistor 40 will indicate saturation during the generation of each sync pulse. Transistor 40 then operates as an amplifier until the transistor voltage of transistor 40 approaches a transistor conduction threshold of 1V _BE (approximately 0.7 volts). When transistor 40 is operating as an amplifier, the inverted sync tip display voltage at the collector of transistor 40 is peak detected by diode 43 and capacitor 44. Therefore, the voltage on capacitor 44 represents the voltage excursion at the base of transistor 40 to a threshold level of approximately 1 volt or less. The peak sensed voltage across capacitor 44 is maintained for the complete switching pulse interval since diode 33 is reverse biased during the switching pulse and transistor 51 exhibits a large input impedance as previously described. The bias current of transistor 51 is also coupled to capacitor 44 and is intended to compensate for the leakage current of capacitor 44, thus maintaining approximately constant voltage across the capacitor during the complete switching pulse interval.

The charging time for capacitor 44 is chosen to be small compared to the time interval of the shortest sync pulse (synchronization pulse). In this embodiment of the present invention, the charge time for capacitor 44 is less than 1/2 microsecond. As noted above, under precise automatic gain adjustment conditions, the forward biased transistor 47 supplies a charge current, such as the leakage current generated by transistor 49, to maintain charge of capacitor 53.

At the end of the select pulse period, transistors 47, 50 and 51 are no longer silver. Diode 33 is forward biased and charging of capacitor 44 quickly discharges to capacitor 53 through diode 33 and resistor 48 to reset the peak detection circuit. The discharge time of capacitor 44 is relatively small and has little effect on the R-F and I-F (total) gains.

When the voltage excursion of the registered tips at the base of transistor 40 is less than the conduction threshold of transistor 40, ie the RF and IF gains, the voltage excursion falls below V _BE . Transistor 40 is off and capacitor 44 charges toward the supply (+ A) voltage. When the voltage at the base of transistors 51 and 50 is at their positive maximum potential, transistor 47 supplies its maximum amount of current, approximately 2 milliamps. Capacitor 53 charges towards approximately 5 volts to reduce its maximum voltage, for example the signal gain of the device. Again at the end of the select pulse, a reset occurs when capacitor 44 discharges to capacitor 53 through diode 33 and resistor 48.

The automatic gain adjustment circuit 38 described above is usually referred to as a sample and has characteristics. Capacitor 44 samples the voltage excursion at the base of transistor 40, which falls within a predetermined range and maintains this sample for the duration of the horizontal select pulse. Typically, during the synchronous mode of operation, the sampled voltage when the select pulse appears is the voltage representing the synchronous tip excursion. When no select pulse appears, the sampled voltage does not charge or discharge current from transistors 47 and 49, respectively, because there is no select pulse current. However, a constant current is supplied to capacitor 53 through resistors 41, diodes 43 and 33, and resistor 48 to prevent stripping of the sync pulses.

The duration of the sample period allows for a low peak current in the automatic gain adjustment capacitor 53, which has a ripple or ripple that appears above the video signal when the automatic gain adjustment voltage is fed back to IF amplifiers 17 and 18 in FIG. Reduce the "glitch" effect.

Since the duration of the charge current in transistor 47 is a function of the horizontal select pulse duration, auto gain control charging on capacitor 53 is independent of the pulse width of the input synchronous pulses at the base of transistor 40. Also, since the selection pulse lasts for approximately 15 microseconds, the duration of the automatic gain adjustment is increased by about three times the horizontal sync pulse of the 5 microsecond period. The automatic gain regulation current is increased by about three times to maintain the same automatic gain adjustment gain. The automatic gain regulation current can be reduced by about three times to maintain the same automatic gain adjustment gain, resulting in improved instantaneous response of the device. Therefore, the vertical attenuation is reduced because shorter (2 1/2 microseconds) equalization pulses continue. That is, the automatic gain control charging is not dependent on the width of the pulses, but only on the exclusion of pulses beyond the threshold of transistor 40.

By reducing the vertical attenuation, the speed of the automatic gain adjustment circuit is increased by the proper choice of capacitor 53, allowing the automatic gain adjustment to be adjusted quickly when there is a sudden change in the level of the signal repaired at the antenna. This increased automatic gain adjustment speed reduces the influence of the flutter of the aircraft from passing aircraft and reduces fading when the tuning channel changes from a strong incoming signal to a weak incoming signal or vice versa.

Another advantage of the circuit described while operating in the synchronous mode is that while there is impact noise, the gain does not decrease to a substantial amount because the impact noise above the black level has the same effect as the sync pulse of transistor 40. If such noise occurs during the selection pulse supplied by generator 57, the noise can affect the reduction of RF and IF gain. In terms of efficiency, this is a false gain reduction. To prevent this undesirable operating condition, the noise circuit shown as 84 is coupled to the source of video signals applied to the base of transistor 40. The noise circuit operates to discharge capacitor 44 and prevents the reduction in RF and IF gain that occurs when transistor 40 becomes saturated by noise signals. The operation of noise sensing circuits, such as some of the circuits used herein, is described in US Pat. No. 3,634,620 entitled "Noise Protection Automatic Gain Control Circuit for Controlling the Amplitude of Feedback Pulses." The patented noise protection circuit operates to reduce the amount of feedback current supplied to the automatic gain adjustment circuit when noise occurs, but the noise circuit used here prevents false automatic gain adjustment signals and prevents peak detection at capacitor 44. To prevent the value of the sampled voltage across capacitor 44 operates to decrease. The noise circuit 84 operates as follows. Capacitor 58 connected with resistor 5 differentiates the signals supplied to capacitor 58.

The forward portion of the noise present at the base of transistor 40 will be peak detected by transistor 59 and capacitor 61. The charging time for capacitor 61 is relatively short compared to the charging time constant associated with capacitor 53. The discharge time constant for the capacitor 61 is relatively long compared to the charging time. Thus, transistor 59 supplies a large charge current in the presence of a noise pulse, but the charge current will be a short period during which capacitor 61 maintains the charge supplied by each pulse for a long duration. The peak sensed voltage across capacitor 61 is applied to the base of transistor 60 and turns on transistor 60 to allow current to flow in the base of transistor 63. When transistor 60 is turned on, transistor 63 is saturated and remains saturated for a period of time determined by the discharge time of capacitor 61. When transistor 63 is saturated, capacitor 44 is discharged through resistor 64 and transistor 63, thus eliminating noise at capacitor 44.

When the switching pulse appears, capacitor 44 can charge up to the voltage indicated by the partial voltage between resistor 41 and resistor 64, but does not continue charging. The partial pressure was chosen to make sufficient automatic gain adjustment to ensure automatic gain adjustment "closed", but automatic gain adjustment in the presence of impact noise is not sufficient to cause "set-up". This effectively works to reduce the erroneous auto gain regulation voltage across capacitor 44. Once the impact noise has passed, transistor 60 will remain on for a time determined by the amount of noise already generated due to the long discharge time constant of capacitor 61 (relative to the noise pulse). If transistor 63 is not in saturation, capacitor 44 returns to its normal operating state. Therefore, noise circuit 84 prevents the automatic gain adjustment circuit from responding to shock noise and prevents false automatic gain adjustment voltage at terminal 2. If noise occurs during the period between sampling, i.e. when no select pulse is present, capacitor 44 charges to a partial pressure between resistors 41 and 64. If there is a series of noise pulses, capacitor 44 remains at a partial pressure, so it does not respond to each noise pulse and provides the selected low gain automatic gain adjustment operation during the series of noise pulses.

The slow discharge time of capacitor 61 operates to continuously prevent rapid changes in voltage across capacitor 44, thus maintaining a relatively constant automatic gain control voltage at terminal 2 during switching in the presence of impact noise.

Circuit 38 operates to provide noise protection and automatic gain adjustment voltage during the second mode (ie, when the switching pulse sync pulses are inconsistent in time). In this out-of-lock mode, when the RF and IF gains are too low, the voltage excursion at the base of transistor 40 will be greater than 1 volt at all times (except as large as possible noise pulses). . So when there is a switching pulse, the base of transistor 51 goes to ground potential and a constant leakage current is generated by transistor 49. Therefore, capacitor 53 discharges toward a minimum threshold voltage of approximately 2V _BE, which operates to increase the gain of the IF and RF amplifiers. When the select pulse is gone, transistor 49 no longer generates current and no change in auto gain control voltage occurs.

Although during video, when the video signal excursion at the base of transistor 40 falls below V _BE (ie, too much RF and IF gain), the video signal excursions are detected across capacitor 44 as already described. When the switching pulse is supplied by generator 57, the automatic gain control current is supplied by transistor 47, thereby reducing the total gain of the device. In the absence of a select pulse, capacitor 44 discharges through diode 33, resistor 48 and capacitor 53. This discharge time is very short compared to the discharge time of the capacitor 53. If, between the select pulses, the voltage excursion at the base of transistor 40 is less than V _BE , the charge current is supplied to capacitor 53 through resistors 41, diodes 43 and 33 and 48 to reduce RF and IF gain. do.

Although during crowd mode, the circuit is protected from shock noise pulses. When there is a select pulse, if transistor 40 is out of saturation by noise, noise protection circuit 84 operates to prevent capacitor 44 from charging up to power + A as described above. Capacitor 44 goes down to the voltage determined by resistors 41 and 64, which attempt to make capacitor 53 the same voltage. In the absence of a select pulse, if transistor 40 is turned off by noise, a second charge path comprising resistor 41, diodes 43 and 33, and resistor 48 is coupled to capacitor 53. This charger attempts to supply current to reduce the gain. This second charging path also forms a low-gain, non-selective AGC device to reduce the AGC beat that occurs when the second mode is present. Stripping of the sync pulses during the second state is prevented by the charge current generated when diode 33 is forward biased and transistor 40 is off. The current used for the non-select AGC charging time is small and limited by resistors 41 and 48 in series with diodes 43 and 33. This component of the AGC does not continue because capacitor 44 is rapidly discharged through diode 33 and resistor 48.

The operation of the circuit described above during the loud mode, even in the presence of noise, also prevents the stripping of the sync pulse when a false AGC signal is exhibited by the capacitor 44. Therefore, the circuit described above is protected against noise during synchronous mode and during synchronous and asynchronous mode.

In the above-described circuit embodying the present invention, the transistor 49 serves to discharge the capacitor 53 in a controlled manner. The amount of current drawn depends on the magnitude of the select current supplied through transistor 50 and diode 52 past terminal 1.

Since the response time of the AGC device depends on the 53 charge and discharge times of the AGC capacitors, the AGC circuit of FIG. 1 is designed to increase and decrease the RF and IF gain at a variable rate determined by the relative level of the video signal with respect to the selected reference level. Are arranged. In many conventional AGC devices in which a resistor is coupled across an AGC filter capacitor, it takes a relatively long time to discharge the capacitor. Since there is a current leakage through this resistor during each horizontal period, when the video signal is operating in normal mode, a "tilt" appears in the video signal from white to black across the television screen. Since no outgoing resistor is used in the embodiment of the present invention, the change in AGC voltage during the horizontal period of video information is reduced, while increasing the base speed of the AGC device such that the flute of the aircraft changes.

3A, 3B and 3C are circuit schematic diagrams embodying the present invention for use in AGC devices in which AGC capacitors are discharged when the video signal is too large. A decrease in the AGC voltage results in a decrease in the RF and IF gain.

Referring to FIG. 3A, the bypass video signals generated by the second video amplifier 34 of FIG. 1 are coupled to the base of transistor 68 at terminal 78 through resistor 65. Referring to FIG. Transistor 68 has the function of a threshold sensitive device similar to transistor 40 in FIG. The collector of transistor 68 is coupled to power supply terminal 79 via resistor 66 while its emitter is coupled to reference source (ground) through resistor 71.

Capacitor 67 is coupled between the base of transistor 68 and the collector. Diode 69 is coupled between the collector of transistor 68 and the base of transistor 72. Capacitor 70 is coupled between the base of transistor 72 and ground. Diode 69 and capacitor 70 act as peak detectors in the same manner as diode 43 and capacitor 44 in FIG. The collector of transistor 72 is coupled to the switching pulse generator via terminal 80. Transistor 72 has the same function as transistors 50 and 51 of FIG. The emitter of transistor 72 is coupled to ground through resistor 73 and diode 74. Diode 74 has the same function in this circuit and combines with transistor 75 and acts as a current transformer to discharge capacitor 70 at the end of the switching period. The base of transistor 75 is coupled to the junction between diode 74 and resistor 73. The emitter of transistor 75 is coupled to ground, while the collector of transistor 75 is coupled to output terminal 76 for coupling to an AGC capacitor (not shown).

Transistor 75 is for controlling the voltage across the AGC capacitor and has the same function as transistor 47 in FIG.

The operation of the circuit is as follows. Since thermal and shock noise are higher in frequency than the sync pulse of the video, resistor 65 and capacitor 67 form a low pass filter that limits the AGC device's bandwidth to thermal and shock noise. When the input sync pulse signals at the base of transistor 68 fall below the selected threshold, transistor 68 is saturated and diode 69 and capacitor 70 peak detect the amplitude of the sync signal.

Transistor 72, resistor 73, diode 74 and transistor 75 form the voltages for the current transformer and current amplifier. Since the race current of transistor 72 discharges only capacitor 70, capacitor 70 has a peak detected signal. When a horizontal switching pulse is generated at the collector of transistor 72, this peak detected signal is converted into output current through emitter, resistor 73 and diode 74 of transistor 72. The collector current of transistor 75 is approximately equal to the current flowing from the emitter of transistor 72.

Therefore, the discharge current determined by the peak signal across the capacitor 70 flows from the terminal 76 to the collector of the transistor 75. This discharge current will attempt to reduce the voltage across the AGC capacitor (not shown). The larger the pike detected signal of capacitor 70, the greater the discharge current in the collector of transistor 75, thus operating to reduce the gain of the RF and IF amplifiers.

When the switching pulses are not in the collector of transistor 72, the charge of capacitor 70 is rapidly moved to ground through the forward bias base-emitter junction, resistor 73 and diode 74 of transistor 72. The AGC discharge current then ends. Usually, the circuit described above is coupled to a power source that includes, for example, a resistor divider circuit, so when there is no AGC discharge current, the AGC capacitor will charge up to the partial pressure to increase RF and IF gain.

Since the duration of the discharge current in transistor 75 is a function of the horizontal switching pulse duration, the AGC discharge current is independent of the pulse width of the input synchronous pulses at terminal 78. Therefore, the circuit has the same sample and the characteristics of the circuit of FIG.

The circuit of FIG. 3B is the same as the circuit of FIG. 3A except that capacitor 81 replaces capacitors 67 and 70 of FIG. 3A. Resistors 65, 66, 71, and 73 are replaced with suitable values to provide the appropriate time constant and base current for transistor 72. The operation of 81 of this capacitor which serves this dual function is described with reference to FIG. 3C.

3C is a circuit diagram for implementing the present invention for use in an AGC circuit in which a decreasing AGC voltage reduces gain. Bypass video information is coupled to the base of the level-shafting transistor 100 at terminal 78. The emitter is coupled to positive power supply terminal 79 through a resistor 102. The base of the threshold sensitive transistor 105 is coupled to the emitter of transistor 100 through a resistor 101.

Transistor 105 has the same function as transistor 40 in FIG. Diode 106 and capacitor 107 are coupled between the collector and base of transistor 105 and form a peak detector similar to diode 43 bar capacitor 44 of FIG.

The collector of transistor 108 is coupled to ground and the base is coupled to the collector of transistor 109. The emitter of transistor 109 is coupled to the base of transistor 110. The collector of transistor 110 is coupled to a power supply (+) and the emitter is coupled to ground through resistor 111 and diode 112.

Transistors 108, 109 and 110 operate in the same manner as transistors 50 and 51 in FIG. The base-emitter junction of resistor 111, diode 112 and transistor 118 operates in the same manner as transistor 47 and resistor 48 in FIG. The common terminal between diode 112 and resistor 111 is coupled to the bases of transistors 117 and 118. The emitter of transistor 117 is coupled to ground and the collector of transistor 117 is coupled to an AGC capacitor (not shown) through terminal 76. The collector of transistor 118 is coupled to the collector of transistor 117 through diode 119. Transistor 118 operates in the same manner as transistor 47 in FIG. 1, which supplies a charging current and transistor 118 supplies a discharge current to the AGC capacitor associated with the voltage across their respective peak detection capacitor.

The base of transistor 116 is coupled to the collector of transistor 117 and the collector of transistor 116 is coupled to ground. The emitter of transistor 116 is coupled to zener diode 114 through resistor 115. Zener diode 114 is coupled between zener diode 113 and ground. Zener diode 113 is coupled to terminal 80.

The repeating switching pulse generator is coupled to terminal 80. The base of transistor 120 is coupled to the emitter of transistor 116. The collector of transistor 120 is coupled to the positive power supply and its emitter is coupled to terminal 76 through resistor 121. Zener diode 114, resistor 115, transistor 120 and resistor 121 operate in the same manner as transistor 49 in FIG. 1 to supply AGC charging current when the video is sampled during the switching pulse period.

Transistor 122 and resistor 123 are coupled between terminal 78 and terminal 76. The base of transistor 122 is coupled to terminal 78 and its collector is coupled to ground. Transistor 122 and resistor 123 supply the selected AGC charging current during loud mode, similar to the operation of resistors 41, diodes 43 and 33, and resistor 48 in FIG.

The circuit operation of FIG. 3C is as follows.

The floating video signal is applied to input terminal 78. Transistor 100 is a DC level shifter and couples a video signal to the base of transistor 105 when transistor 100 is turned on. Resistor 101 and capacitor 107 form an input filter that limits the bandwidth of the video signal coupled to terminal 78.

When there is a negative signal with an amplitude less than the selected positive threshold, transistor 105 is biased so that transistor 105 is out of saturation. Diode 106 and capacitor 107 peak detect the collector voltage of transistor 105 when transistor 105 is out of saturation. Therefore, when the gain of the device is too large or approximately accurate, the signal excursions at the base of the transistor 105, causing the transistor 105 to desaturate, charge through the diode 106 up to a voltage at which the capacitor 107 exhibits the least amount (minimum positive) voltage excursion of the signal. Do it.

Usually during the synchronous mode, the smallest positive signals that appear at the base of transistor 105 are horizontal sync pulses, which also coincide in time with the switching pulses supplied at terminal 80. With this switching current, transistor 108 is turned off and the voltage of capacitor 107 determines the base current of transistor 109. The current allowed to flow in transistor 109 minimizes base current leakage in transistor 109 to maintain approximately constant charge in capacitor 107.

When the switching current is lost, capacitor 107 quickly discharges through transistor 108, which is turned on in the absence of a switching pulse. The charge time constant of the capacitor 107 is about 0.5 microseconds. The charging time constant of the capacitor 107 is selected to be smaller than the pulse width of the shortest pulse appearing during the vertical retrace period of the video signal. Transistors 109 and 110 send the peak detected signal of capacitor 107 to resistor 111 and diode 112. Transistor 118 supplies the resulting discharge current to an AGC capacitor (not shown) coupled to the collector of transistor 118 at terminal 76. When transistor 117 saturates, there is a very large RF and IF gain, transistor 105 is turned off, and transistor 116 conducts to turn transistor 120 off. When transistor 118 is conducting, the transistor 117 conducts, allowing a discharge current at terminal 76 to be supplied to the AGC capacitor to reduce the AGC voltage, reducing RF and IF gain.

When the transistor 105 cannot be saturated because there is a switching pulse and there are too few signal excursions at the base of the transistor 105, i.e. when the horizontal sync voltage excursions are too small or sampling occurs during the video portion of the horizontal period, the transistor 120 has a base clamped to the voltage across the zener diode 114.

In this embodiment, the zener diode voltage is chosen to be approximately 5.5 volts. The selected charge current then flows through resistor 121 to terminal 76 to increase the charge on the AGC capacitor and increase the RF and IF gain.

When the video sync pulse voltage excitation has an amplitude that causes transistor 105 to be saturated (ie, accurate RF and IF gain or very much gain), the sync pulse voltage excursion remains peak-detected during the complete horizontal switching period. This effectively extends the width of the sync and equalization pulses to the complete switching pulse period.

Transistors 109 and 110 are the same as the operations of transistors 50 and 51 in FIG. 1, where in transistors 109 and 110 the amount of discharge current supplied by transistor 118 is determined by the peak-dotted voltage applied to the base of transistor 109, while In transistors 50 and 51 of 1 degree, the amount of charge current supplied by transistor 47 is determined by the peak-detected voltage supplied to the base of transistor 51.

When the device of FIG. 3C is in the non-horizontal lock mode, i.e. when the switching pulse is present at terminal 80 and no synchronous pulse is present at terminal 78, transistor 122 and resistor 123 are low-gain simple AGC devices that reduce AGC "bite". This AGC "bite" is generated when a non-horizontal lock mode occurs. When there is a horizontal sync pulse to which transistor 122 is conductive and there are no switching pulses, transistor 122 usually tries to reduce the voltage of the AGC capacitor connected to terminal 76. This offsets the increase in the AGC voltage due to transistor 120 and resistor 121 and is conducting during the switching period in the asynchronous state of transistor 120.

Various modifications may be made within the scope of the present invention. For example, by turning the collector of transistor 50 in FIG. 1 directly to ground, capacitor 53 can be discharged by coupling the resistance across the capacitor instead of the transistor-diode coupling of transistor 49 and diode 52. Other noise protection circuits may also be used in place of the noise protection circuit 84 of FIG. Still other modifications may be made by those skilled in the art.

Claims (1)

As shown in the figure and described above in the text, the synchronization signal component includes pulses of different durations, and the automatic gain adjustment circuit is generally temporally coincident with the synchronization signal pulses and is less than the shortest period of the synchronization signal pulses. In particular, in an automatic gain adjustment circuit responsive to said synchronization signal component of a composite video signal comprising a generator of repetitive pulses having a longer duration and a device for supplying said composite video signal comprising said signal pulses, An amplitude coupled to the video signal and coupled to the video signal to maintain a first conductivity state for video signals that are first polarity with respect to a threshold level and to alter video signal excursions that will be opposite polarity with respect to the threshold level. Induction circuitry, the generator to detect the converted video signal excursions A peak detection circuit coupled to a sensitive circuit and having a time constant suitable for peak detection of each of the synchronization signal pulses of a different period, combining the generator of the repetitive pulses, and also detecting by the peak detection circuit while the repetitive pulses are generated. A switching circuit coupled to the peak detection circuit for supplying a variable current determined by the amplitude of the determined signal, and an output coupled to the switching circuit to produce an automatic gain control voltage determined by the variable current generated by the switching circuit. Selective automatic gain adjustment circuit characterized by filter circuits.

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