KR20240022648A - Systems and methods for testing MEMS arrays and associated ASICs - Google Patents

Abstract

Described herein are methods and systems for testing transducers and associated integrated circuits. In some cases, a method or system described herein includes modulating a bias voltage using a test signal to generate a modulated bias voltage signal useful when testing multiple transducers in a transducer array in parallel. It can be included.

Description

Systems and methods for testing MEMS arrays and associated ASICs

This application relates particularly to medical systems, methods, and systems for medical imaging, such as by ultrasound.

Recently developed and commercialized ultrasonic technologies include MEMS (microelectromechanical systems) ultrasonic transducers, which can have numerous advantages over traditional piezoelectric transducers, such as PZT transducers. Arrays were used. Ultrasound MEMS arrays can include large arrays of ultrasound transducers, such as piezoelectric micromachined ultrasound transducers (pMUTs) and capacitive micromachined ultrasound transducers (cMUTs). there is. These arrays are typically mounted on application specific integrated circuits (ASICs), and in many cases, each ultrasound transducer needs to be tested to ensure that it is functional. Failures that may occur during manufacturing may include, among other things, MEMS devices with broken membranes, shorted, or weak or non-existent connections to the ASIC. Testing of ultrasonic MEMS arrays using existing technologies, for example, is complex and time-consuming because current testing techniques require the transducers to be mechanically (e.g., ultrasonic) stimulated to produce a testable output. Because it is demanded. Doing so can be both technically challenging and expensive in a test environment.

The methods and systems disclosed herein dramatically reduce the cost and complexity for testing ultrasonic MEMS transducer arrays and associated ASICs. In some aspects, a method for testing a transducer array includes applying a test signal to a bias voltage signal to generate a modulated bias voltage signal; providing a modulated bias voltage signal to an ultrasonic transducer array; Measuring the output signal of the ultrasonic transducer array; and determining whether the measured output signal is within a set of expected output limits. In some cases, the output signal is measured from a MEMS transducer or low-noise amplifier (LNA) of an ultrasonic transducer array. In some cases, the method further includes performing measurements and determinations in parallel on each MEMS transducer or LNA of a row of the ultrasonic transducer array. In some cases, the method further includes performing measurements and determinations for each row of the ultrasonic transducer array in sequence. In some cases, the method further includes performing measurements and determinations in parallel for each MEMS transducer or LNA of a column of the ultrasonic transducer array. In some cases, the method further includes sequentially performing measurements and determinations for each row of the ultrasonic transducer array. In some cases, the method further includes determining a total number of errors based on the total number of measured output signals that are determined to be not within the set of expected output limits. In some cases, the method further includes identifying the ultrasonic transducer array as rejected if the total number of errors exceeds an error count limit. In some cases, the set of expected output limits includes an output voltage amplitude within 30% of the expected output voltage amplitude value. In some cases, the set of expected power limits includes a signal frequency within 5% of the expected signal frequency value.

In various aspects, a system for testing a transducer array includes an ultrasonic transducer array comprising a plurality of MEMS transducers; bias voltage signal source; a test voltage signal source connected in series to the bias voltage signal source and the ultrasonic transducer array; Measuring the output signal of the ultrasonic transducer array; and one or more controllers configured to perform the step of determining whether the measured output signal is within a set of expected output limits; It includes a plurality of low noise amplifiers (LNAs) connected in series with an ultrasonic transducer array and one or more controllers. In some cases, the output signal is measured from one or more of a MEMS transducer or LNA of an ultrasonic transducer array. In some cases, the controller is configured to perform measurements and decisions on each MEMS and LNA in a row of the ultrasonic transducer array in parallel. In some cases, the controller is configured to perform measurements and decisions for each row of the ultrasonic transducer array in sequence. In some cases, the controller is configured to perform measurements and decisions in parallel for each MEMS and LNA of the array of ultrasonic transducers. In some cases, the controller is configured to perform measurements and decisions for each row of the ultrasonic transducer array in sequence. In some cases, the controller is also configured to determine the total number of errors based on the total number of measured output signals that are determined to be not within the set of expected output limits. In some cases, the controller is also configured to identify the ultrasonic transducer array as rejected if the total number of errors exceeds the error count limit. In some cases, the set of expected output limits includes an output voltage amplitude within 30% of the expected output voltage amplitude value. In some cases, the set of expected power limits includes a signal frequency within 5% of the expected signal frequency value.

A better understanding of the features and advantages of the subject matter will be obtained by reference to the following detailed description and accompanying drawings, which set forth exemplary embodiments in which the principles of the invention are utilized:
1 shows a schematic diagram of a handheld ultrasound probe, according to embodiments.
2A shows a schematic diagram of a transducer array, according to embodiments.
Figure 2B shows a perspective view of a transducer array, according to embodiments.
Figure 2C shows a schematic diagram of a transducer array, according to embodiments.
3 shows a diagram of a testing circuit, according to embodiments.
4 shows a diagram of a testing circuit, according to embodiments.
Figure 5 shows a block diagram of testing processes, according to embodiments.

Disclosed herein are methods and systems for improved testing of ultrasonic transducer arrays. For example, the methods and systems described herein may include modulating the bias voltage of an ultrasonic transducer imager system or portion thereof using an ultrasonic transducer array and an application-specific integrated circuit (ASIC) of the ultrasonic transducer imager. This includes dramatically reducing the time, cost, and technical difficulty of testing. Modulating the bias voltage of an ultrasonic transducer imager system may be performed using a plurality of ultrasonic imager system transducers (e.g., MEMS elements) and, in some cases, application-specific integrated circuits (ASICs) associated with the transducers. May allow interrogation of connections and configurations. In some cases, modulating the bias voltage may be used to apply a precise mechanical input (e.g., using specialized testing equipment) to each transducer element (e.g., MEMS element) of the array (or tested portion thereof). Allows examination of the connections and configuration of the ultrasonic imager circuitry, while avoiding the need for this. Reductions in the time and complexity of testing ultrasonic imager system components, for example, as described herein, can significantly reduce the cost of production and improve quality control.

devices

In some cases (e.g., as shown in FIG. 1), an ultrasonic imager system may include: a transducer array 101 (e.g., a plurality of transducers) for transmitting and receiving pressure waves; Contains one or more transceiver tiles, each of which may include deducer elements); A coating layer ( 212); a control unit 202, such as an ASIC chip (or ASIC for short), for controlling the transceiver tile(s) 101; For example, Field Programmable Gate Arrays (FPGAs) 214 for controlling components of an ultrasound imager system; Circuit(s) 215, such as an Analogue Front End (AFE), for example, for processing/conditioning signals; For example, an acoustic absorber layer 203 for absorbing waves generated by transducer tiles 210, which may propagate toward circuit 215; a communication unit 208 for communicating data with an external device, e.g., wirelessly or through one or more ports 216; For example, memory 218 for storing data; a battery 206 to provide electrical power to components of the imager; and optionally a display 217 for displaying images of target objects, such as internal organs of a patient.

In some cases, a plurality of transducer elements of an ultrasonic transducer array are arranged in columns and rows (e.g., starting at column 1 and row 1, as shown in FIG. 2A). ) can be spatially arranged within. In some cases, a plurality of transducers of the ultrasonic transducer array portion 250 (e.g., as shown in FIG. 2B) may be arranged on a flat substrate 255 and provided with a cover 260. In some cases, for example, as shown in FIG. 2C, a plurality of transducers of an ultrasonic transducer array portion are arranged on a substrate that is curved (e.g., in cross-section). In some cases, the plurality of transducer elements of an ultrasonic transducer array (e.g., as shown in FIG. 2C) may be divided into a plurality of transducer array portions 250a, 250b, and 250c.

transducer arrays

An ultrasonic imager system (or ultrasonic imager test system 100) may include a transducer array 101, for example, as illustrated in FIG. 3. An ultrasonic transducer array, or portion thereof, may include a plurality of microelectromechanical system (MEMS) transducer elements (eg, arranged in rows and columns on a substrate of the ultrasonic imager system). In some cases, the MEMS transducer element may be a machined ultrasound transducer (MUT). In some cases, the machined ultrasonic transducer (MUT) may be a piezoelectric micromachined ultrasonic transducer (pMUT). In some cases, the micromachined ultrasonic transducer (MUT) may be a capacitive micromachined ultrasonic transducer (cMUT). An ultrasonic imager system (or ultrasonic imager test system 100 ) may include a plurality of application-specific integrated circuit (ASIC) components 102 . In some cases, multiple ASIC components 102 of the ultrasonic imager system or ultrasonic imager test system 100 may be coupled to multiple transducer elements of a transducer array. The ASIC components 102 of the ultrasonic imager test system 100 may include one or more of a low noise amplifier (LNA) (e.g., where the LNA is configured to output from one or more transducers, e.g., of the transducers). used to process signals from the row). In some cases, one or more ASIC components 102 of an ultrasound imager system may be used to control multiple transducer elements of a transducer array. In some cases, one or more ASIC components 102 may be assembled as a unit with a substrate and/or multiple transducer elements. In some cases, one or more ASIC components 102 may be located external to the ultrasound imager device and electrically coupled (eg, via a cable) to a plurality of transducer elements.

Ultrasound imager system 100 may include a bias voltage source 103. The bias voltage is a reference voltage (e.g., a constant 0 V or -18 V input signal) that can be used during testing and operation of the ultrasonic transducer array to normalize the voltage modulation produced by the ultrasonic transducer elements of the ultrasonic transducer array. It can be a static direct current (DC) voltage, which can improve the accuracy and precision of images produced by the array. A bias voltage may be distributed to each element of the ultrasonic transducer array during operation. The distribution of bias voltage to each individual transducer array element (e.g., MEMS element) may vary, for example, due to variations in transducer and/or ASIC configurations associated with the manufacturing process (e.g., given the same input acoustic signal). to) facilitate normalization of the output voltage of each individual transducer array element, which may be slightly different from each other.

As described herein, a bias voltage (e.g., generated by bias voltage source 103) may be modulated, for example, with a test signal (e.g., generated by test signal source 106). Modulation of the bias voltage by the test signal may result in a modulated bias voltage (eg, including superposition of the test signal and bias voltage). In some cases, for example, as shown in FIG. 3, transformer 105 (e.g., a step-down transformer) may be used to adjust the bias voltage of the ultrasonic transducer imager (e.g., -18 V bias). It can be used to adjust (e.g., reduce) the amplitude of a test signal used to modulate a constant bias voltage (e.g., voltage). Transformer 105 may be connected in series with the bias voltage source 103.

In some cases, the test signal source 106 and step-down transformer 105 used in testing may be external to the ultrasonic transducer system or array. In some cases, the test signal source 106 and/or the step-down transformer 105 may be connected between the bias voltage source 103 of the ultrasonic transducer imager and the ultrasonic transducer array 101 (e.g., an array of MEMS elements). An ultrasonic transducer may be coupled to the imager. The transducer elements of the transducer element array 101 include an application-specific integrated circuit (ASIC) 102 (e.g., which may include a plurality of low-noise amplifiers and, in some cases, one or more bypass capacitors). ) can be coupled to the control circuit of the ultrasonic imager. The modulated bias voltage signals may be received after the ASIC circuit and may result from failures or defects in one or more of the ASIC and/or the MEMS transducer array of the ultrasonic imager. Changes to (e.g., amplitude, frequency, and/or waveform shape) may be analyzed.

Modulation of the bias voltage (e.g., with a test signal, as described herein) may be performed (e.g., by measurement system 107) over an unmodulated bias voltage (or an ASIC output signal using an unmodulated bias voltage). may result in a more informative output signal (which must be measured and/or processed). For example, the injected test signal may exhibit changes in amplitude, waveform shape, and/or periodicity that may result, for example, from defects in the hardware of the transducer array of the ultrasonic imager and/or the MEMS transducers of the ASIC. It may have a defined waveform that can be easily evaluated (e.g., using measurement system 107) for changes in periodicity. In some cases, the test signal includes a periodic waveform. For example, the test signal may have a sinusoidal waveform. In some cases, the test signal has a non-zero maximum amplitude. In some cases, the test signal may have a peak-to-peak amplitude (e.g., after a step-down transformer) of 0.1 millivolts to 3 millivolts. In some cases, the test signal is 0.1 millivolt to 0.3 millivolt, 0.1 millivolt to 0.5 millivolt, 0.1 millivolt to 1 millivolt, 0.1 millivolt to 2 millivolt, 0.1 millivolt to 2.5 millivolt, 0.1 millivolt. Volt to 3 millivolt, 0.3 millivolt to 0.5 millivolt, 0.3 millivolt to 1 millivolt, 0.3 millivolt to 2 millivolt, 0.3 millivolt to 2.5 millivolt, 0.3 millivolt to 3 millivolt, 0.5 millivolt to 0.5 millivolt. 1 millivolt, 0.5 millivolt to 2 millivolt, 0.5 millivolt to 2.5 millivolt, 0.5 millivolt to 3 millivolt, 1 millivolt to 2 millivolt, 1 millivolt to 2.5 millivolt, 1 millivolt to 3 millivolt. Volts, 2 millivolts to 2.5 millivolts, 2 millivolts to 3 millivolts, or 2.5 millivolts to 3 millivolts (e.g., after a step down transformer) peak-to-peak amplitude. In some cases, the test signal may be 0.1 millivolts, 0.3 millivolts, 0.5 millivolts, 1 millivolts, 2 millivolts, 2.5 millivolts, or 3 millivolts peak-to-peak (e.g., after a step-down transformer). It may have a peak amplitude. In some cases, the test signal has a peak-to-peak (e.g., after a step-down transformer) of at least 0.1 millivolt, 0.3 millivolt, 0.5 millivolt, 1 millivolt, 2 millivolt, 2.5 millivolt, or 3 millivolt. -Can have peak amplitude. In some cases, the test signal may have a peak-to-peak (e.g., after a step-down transformer) of up to 0.1 millivolt, 0.3 millivolt, 0.5 millivolt, 1 millivolt, 2 millivolt, 2.5 millivolt, or 3 millivolt. -Can have peak amplitude.

In some cases, for example, as shown in FIG. 4, a failure or defect in the ultrasonic transducer array (e.g., MEMS transducer array) or ASIC may cause the bias voltage source 103 (or transformer 105) to ) and transformer array 101 (e.g., at a MEMS bias node or X-node), between transducer array 101 and ASIC 102 (e.g., at an O-node or ASIC LNA input), and/ or by the voltage or shape of the signal measured at a point in the ultrasonic transducer system after the ASIC (e.g., at the ASIC LNA output). Table 1 lists some of the failures that can occur during manufacturing, and the -18 volt (V) constant bias voltage input and 1 millivolt (mV) peak-to-peak alternating current (AC) used to modulate the bias voltage. Assuming a test signal, we illustrate the effects faults can have on a modulated bias voltage signal measured at various points in the circuit. It is noted that the expected signal voltage at the ASIC LNA input under the MEMS transducer element short circuit conditions shown in Table 1 is measured through voltage clamping using protection diodes. Figure 4 shows a diagram of the test circuit with X-node and O-node reference points identified on the circuit.

As shown, the output signal measured after the ASIC's LNAs is measured as a 0 V constant signal for conditions such as a faulty thermal compression bond (TCB) at the O-node or a broken MEMS transducer. It can be. Failure of the circuit before the bias voltage is introduced into the MEMS transducer array can also result in a constant 0 V output signal output after the ASIC LANs; However, such a failure will also result in a constant 0 V output signal at the MEMS bias node (e.g., a decrease or increase in the amplitude of the output periodic signal may indicate a failed ASIC component, such as a failed LNA).

In some cases, the test measurement system 107 of the ultrasonic imager test system 100 may include one or more analog-to-digital converters (ADCs) 201. In some cases, the signal output from each LNA of the ultrasonic imager test system 100 is passed to a different ADC of the test measurement system 107. Controller 202 (eg, including a processor and optionally non-transitory memory) may be coupled to one or more ADCs of test measurement system 107. In some cases, one or more on-board ADCs of the ultrasonic imager system may be used when testing the ultrasonic imager system (e.g., where the ADCs of the ultrasonic imager test system 100 are For example, including on-board ADCs of an ultrasonic imager system, as opposed to using ADCs in a separate test measurement system 107). In some cases, controller 202 is configured to perform a fast Fourier transform (FFT) on data received from one or more LNAs. In some cases, controller 202 includes a multi-channel FFT system. In some cases, test measurement system 107 includes signal analysis unit 203. In some cases, signal analysis unit 203 is configured to perform one or more analyzes on a signal received from one or more LNAs of an ultrasonic imager system (e.g., via an ADC or controller of test measurement system 107). processor (e.g., and non-transitory memory). In some cases, signal analysis unit 203 may perform signal amplitude comparison, waveform shape comparison, and/or pass/fail logic functions (e.g., for one or more signals received from one or more LNAs of an ultrasound imager system). It is configured to carry out these tasks.

In some cases, test measurement system 107 may include test signal source 106. In some cases, test measurement system 107 may include transformer 105. In some cases, test measurement system 107 may include a bias voltage source 103.

In some cases, test measurement system 107, or portions thereof, is located local to the ASIC. In some cases, test measurement system 107 or a portion thereof is located remotely from the ASIC (e.g., where test measurement system 107 or a portion thereof is coupled wirelessly or by a cable to the ASIC). In some cases, all or part of test measurement system 107 (e.g., test signal source 106, transformer 105, one or more ADCs, one or more controllers, and/or one or more signal analysis units) may be removably coupled to the transducer array 101 and/or ASIC 102 of the ultrasonic transducer imager.

4 shows an example of an ultrasonic imager system 100. The signal source may be a low-impedance test signal source 106 (e.g., 50 ohms, 10 V _RMS ) capable of generating a periodic test signal (e.g., a sinusoidal signal). A low-impedance (e.g., 0.35 Ohm) step-down transformer (e.g., to reduce the peak-to-peak voltage of the test signal to +/- 1 mV _RMS ) can be used to reduce the peak-to-peak voltage of the test signal to +/-1 mV RMS. can be placed in series with a bias voltage source (which can be used to supply a voltage bias input). In some cases, a -18 V _DC +/- 1 mV _RMS signal may be measured at the input node of the MEMS transducer array 101 of the ultrasonic transducer imager. In some cases, this MEMS input signal can be measured as a 1 mV _RMS signal at the input node to the ASIC LNAs. In some cases, the signal may be measured as a 30 mV _RMS signal at the ASIC LNA output node.

Methods for testing MEMS arrays and associated ASICs

Figure 5 shows steps in methods for testing a MEMS transducer array and associated ASIC. In some cases, the ASIC and MEMS array may be powered on and configured prior to testing (eg, step 1001). This may include verification of reference system parameters, such as bias voltage parameters, and may involve connection of test signal source, transformer, and/or output signal measurement components. In some cases, a first row (e.g., row 1) of the ultrasonic transducer array may be selected for testing prior to test signal introduction (e.g., step 1002). The first row is not necessarily the top or leftmost row of transducers. In some cases, regardless of its physical location on the array, the first row is simply the first row that is tested. In some cases (e.g., in methods and systems where elements of each row are tested in parallel, rather than elements of each row, as shown in FIG. 5), elements of each column are tested in parallel. The first column, not row 1, is selected.

As shown at step 1003 of Figure 5, a test signal may be applied to the ultrasonic imager system (e.g., using a test circuit such as those shown in Figures 3-5). The test signal may be input as a bias voltage for the MEMS using transformer 105 (e.g., where transformer 105 is placed in series with bias voltage source 103). The test signal (e.g., for modulation of a bias voltage signal) may have a periodic waveform. In some cases, a sinusoidal test signal may be used. When selecting a test signal for use in methods and systems for testing the ultrasonic transducer array 101 and/or ASIC 102, it may be advantageous to use a periodic signal with a frequency that is not excessively high or low. there is. By avoiding test signals with very high frequencies, attenuation of the periodic signal (eg, due to capacitance on the transducer board) can be reduced or avoided. In some cases, insufficient gain from ASIC LNAs can be avoided if test signals with very low frequencies are avoided. In some cases, the test signal is below 5 kHz, 5 kHz to 10 kHz, 10 kHz to 15 kHz, 15 kHz to 20 kHz, 20 kHz to 25 kHz, 25 kHz to 30 kHz, 30 kHz to 35 kHz, 35 kHz. It may have a frequency between 40 kHz, between 40 kHz and 45 kHz, between 45 kHz and 50 kHz, or above 50 kHz. In some cases, a frequency in the range of 20 kHz (eg, 15 kHz to 25 kHz) may be optimal.

In some cases, the test signal is input as a bias voltage signal using a signal transformer 105 (e.g., a step-down signal transformer). In some cases, the use of a signal transformer has the advantage of reducing source impedance, for example, the signal transformer can drive a large capacitive load. This test signal may be capacitively coupled to the input of ASIC 102 by a MEMS capacitance.

As shown in step 1004, the output of the ASIC (e.g., for column 1) may be captured, for example, to detect failures in the MEMS array and/or ASIC. In some cases, for example, as shown in step 1005, the output of the ultrasonic MEMS array and ASIC system stimulated by a modulated bias signal (e.g., as described herein) may be used to test the Can be evaluated for compliance with restrictions. In some cases, a measured signal that is not within expected (or required) power limits (e.g., for amplitude, periodicity, phase, and/or frequency) may result in a failure (e.g., in an ultrasound imager system). can be classified as an error signal. In some cases, a damaged MEMS may have significantly lower capacitance, which may result in lower gain. In some cases, a damaged MEMS element may contain a short circuit that can cause the ASIC output to saturate. Faulty coupling between the ASIC and the MEMS can result in the transducer circuit failing to produce output. In some cases, the error count may be incremented (e.g., by one) and the measurement system may be incremented (e.g., as shown in step 1006) if the measured signal is not within output limits. One may proceed to analyze the output from the next MEMS/ASIC (e.g. located in the next row, e.g. column +1). Instead, if the measured signal is within the output limits, the measurement system does not increment the error count, as shown in step 1007 (e.g., next row, e.g., row +1). You can then proceed to analyze the output from the MEMS/ASIC (located in ). The output from the MEMS/ASIC located in the next column (e.g., column +1) is analyzed for conformity with expected/required output limits (e.g., as shown in step 1008). It can be. Non-compliance with expected/required output limits may result in an increment of the error count (eg, by one), as shown at 1009. If the error count is incremented, or if the output is found to be within limits, to determine whether a previously tested MEMS/ASIC was within the last row of the array or portion thereof (e.g., step 1010) A check may be performed (as shown in ). In some cases, the test system may return to step 1007 and analyze the next MEMS/ASIC in the row if the previously analyzed MEMS/ASIC was not within the last column of the row/array. Steps 1004-1010 may be performed by processing row-by-row instead of column-by-column, as shown in FIG. 5. is considered. In some cases, testing of each MEMS/ASIC element within a column (or row) of an ultrasonic imager system (e.g., steps 1004-1010, as indicated by the dashed box in FIG. 5) may be performed in parallel. It can be performed as: MEMS can be tested in parallel because a modified bias voltage signal can be applied to all MEMS simultaneously.

If the MEMS/ASIC previously analyzed in steps 1008-1010 was located within the last column of the row (or the last row of the row), then the row analyzed was the last row of the array (or the last row of the row was A decision check may be performed (e.g., as shown in step 1011) to determine whether it was the last row of the array. If the row (or column) was not the last in the array, the measurement system determines the MEMS/ASIC in the first column of the next row (e.g., row +1), e.g. You can proceed to analyze the output from the MEMS/ASIC element in the next row (or column) (or, if you proceed down the rows of each column, the next column can be analyzed). The analysis can be performed in parallel, for example.

If the decision check at step 1011 returns a result indicating that the previously analyzed MEMS/ASIC was the last row and column (e.g., row +x, column +x), for example, step 1013 ), a decision check may be made to determine whether the total error count is below an acceptable limit. If the error count is above (or alternatively exceeds) the limit, the device/array may be marked as rejected (or “error”) and testing may be performed (e.g., as shown in step 1015). It may end. If the total error count is below (or alternatively below) the limit, the device/array may be marked as accepted (or “passed”) and the test may be performed (e.g., as shown in step 1014). ) can be terminated. In some cases, an intermediate decision check may be performed at any step between steps 1004 and 1013 to determine whether the total error count has been met or exceeded. In some cases, this intermediate decision check means that if the total error count exceeds (or alternatively meets) the limit, the device/array is marked as rejected (or "error") and the test is terminated. It may result. During this interim decision check, if the error count is found to be less than (or alternatively equal to) the limit, the testing system may be permitted to continue with the testing method 1000.

Although the above steps represent embodiments of the methods of FIG. 5 for testing a MEMS array transducer in accordance with embodiments, those skilled in the art will still recognize many variations based on the teachings described herein. something to do. The steps may be completed in different orders. Steps can be added or deleted. Some of the steps may include sub-steps. Many of the steps can be repeated frequently enough to be advantageous for testing.

One or more of the steps of the method of Figure 5 may be performed using circuitry as described herein, for example, using an ASIC or other processing or logic circuitry as described herein. Circuitry may be programmed to provide one or more of the steps of the method of Figure 5, and the program may include, for example, program instructions stored on a computer-readable memory, or programmed steps in processing or logic circuitry. there is.

Error conditions and ultrasound system failures

A method of testing an ultrasonic transducer array (eg, MEMS array) or portion thereof may include identifying errors during testing. Errors during testing may include voltages, currents, waveforms, or portions of waveforms that deviate from expected values or waveform shapes. In some cases, an error identified, measured, or detected during testing may be the result of a failure in the MEMS array or a portion thereof (e.g., a MEMS element or group of MEMS elements within the array). A method of testing may include identifying a failure in a MEMS array or portion thereof (eg, a MEMS element or group of MEMS elements of the array). In some cases, a lower number of failures in a MEMS array or portion thereof may result in the MEMS array having higher sensitivity, higher accuracy, and/or, e.g., compared to a MEMS array or portion thereof with a larger number of failures. Or it may result in having more reproducible measurements.

In some cases, the error may result from a failure in the MEMS array or part thereof. A failure may result from a fault in the array or one or more connections to, from, or within the array. For example, a failure may result from a damaged MEMS element, short circuit, or faulty coupling between the ASIC component and the MEMS component.

In some cases, identifying an error in a MEMS array or portion thereof (e.g., as a result of a failure) may involve changing the output of the MEMS array or portion thereof (e.g., in response to a test signal applied to the MEMS array or portion thereof). It may include measuring. For example, by comparing the output of the ultrasonic imager system (or ultrasonic imager test system 100) or portion thereof to an expected output voltage value or expected output voltage range, errors (e.g., resulting from system failure) can be detected. may be identified in an ultrasonic imager system or portion thereof (eg, an array of MEMS elements or a group of MEMS elements). In some cases, the method described herein may include determining whether an output signal of an ultrasonic imager system (or ultrasonic imager test system 100) is within a set of output limits. In some cases, the set of output limits includes a range of expected output signal voltage amplitude values. In some cases, the expected output signal voltage amplitude value is 0.1 Volt to 1 Volt, 0.1 Volt to 2 Volt, 0.1 Volt to 3 Volt, 0.1 Volt to 4 Volt, 0.1 Volt to 5 Volt, 0.1 Volt to 7.5 Volt, 0.1 Volt to 7 Volt. 10 Volts to 10 Volts, 0.1 Volts to 15 Volts, 0.1 Volts to 18 Volts, 0.1 Volts to 20 Volts, 1 Volts to 2 Volts, 1 Volts to 3 Volts, 1 Volts to 4 Volts, 1 Volts to 5 Volts, 1 Volts to 1 Volts 7.5 volts, 1 volt to 10 volts, 1 volt to 15 volts, 1 volt to 18 volts, 1 volt to 20 volts, 2 volts to 3 volts, 2 volts to 4 volts, 2 volts to 5 volts, 2 volts to 7.5 volts , 2 volts to 10 volts, 2 volts to 15 volts, 2 volts to 18 volts, 2 volts to 20 volts, 3 volts to 4 volts, 3 volts to 5 volts, 3 volts to 7.5 volts, 3 volts to 10 volts, 3 15 Volts to 15 Volts, 3 Volts to 18 Volts, 3 Volts to 20 Volts, 4 Volts to 5 Volts, 4 Volts to 7.5 Volts, 4 Volts to 10 Volts, 4 Volts to 15 Volts, 4 Volts to 18 Volts, 4 Volts to 4 Volts 20 Volts, 5 Volts to 7.5 Volts, 5 Volts to 10 Volts, 5 Volts to 15 Volts, 5 Volts to 18 Volts, 5 Volts to 20 Volts, 7.5 Volts to 10 Volts, 7.5 Volts to 15 Volts, 7.5 Volts to 18 Volts , 7.5 volts to 20 volts, 10 volts to 15 volts, 10 volts to 18 volts, 10 volts to 20 volts, 15 volts to 18 volts, 15 volts to 20 volts, or 18 volts to 20 volts, or greater than 20 volts. there is. In some cases, the expected output signal voltage amplitude value may be 0.1 volts, 1 volt, 2 volts, 3 volts, 4 volts, 5 volts, 7.5 volts, 10 volts, 15 volts, 18 volts, or 20 volts. In some cases, the set of output limits includes a range of expected output signal frequency values. In some cases, expected output signal frequency values are 0.1 kHz to 1 kHz, 0.1 kHz to 5 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 20 kHz, 0.1 kHz to 25 kHz, 0.1 kHz. to 30 kHz, 0.1 kHz to 35 kHz, 0.1 kHz to 40 kHz, 1 kHz to 5 kHz, 1 kHz to 10 kHz, 1 kHz to 15 kHz, 1 kHz to 20 kHz, 1 kHz to 25 kHz, 1 kHz to 30 kHz, 1 kHz to 35 kHz, 1 kHz to 40 kHz, 5 kHz to 10 kHz, 5 kHz to 15 kHz, 5 kHz to 20 kHz, 5 kHz to 25 kHz, 5 kHz to 30 kHz, 5 kHz to 35 kHz, 5 kHz to 40 kHz, 10 kHz to 15 kHz, 10 kHz to 20 kHz, 10 kHz to 25 kHz, 10 kHz to 30 kHz, 10 kHz to 35 kHz, 10 kHz to 40 kHz, 15 kHz to 20 kHz, 15 kHz to 25 kHz, 15 kHz to 30 kHz, 15 kHz to 35 kHz, 15 kHz to 40 kHz, 20 kHz to 25 kHz, 20 kHz to 30 kHz, 20 kHz to 35 kHz, 20 kHz to 40 kHz, 25 kHz to 30 kHz, 25 kHz to 35 kHz, 25 kHz to 40 kHz, 30 kHz to 35 kHz, 30 kHz to 40 kHz, or 35 kHz to 40 kHz, or greater than 40 kHz. In some cases, the expected output signal frequency value may be 0.1 kHz, 1 kHz, 5 kHz, 10 kHz, 15 kHz, 20 kHz, 25 kHz, 30 kHz, 35 kHz, or 40 kHz.

In some cases, the measured value (e.g., measured output signal voltage amplitude and/or measured output signal frequency) is 0.1% to 1%, 0.1% to 5%, 0.1% to 10% greater than the expected value or range. %, 0.1% to 20%, 0.1% to 25%, 0.1% to 30%, 0.1% to 40%, 0.1% to 50%, 1% to 5%, 1% to 10%, 1% to 20%, 1% to 25%, 1% to 30%, 1% to 40%, 1% to 50%, 5% to 10%, 5% to 20%, 5% to 25%, 5% to 30%, 5% to 40%, 5% to 50%, 10% to 20%, 10% to 25%, 10% to 30%, 10% to 40%, 10% to 50%, 20% to 25%, 20% to 30% %, 20% to 40%, 20% to 50%, 25% to 30%, 25% to 40%, 25% to 50%, 30% to 40%, 30% to 50%, or 40% to 50% , or may be greater than 50%, an error may be determined to exist (or the error count may be incremented by one). In some cases, the measured value (e.g., measured output signal voltage amplitude and/or measured output signal frequency) is 0.1% to 1%, 0.1% to 5%, 0.1% to 10% less than the expected value or range. %, 0.1% to 20%, 0.1% to 25%, 0.1% to 30%, 0.1% to 40%, 0.1% to 50%, 1% to 5%, 1% to 10%, 1% to 20%, 1% to 25%, 1% to 30%, 1% to 40%, 1% to 50%, 5% to 10%, 5% to 20%, 5% to 25%, 5% to 30%, 5% to 40%, 5% to 50%, 10% to 20%, 10% to 25%, 10% to 30%, 10% to 40%, 10% to 50%, 20% to 25%, 20% to 30% %, 20% to 40%, 20% to 50%, 25% to 30%, 25% to 40%, 25% to 50%, 30% to 40%, 30% to 50%, 40% to 50%, or may be greater than 50%, then it may be determined that an error exists (or the error count may be incremented by one).

An assessment of the number of failures detected in a MEMS array or part thereof, for example, by summing the total number of failures in the MEMS array or part thereof, can be used to determine whether the MEMS array can be used or should be rejected. It can be. For example, a MEMS array where the total number of detected failures exceeds a total failure limit or threshold may be identified or marked as rejected, while a MEMS array where the total number of detected failures in the array is below the limit or threshold may be accepted. May be identified or marked as possible (e.g., marked as “passed”).

In some cases, the total failure limit or threshold may be determined based on expected system performance parameters. In some cases, the total failure limit (e.g., pass/fail threshold) may be determined based at least in part on the desired level of sensitivity, accuracy, and/or reproducibility of the measurements. there is. In some cases, the total failure limit (eg, pass/fail threshold) may be based at least in part on the expected number of failures the MEMS array or portion thereof may have before a desired level or performance is lost. In some cases, the total error limit (eg, pass/fail threshold) may be between 0.01 percent and 50 percent of the MEMS element per square millimeter. In some cases, the total error limit (e.g., pass/fail threshold) is 0.01 percent to 0.1 percent, 0.01 percent to 1 percent, 0.01 percent to 2 percent, 0.01 percent to 3 percent, or 0.01 percent to 0.01 percent of MEMS elements per square millimeter. 4 percent, 0.01 percent to 5 percent, 0.01 percent to 7 percent, 0.01 percent to 10 percent, 0.01 percent to 20 percent, 0.01 percent to 25 percent, 0.01 percent to 50 percent, 0.1 percent to 1 percent, 0.1 percent to 2 percent. , 0.1 percent to 3 percent, 0.1 percent to 4 percent, 0.1 percent to 5 percent, 0.1 percent to 7 percent, 0.1 percent to 10 percent, 0.1 percent to 20 percent, 0.1 percent to 25 percent, 0.1 percent to 50 percent, 1 Percent to 2 percent, 1 percent to 3 percent, 1 percent to 4 percent, 1 percent to 5 percent, 1 percent to 7 percent, 1 percent to 10 percent, 1 percent to 20 percent, 1 percent to 25 percent, 1 percent to 1 percent. 50 percent, 2 percent to 3 percent, 2 percent to 4 percent, 2 percent to 5 percent, 2 percent to 7 percent, 2 percent to 10 percent, 2 percent to 20 percent, 2 percent to 25 percent, 2 percent to 50 percent , 3 percent to 4 percent, 3 percent to 5 percent, 3 percent to 7 percent, 3 percent to 10 percent, 3 percent to 20 percent, 3 percent to 25 percent, 3 percent to 50 percent, 4 percent to 5 percent, 4 Percent to 7 percent, 4 percent to 10 percent, 4 percent to 20 percent, 4 percent to 25 percent, 4 percent to 50 percent, 5 percent to 7 percent, 5 percent to 10 percent, 5 percent to 20 percent, 5 percent to 25 percent, 5 percent to 50 percent, 7 percent to 10 percent, 7 percent to 20 percent, 7 percent to 25 percent, 7 percent to 50 percent, 10 percent to 20 percent, 10 percent to 25 percent, 10 percent to 50 percent , 20 percent to 25 percent, 20 percent to 50 percent, or 25 percent to 50 percent. In some cases, the total error limit (e.g., pass/fail threshold) may be 0.01 percent, 0.1 percent, 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, 7 percent, 10 percent, per square millimeter of MEMS element. It could be 20 percent, 25 percent, or 50 percent. In some cases, the total error limit (e.g., pass/error threshold) is at least 0.01 percent, 0.1 percent, 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, 7 percent, 10 percent, 20 percent, 25 percent. , or it could be 50 percent. In some cases, the total error limit (e.g., pass/fail threshold) may be up to 0.01 percent, 0.1 percent, 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, 7 percent, or 10 percent of the MEMS element per square millimeter. , may be 20 percent, 25 percent, or 50 percent.

In some cases, the total error limit (eg, pass/fail threshold) may be based at least in part on the distribution of total failures per MEMS array or portion thereof across a production batch of MEMS arrays. For example, pass/fail decisions can be made based on analysis of MEMS arrays from a production run binned by total number of failures. In some embodiments, the top quintile of tested MEMS arrays (e.g., ranked or binned by the total number of failures per array, failures per MEMS element, or errors per square millimeter of array area) ), top 2 quintiles, top 3 quintiles, top 4 quintiles, top quartile, top 2 quartiles, top 3 quartiles, top third , only the top two tertiles, or top half, are identified or marked as “pass” (e.g., identified or marked as available and/or subsequently incorporated into the final device for sale).

Methods and systems for testing ultrasonic devices and portions thereof (e.g., MEMS arrays or portions thereof, ASICs, etc.) include, for example, probes to sequentially provide mechanical signals to individual transducer elements. The time (and cost) of generating and testing ultrasonic device components (e.g., MEMS arrays, portions of MEMS arrays, ASICs, etc.) compared to current generation and testing methods and systems that may require using can be significantly reduced. Advantageously, the methods and systems described herein utilize a bias voltage (e.g., modulated as described herein) to test device components in parallel, without requiring mechanical modulation of the deformable transducer element. You can use it. In some cases, methods and systems can be used to test multiple elements in parallel. For example, the testing system or method described herein can be used for testing 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10 to 20, 20 to 30, 30 to 40, 40 to 50, 50 It can be configured to test between 100, 100 and 200, 200 and 500, 500 and 1000, or more than 1000 MEMS elements in parallel. In some cases, elements of an ultrasonic transducer array can be tested according to the order of their arrangement on a substrate. For example, all or part of the MEMS elements within a row of an array or a column of an array (e.g., as shown in FIG. 2A) can be tested in parallel. In some cases, a row or column of MEMS elements can be tested within 20 microseconds to 50,000 microseconds. In some cases, a row or column of MEMS elements may have a range of 20 microseconds to 50 microseconds, 20 microseconds to 100 microseconds, 20 microseconds to 150 microseconds, 20 microseconds to 200 microseconds, or 20 microseconds to 500 microseconds. seconds, 20 microseconds to 1,000 microseconds, 20 microseconds to 5,000 microseconds, 20 microseconds to 10,000 microseconds, 20 microseconds to 50,000 microseconds, 50 microseconds to 100 microseconds, 50 microseconds to 150 microseconds, 50 microseconds to 200 microseconds, 50 microseconds to 500 microseconds, 50 microseconds to 1,000 microseconds, 50 microseconds to 5,000 microseconds, 50 microseconds to 10,000 microseconds, 50 microseconds to 50,000 microseconds, 100 microseconds seconds to 150 microseconds, 100 microseconds to 200 microseconds, 100 microseconds to 500 microseconds, 100 microseconds to 1,000 microseconds, 100 microseconds to 5,000 microseconds, 100 microseconds to 10,000 microseconds, 100 microseconds to 100 microseconds 50,000 microseconds, 150 microseconds to 200 microseconds, 150 microseconds to 500 microseconds, 150 microseconds to 1,000 microseconds, 150 microseconds to 5,000 microseconds, 150 microseconds to 10,000 microseconds, 150 microseconds to 50,000 microseconds seconds, 200 microseconds to 500 microseconds, 200 microseconds to 1,000 microseconds, 200 microseconds to 5,000 microseconds, 200 microseconds to 10,000 microseconds, 200 microseconds to 50,000 microseconds, 500 microseconds to 1,000 microseconds, 500 microseconds to 5,000 microseconds, 500 microseconds to 10,000 microseconds, 500 microseconds to 50,000 microseconds, 1,000 microseconds to 5,000 microseconds, 1,000 microseconds to 10,000 microseconds, 1,000 microseconds to 50,000 microseconds, 5,000 microseconds seconds to 10,000 microseconds, 5,000 microseconds to 50,000 microseconds, or 10,000 microseconds to 50,000 microseconds. In some cases, a row or column of MEMS elements may have 20 microseconds, 50 microseconds, 100 microseconds, 150 microseconds, 200 microseconds, 500 microseconds, 1,000 microseconds, 5,000 microseconds, 10,000 microseconds, or 50,000 microseconds. It can be tested within microseconds. In some cases, a row or column of MEMS elements can be at least 20 microseconds, 50 microseconds, 100 microseconds, 150 microseconds, 200 microseconds, 500 microseconds, 1,000 microseconds, 5,000 microseconds, 10,000 microseconds, or It can be tested in 50,000 microseconds. In some cases, a row or column of MEMS elements can have up to 20 microseconds, 50 microseconds, 100 microseconds, 150 microseconds, 200 microseconds, 500 microseconds, 1,000 microseconds, 5,000 microseconds, 10,000 microseconds, or It can be tested in 50,000 microseconds. In some cases, a row or column of MEMS elements can be tested in 0.05 to 0.10 seconds. In some cases, a row or column of MEMS elements can be tested in 0.1 to 100 seconds. In some cases, a row or column of MEMS elements may be configured to perform a 0.1 sec to 0.2 sec, 0.1 sec to 0.5 sec, 0.1 sec to 1 sec, 0.1 sec to 2 sec, 0.1 sec to 3 sec, 0.1 sec to 4 sec, 0.1 sec to 5 seconds, 0.1 seconds to 10 seconds, 0.1 seconds to 100 seconds, 0.2 seconds to 0.5 seconds, 0.2 seconds to 1 second, 0.2 seconds to 2 seconds, 0.2 seconds to 3 seconds, 0.2 seconds to 4 seconds, 0.2 seconds to 5 seconds seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 100 seconds, 0.5 seconds to 1 second, 0.5 seconds to 2 seconds, 0.5 seconds to 3 seconds, 0.5 seconds to 4 seconds, 0.5 seconds to 5 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 100 seconds, 1 second to 2 seconds, 1 second to 3 seconds, 1 second to 4 seconds, 1 second to 5 seconds, 1 second to 10 seconds, 1 second to 100 seconds, 2 seconds to 3 seconds, 2 seconds to 4 seconds, 2 seconds to 5 seconds, 2 seconds to 10 seconds, 2 seconds to 100 seconds, 3 seconds to 4 seconds, 3 seconds to 5 seconds, 3 seconds to 10 seconds, 3 seconds to 100 seconds, 4 seconds to 5 seconds seconds, 4 seconds to 10 seconds, 4 seconds to 100 seconds, 5 seconds to 10 seconds, 5 seconds to 100 seconds, or 10 seconds to 100 seconds. In some cases, a row or column of MEMS elements may be tested in 0.1 seconds, 0.2 seconds, 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 10 seconds, or 100 seconds. In some cases, a row or column of MEMS elements can be tested in at least 0.1 seconds, 0.2 seconds, 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 10 seconds, or 100 seconds. In some cases, a row or column of MEMS elements may be tested in up to 0.1 seconds, 0.2 seconds, 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 10 seconds, or 100 seconds.

In some cases, the rows or columns of the ultrasound array or portion thereof are 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18. , 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 35 to 40, 40 to 50, 50 to 100, 100 to 200 , may have between 200 and 500, or more than 500 MEMS elements.

In some cases, a MEMS ultrasonic array can be tested within 0.01 milliseconds to 50 milliseconds. In some cases, the MEMS ultrasound array has a frequency range of 0.01 millisecond to 0.1 millisecond, 0.01 millisecond to 1 millisecond, 0.01 millisecond to 2 millisecond, 0.01 millisecond to 3 millisecond, 0.01 millisecond to 3.5 millisecond, 0.01 millisecond to 3.5 millisecond. Milliseconds to 4 milliseconds, 0.01 milliseconds to 5 milliseconds, 0.01 milliseconds to 7.5 milliseconds, 0.01 milliseconds to 10 milliseconds, 0.01 milliseconds to 20 milliseconds, 0.01 milliseconds to 50 milliseconds, 0.1 milliseconds to 1 millisecond, 0.1 millisecond to 2 milliseconds, 0.1 millisecond to 3 milliseconds, 0.1 millisecond to 3.5 milliseconds, 0.1 millisecond to 4 milliseconds, 0.1 millisecond to 5 milliseconds, 0.1 milliseconds to 7.5 milliseconds Milliseconds, 0.1 milliseconds to 10 milliseconds, 0.1 milliseconds to 20 milliseconds, 0.1 milliseconds to 50 milliseconds, 1 milliseconds to 2 milliseconds, 1 milliseconds to 3 milliseconds, 1 milliseconds to 3.5 milliseconds , 1 millisecond to 4 milliseconds, 1 millisecond to 5 milliseconds, 1 millisecond to 7.5 milliseconds, 1 millisecond to 10 milliseconds, 1 millisecond to 20 milliseconds, 1 millisecond to 50 milliseconds, 2 Milliseconds to 3 milliseconds, 2 milliseconds to 3.5 milliseconds, 2 milliseconds to 4 milliseconds, 2 milliseconds to 5 milliseconds, 2 milliseconds to 7.5 milliseconds, 2 milliseconds to 10 milliseconds, 2 milliseconds to 20 milliseconds, 2 milliseconds to 50 milliseconds, 3 milliseconds to 3.5 milliseconds, 3 milliseconds to 4 milliseconds, 3 milliseconds to 5 milliseconds, 3 milliseconds to 7.5 milliseconds, 3 milliseconds to 10 milliseconds. milliseconds, 3 milliseconds to 20 milliseconds, 3 milliseconds to 50 milliseconds, 3.5 milliseconds to 4 milliseconds, 3.5 milliseconds to 5 milliseconds, 3.5 milliseconds to 7.5 milliseconds, 3.5 milliseconds to 10 milliseconds , 3.5 milliseconds to 20 milliseconds, 3.5 milliseconds to 50 milliseconds, 4 milliseconds to 5 milliseconds, 4 milliseconds to 7.5 milliseconds, 4 milliseconds to 10 milliseconds, 4 milliseconds to 20 milliseconds, 4 Milliseconds to 50 milliseconds, 5 milliseconds to 7.5 milliseconds, 5 milliseconds to 10 milliseconds, 5 milliseconds to 20 milliseconds, 5 milliseconds to 50 milliseconds, 7.5 milliseconds to 10 milliseconds, 7.5 milliseconds It can be tested within 20 milliseconds, 7.5 milliseconds to 50 milliseconds, 10 milliseconds to 20 milliseconds, 10 milliseconds to 50 milliseconds, or 20 milliseconds to 50 milliseconds. In some cases, the MEMS ultrasonic array has 0.01 millisecond, 0.1 millisecond, 1 millisecond, 2 millisecond, 3 millisecond, 3.5 millisecond, 4 millisecond, 5 millisecond, 7.5 millisecond, 10 millisecond, and 20 millisecond frequencies. It can be tested in milliseconds, or 50 milliseconds. In some cases, the MEMS ultrasonic array has a frequency range of at least 0.01 msec, 0.1 msec, 1 msec, 2 msec, 3 msec, 3.5 msec, 4 msec, 5 msec, 7.5 msec, 10 msec, It can be tested in 20 milliseconds, or 50 milliseconds. In some cases, the MEMS ultrasonic array can operate at frequencies up to 0.01 ms, 0.1 ms, 1 ms, 2 ms, 3 ms, 3.5 ms, 4 ms, 5 ms, 7.5 ms, 10 ms, It can be tested in 20 milliseconds, or 50 milliseconds.

In some cases, the methods and systems for testing MEMS arrays or portions thereof described herein reduce the time required to test an ultrasonic array compared to mechanical testing (e.g., using test ultrasonic waves). For example, at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, 1% to 5%, 5% It can be reduced by 10% to 10%, 10% to 20%, 20% to 30%, 30% to 40%, 40% to 50%, or more than 50%.

Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by a person skilled in the art to which this subject matter belongs.

Although certain embodiments and examples are provided in the foregoing description, the subject matter extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses, and modifications and equivalents thereof. Accordingly, the scope of the claims appended hereto is not limited by any of the specific embodiments described herein. For example, in any method or process disclosed herein, the acts or operations of the method or process may be performed in any suitable order and are not necessarily limited to any particular disclosed order. Although various operations may ultimately be described as multiple individual operations in a manner that may be useful in understanding certain embodiments; However, the order of description should not necessarily be interpreted to imply that these operations are order dependent. Additionally, the structures, systems, and/or devices described herein may be embodied as integrated components or as separate components.

For the purpose of comparing various embodiments, certain aspects and advantages of these embodiments are described. All of these aspects or advantages are not necessarily achieved by any particular embodiment. Thus, for example, various embodiments may achieve or optimize one advantage or group of advantages as taught herein without necessarily achieving other aspects or advantages as may also be taught or suggested herein. It can be done in this way.

As used herein, A and/or B encompasses one or more of A or B, and combinations thereof, such as A and B. The terms “first,” “second,” “third,” and the like may be used herein to describe various elements, components, regions, and/or sections, but these elements, components, It will be understood that regions, and/or sections should not necessarily be limited by these terms. These terms may only be used to distinguish one element, component, area, or section from another element, component, area, or section. Accordingly, in some cases, a first element, component, region, or section discussed herein may be referred to as a second element, component, region, or section, without departing from the teachings of the disclosure. .

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, refer to the features described. , specifies the presence of regions, integers, steps, operations, elements, and/or components, but also includes one or more other features, regions, integers, steps, operations, elements, components, and/or the presence of additional groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Throughout this disclosure, various embodiments are presented in range format. It should be understood that the description in range format is for convenience and brevity only and should not be construed as an inflexible limitation on the scope of any embodiments. Accordingly, unless the context clearly dictates otherwise, a description of a range should be construed as having specifically disclosed all possible subranges, as well as individual numerical values within the range, down to the tenth of the unit of the lower limit. For example, a description of a range such as 1 to 6 includes subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc. , individual values within that range, e.g., 1.1, 2, 2.3, 5, and 5.9, should be considered as specifically disclosed. This applies regardless of the width of the range. The upper and lower limits of these intermediate ranges may independently be included within the smaller ranges, and are also encompassed within the invention subject to any specifically excluded limitation within the recited range. Where a stated range includes one or both of the limitations, ranges excluding either or both of the included limitations are also included within the invention, unless the context clearly dictates otherwise.

As used in this specification and claims, unless otherwise indicated, the terms "about" and "approximately" or "substantially" mean, depending on the embodiment, a numerical value of +/- 0.1, including increments thereof. %, +/- 1 %, +/- 2 %, +/-3 %, +/-4 %, +/-5 %, +/-6 %, +/-7 %, +/-8 %, Refers to fluctuations of less than +/-9 %, +/-10 %, +/-11 %, +/-12 %, +/-14 %, +/-15 %, or +/-20 %. By way of non-limiting example, about 100 meters can be, depending on the embodiment, 95 meters to 105 meters (+/-5% of 100 meters), 90 to 110 meters (+/-10% of 100 meters), or ranges from 85 meters to 115 meters (+/-15% of 100 meters).

While preferred embodiments of the invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and permutations will now occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention, and that methods and structures within the scope of these claims and their equivalents may be covered accordingly.

Claims (20)

As a method for testing a transducer array,
applying a test signal to the bias voltage signal to generate a modulated bias voltage signal;
providing the modulated bias voltage signal to an ultrasonic transducer array;
measuring an output signal of the ultrasonic transducer array; and
A method for testing a transducer array, comprising determining whether the measured output signal is within a set of expected output limits. According to paragraph 1,
A method for testing a transducer array, wherein the output signal is measured from a MEMS transducer or a low-noise amplifier (LNA) of the ultrasonic transducer array. According to paragraph 2,
A method for testing a transducer array, further comprising performing the measurements and determinations in parallel for each MEMS transducer or LNA of a row of the ultrasonic transducer array. According to paragraph 3,
A method for testing a transducer array, further comprising performing the measurements and determinations for each row of the ultrasonic transducer array in sequence. According to paragraph 2,
A method for testing a transducer array, further comprising performing the measurements and determinations in parallel for each MEMS transducer or LNA of a column of the ultrasonic transducer array. According to clause 5,
A method for testing a transducer array, further comprising sequentially performing the measurements and determinations for each row of the ultrasonic transducer array. According to any one of claims 1 to 6,
A method for testing a transducer array, further comprising determining a total number of errors based on the total number of measured output signals that are determined to be not within a set of expected output limits. According to any one of claims 1 to 7,
If the total number of errors exceeds an error count limit, identifying the ultrasonic transducer array as rejected. According to any one of claims 1 to 8,
A method for testing a transducer array, wherein the set of expected output limits includes an output voltage amplitude within 30% of the expected output voltage amplitude value. According to any one of claims 1 to 9,
A method for testing a transducer array, wherein the set of expected output limits includes a signal frequency within 5% of the expected signal frequency value. A system for testing a transducer array, comprising:
An ultrasonic transducer array including a plurality of MEMS transducers;
bias voltage signal source;
a test voltage signal source connected in series to the bias voltage signal source and the ultrasonic transducer array;
measuring an output signal of the ultrasonic transducer array; and
determining whether the measured output signal is within a set of expected output limits.
one or more controllers configured to perform;
A system for testing a transducer array, comprising a plurality of low noise amplifiers (LNAs) connected in series with the ultrasonic transducer array and the one or more controllers. According to clause 11,
A system for testing a transducer array, wherein the output signal is measured from one or more of a MEMS transducer or LNA of the ultrasonic transducer array. According to clause 12,
wherein the controller is configured to perform the measurements and determinations in parallel for each MEMS and LNA of a row of the ultrasonic transducer array. According to clause 13,
The system for testing a transducer array, wherein the controller is configured to sequentially perform the measurements and determinations for each row of the ultrasonic transducer array. According to clause 12,
The system for testing a transducer array, wherein the controller is configured to perform the measurements and determinations in parallel for each MEMS and LNA of the row of ultrasonic transducer arrays. According to clause 15,
The system for testing a transducer array, wherein the controller is configured to sequentially perform the measurements and determinations for each row of the ultrasonic transducer array. According to any one of claims 11 to 16,
The system for testing a transducer array, wherein the controller is further configured to determine a total number of errors based on the total number of measured output signals that are determined to be not within the set of expected output limits. According to any one of claims 11 to 17,
The system for testing a transducer array, wherein the controller is further configured to identify the ultrasonic transducer array as rejected if the total number of errors exceeds an error count limit. According to any one of claims 11 to 18,
A system for testing a transducer array, wherein the set of expected output limits includes an output voltage amplitude within 30% of the expected output voltage amplitude value. According to any one of claims 11 to 19,
A system for testing a transducer array, wherein the set of expected output limits includes a signal frequency within 5% of the expected signal frequency value.