KR20230077606A - Error correction code circuit, memory device including error correction code, and operation method of error correction code - Google Patents

Abstract

A memory device according to the present invention performs error correction code decoding based on a memory cell array configured to store first data and first parity data, and the first data and first parity data to obtain an error corrected data. An ECC circuit configured to output data and a decoding status flag, and an input/output circuit configured to provide error corrected data and a decoding flag to a memory controller. The ECC circuit includes a syndrome generator configured to generate a syndrome based on the first data and the first parity data, a syndrome decoding circuit configured to generate an error vector by decoding the syndrome, and error-corrected data based on the error vector and the first data. and a high-speed decoding status flag (DSF) generator configured to generate a decoding status flag based on the syndrome, without an error vector.

Description

Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit

The present invention relates to a semiconductor memory, and more particularly, to a memory device and an error correction code decoding method of the memory device.

Semiconductor memory consists of volatile memory devices, such as SRAM and DRAM, in which stored data is lost when power supply is cut off, and non-volatile memory devices, such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when power supply is cut off. It is classified as a volatile memory device.

DRAM is widely used as system memory in mobile devices or computer devices. Recently, DRAM devices include an Error Correction Code (ECC) circuit for improving reliability of stored data. The ECC circuit can correct errors in data stored in the DRAM device. If the error of the data exceeds the error correction capability of the ECC circuit, the error cannot be normally corrected. In this case, a means for notifying the decoding result of the ECC circuit to an external device (eg, a memory controller) is required. To this end, the ECC circuit may provide a decoding status flag (DSF) including information on an ECC decoding result to the memory controller.

An object of the present invention is to provide a memory device having improved reliability and improved performance, and a method for decoding an error correction code of the memory device.

According to one embodiment of the present invention, a memory device includes a memory cell array configured to store first data and first parity data; an ECC circuit configured to perform error correction code decoding based on the first data and first parity data, and output error-corrected data and a decoding status flag; and an input/output circuit configured to provide the error-corrected data and the decoding flag to a memory controller, wherein the ECC circuit includes: a syndrome generator configured to generate a syndrome based on the first data and first parity data; a syndrome decoding circuit configured to decode the syndrome to generate an error vector; correction logic circuitry configured to generate the error corrected data based on the error vector and the first data; and a fast decoding status flag (DSF) generator configured to generate the decoding status flag based on the syndrome without the error vector.

According to an embodiment of the present invention, an error correction code (ECC) circuit configured to correct first data based on first data and first parity data stored in a memory device includes: a syndrome generator configured to generate a syndrome based on the first data and the first parity data; syndrome decoding circuitry configured to compare the syndrome with each column of a parity-check matrix to generate an error vector; correction logic circuitry configured to generate the error corrected data based on the error vector and the first data; and a fast decoding status flag (DSF) generator configured to generate a decoding status flag indicating a decoding status for the error corrected data based on the syndrome and a reduced parity-check matrix, wherein the The parity-check matrix includes only partial information of the parity-check matrix.

According to an embodiment of the present invention, an operating method of an error correction code (ECC) circuit configured to correct first data based on first data and first parity data stored in a memory device includes: generating a syndrome based on 1 data and the first parity data; generating an error vector based on the syndrome and the parity-check matrix; generating error-corrected data by performing a logic operation on the error vector and the first data; generating a decoding status flag based on the syndrome and the reduced parity-check matrix; and transmitting the error-corrected data and the decoding status flag to a memory controller, wherein generating the error vector and generating the decoding status flag are performed in parallel.

According to an embodiment of the present invention, a method of configuring an error correction code (ECC) circuit includes: determining a parity-check matrix used for syndrome decoding of the ECC circuit; generating a reduced parity-check matrix based on repetition characteristics of the parity-check matrix; and configuring a high-speed decoding state flag generator of the ECC circuit to perform a logic operation on some information of the syndrome based on information on each column of the reduced parity-check matrix, wherein the reduced parity-check matrix comprises: The check matrix includes only some information of the parity-check matrix.

According to the present invention, an ECC circuit included in a memory device may generate a decoding state flag using only syndrome information. In this case, since the decoding status flag can be generated together with the syndrome decoding operation, the total delay time for ECC decoding can be reduced. Accordingly, a memory device and an error correction code decoding method of the memory device having improved performance and improved reliability are provided.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.
FIG. 2 is a block diagram illustrating the memory device of FIG. 1 .
FIG. 3 is a block diagram for explaining the operation of the ECC circuit of FIG. 2 .
4A is a flowchart showing the operation of the ECC decoder of FIG. 3;
4b is a block diagram showing an ECC decoder configured to perform operations according to the flowchart of FIG. 4a.
Figure 4c is a block diagram showing the DSF generator of Figure 4b.
5A is a flowchart showing the operation of the ECC decoder of FIG. 3;
5B is a block diagram showing an ECC decoder configured to perform operations on the flowchart of FIG. 5A.
Figure 5c is a block diagram showing the fast DSF generator of Figure 5b.
6, 7a, 7b, and 7c are diagrams showing some examples of H-matrices used by the syndrome decoding circuit of FIG. 5a.
8 is a diagram showing some examples of an abbreviated H-matrix generated based on the H-matrices of FIGS. 6 to 7C.
9 is a diagram showing some examples of a syndrome check circuit of the high-speed DSF generator of FIG. 5c.
10 is a diagram showing some examples of a parity error check circuit of the high-speed DSF generator of 5c.
11 is a diagram showing some examples of a high-speed data error check circuit of the high-speed DSF generator of 5c.
12 is a diagram showing some examples of the DST detection circuit of the high-speed DSF generator of 5c.
13 is a block diagram showing some examples of DSF detection circuitry of the high-speed DSF generator of FIG. 5C.
14 is a diagram showing some examples of an abbreviated H-matrix according to an embodiment of the present invention.
FIG. 15 is a diagram showing some examples of a high-speed data error checking circuit using the shortened H-matrix for UE determination of FIG. 14;
16 is a diagram showing some examples of a DSF detection circuit using data error information from the high-speed data error check circuit of FIG. 15;
FIG. 17 is a diagram showing some examples of a DSF detection circuit using data error information from the high-speed data error check circuit of FIG. 15;
18 is a flowchart for explaining a method of generating a reduced H-matrix according to an embodiment of the present invention.
19 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.
20 is a block diagram showing a memory system according to an embodiment of the inventive concept.
21 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.
22 is a diagram showing some examples of a memory package according to an embodiment of the present invention.
23 is a diagram showing some examples of a memory package according to an embodiment of the present invention.
24 is a block diagram exemplarily showing a memory module 6000 to which a memory device according to the present invention is applied.
25 is a diagram illustrating a system 7000 to which a storage device according to an embodiment of the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept. Referring to FIG. 1 , a memory system 10 may include a memory controller 11 and a memory device 100 . In one embodiment, the memory system 10 is an information processing device configured to process various information and store the processed information, such as a personal computer, laptop, server, workstation, smart phone, tablet PC, digital camera, black box, etc. can be one of them.

The memory controller 11 may store data in the memory device 100 or read data stored in the memory device 100 . For example, the memory controller 11 transmits a clock signal CK and a command/address signal CA to the memory device 100, and transmits a data signal DQ and a data strobe signal DQS to the memory device 100. ) can be exchanged. In an embodiment, data DATA is transmitted from the memory controller 11 to the memory device 100 through the data signal DQ and the data strobe signal DQS, or from the memory device 100 to the memory controller ( 11) can be sent. In one embodiment, the memory controller 11 and the memory device 100 may communicate with each other based on a DDR interface or an LPDDR interface, but the scope of the present invention is not limited thereto.

The memory device 100 may operate under the control of the memory controller 11 . In one embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present invention is not limited thereto, and the memory device 100 may include a volatile memory such as SRAM, flash memory, or PRAM. and/or non-volatile memory such as RRAM.

In one embodiment, the memory device 100 may include an error correction code (ECC) circuit 110 . The ECC circuit 110 may be configured to detect and correct errors in data stored in the memory device 100 . For example, the ECC circuit 110 may generate parity data by performing ECC encoding on the first data received from the memory controller 11 . The memory device 100 may store first data received from the memory controller 11 and parity data generated by the ECC circuit 110 together. While the memory device 100 is running, errors may occur in the first data stored in the memory device 100 due to various factors. When a read request for the first data is generated by the memory controller 110, the ECC circuit 110 corrects an error generated in the first data by performing ECC decoding based on the first data and corresponding parity data. can do. The memory device 100 may transmit the corrected first data to the memory controller 11 .

In one embodiment, the ECC circuit 110 may correct errors within a predetermined error correction capability. When the error generated in the data exceeds the error correction capability of the ECC circuit 110, the error generated in the data is not normally corrected.

The memory controller 11 determines whether the read data received from the memory device 100 includes an uncorrectable error or is normal data (eg, data without an error or data with an error normally corrected). need information for To this end, the ECC circuit 110 may transmit a decoding status flag (DSF) to the memory controller 11 . The decoding status flag (DSF) is information indicating whether data transmitted to the memory controller 11 is UE data or normal data. The ECC decoding status flag (DSF) may be generated in the ECC decoding process of the ECC circuit 110 .

In one embodiment, the ECC circuit 110 may generate the decoding status flag (DSF) using only syndromes generated during ECC decoding. In this case, the time required to generate the decoding status flag (DSF) can be shortened. The configuration of the ECC circuit 110 and the method of generating the decoding status flag (DSF) according to the present invention will be described in more detail with reference to the following drawings.

FIG. 2 is a block diagram illustrating the memory device of FIG. 1 . 1 and 2, the memory device 100 includes an ECC circuit 110, a memory cell array 120, a CA buffer 130, an address decoder 140, a command decoder 150, a sense amplifier and a write A driver 160 and an input/output circuit 170 may be included.

The ECC circuit 110 may generate parity data by performing ECC encoding on data to be stored in the memory cell array 120 . Alternatively, the ECC circuit 110 may perform ECC decoding based on the data read from the memory cell array 120 and the parity data to correct data errors. The configuration and operation of the ECC circuit 110 will be described in more detail with reference to the following drawings.

The memory cell array 120 may include a plurality of memory cells. Each of the plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines. In one embodiment, a plurality of word lines may be driven by an X-decoder (or row decoder) (X-DED), and a plurality of bit lines may be driven by a Y-decoder (or column decoder) (Y-DEC). can be driven

The CA buffer 130 may be configured to receive command/address signals CA and temporarily store or buffer the received signals.

The address decoder 140 may decode the address signals ADDR stored in the CA buffer 130 . The address decoder 140 may control the X-decoder and the Y-decoder based on the decoding result.

The command decoder 150 may decode the command CMD stored in the CA buffer 130 . The command decoder 150 may control elements of the memory device 100 based on the decoded result. For example, when the command signal stored in the CA buffer 130 is a write command (ie, when the command received from the memory controller 11 is a write command), the command decoder 150 via the input/output circuit 116 Controls the ECC circuit 110 so that the received data DATA is written into the memory cell array 120 (that is, performs ECC encoding), and controls the operation of the sense amplifier and the write driver 160 (that is, the write driver can be activated).

Alternatively, when the command signal stored in the CA buffer 130 is a read command (ie, when the command received from the memory controller 11 is a read command), the command decoder 150 outputs data stored in the memory cell array 120. The ECC circuit 110 may be controlled (ie, ECC decoding is performed) and the operations of the sense amplifier and the write driver 160 may be controlled (ie, the sense amplifier is activated) so that λ is read.

The sense amplifier and write driver 160 may read data from the memory cell array 120 or write data into the memory cell array 120 through a plurality of bit lines under the control of the command decoder 150 . .

The input/output circuit 170 may receive data DATA from the memory controller 11 or transmit data DATA to the memory controller 11 based on the data signal DQ and the data strobe signal DQS. . In an embodiment, the input/output circuit 170 may receive the decoding status flag DSF from the ECC circuit 110 and transmit the decoding status flag DSF to the memory controller 11 . In one embodiment, the decoding status flag DSF may be transmitted to the memory controller 11 through the data signal DQ. Alternatively, the decoding status flag DSF may be transmitted to the memory controller 11 through various control signals (eg, DBI, DMI, etc.) or other dedicated signals.

FIG. 3 is a block diagram for explaining the operation of the ECC circuit of FIG. 2 . For brevity of the drawings and convenience of explanation, components unnecessary for explaining the operation of the ECC circuit 110 are omitted.

Referring to FIGS. 2 and 3 , the ECC circuit 110 may include an ECC encoder (ECC-ENC) and an ECC decoder (ECC-DEC). The ECC encoder (ECC-ENC) may generate parity data (PRT) by performing ECC encoding on the write data (WDT) to be stored in the memory cell array 120 . For example, with respect to write data (WDT) of 128b, the ECC encoder (ECC-ENC) may generate parity data (PRT) of 8b using a basis bit (BB) of 8b. The write data WDT and the parity data PRT may be stored in the memory cell array 120 through the sense amplifier and the write driver 160 .

The ECC decoder (ECC-DEC) may perform ECC decoding based on the read data RDT and the parity data PRT read from the memory cell array 120 to output error-corrected read data RDT_cor. For example, with respect to the read data RDT of 128b, the ECC decoder (ECC-DEC) may generate error-corrected read data RDT_cor of 128b using the parity data PRT of 8b. The ECC decoder (ECC-DEC) may generate a decoding status flag (DSF) indicating a state of the ECC decoding result or the error corrected read data (RDT_cor).

4A is a flowchart showing the operation of the ECC decoder of FIG. 3; 4b is a block diagram showing an ECC decoder configured to perform operations according to the flowchart of FIG. 4a. Figure 4c is a block diagram showing the DSF generator of Figure 4b.

Hereinafter, in order to concisely and clearly describe embodiments of the present invention, some data values or bit values are described as having a specific level or a specific bit level (eg, “1” or “0”). However, it will be understood that the scope of the present invention is not limited thereto, and various data values or bit values used for the present invention may be variously modified according to implementation methods.

3, 4a, 4b, and 4c, in step S10, the ECC decoder (ECC-DEC) may generate a syndrome (SYD) based on read data (RDT) and parity data (PRT). there is. For example, during a read operation of the memory device 100, the sense amplifier and the write driver 160 read the read data RDT and parity data PRT stored in the memory cell array 120, and write the read data RDT. And the parity data (PRT) may be delivered to the ECC decoder (ECC-DEC). As shown in FIG. 4B , the ECC decoder (ECC-DEC) may include a syndrome generator 111. The syndrome generator 111 may generate a syndrome SYD based on the 128b read data RDT and the 8b parity data PRT. In one embodiment, the syndrome generator 111 generates an 8b check bit based on the 128b read data RDT, and through a logic operation on the 8b check bit and the 8b parity data PRT, the 8b of syndrome (SYD) can be created.

In step S20, the ECC decoder (ECC-DEC) may generate an error vector (ERV) by decoding the syndrome (SYD). For example, as shown in FIG. 4B , the ECC decoder (ECC-DEC) may include a syndrome decoding circuit 112 . The syndrome decoding circuit 112 may receive the syndrome SYD from the syndrome generator 111, decode the received syndrome SYD, and generate an error vector ERV.

In an embodiment, the syndrome decoding circuit 112 compares a parity-check matrix (hereinafter, referred to as an "H-matrix") and the syndrome SYD, in the read data RDT. The location where the error occurred can be detected. The error vector ERV may have a size of 128b (ie, the same size as the read data RDT), and may include information about a position where an error occurs in the read data RDT.

In step S31, the ECC decoder (ECC-DEC) may correct an error of the read data (RDT) using the error vector (ERV). For example, as shown in FIG. 4B , the ECC decoder (ECC-DEC) may include a correction logic circuit 113 . The correction logic circuit 113 performs a bitwise XOR operation on the read data RDT and the error vector ERV read from the sense amplifier and write driver 160, and outputs the error-corrected read data RDT_cor. can do.

In step S32, the ECC decoder (ECC-DEC) may generate a decoding status flag (DSF) based on the error vector (ERV) and syndrome (SYD). For example, as shown in FIG. 4B , the ECC decoder (ECC-DEC) may include a DSF generator 114. The DSF generator 114 may receive the syndrome (SYD) of 8b and the error vector (ERV) of 128b from the syndrome decoding circuit 112 and generate a decoding status flag (DSF) based on the received information.

As a more detailed example, as shown in FIG. 4C, the DSF generator 114 includes a data error check circuit 114a, a syndrome check circuit 114b, a parity error check circuit 114c, and a decoding status flag detection circuit ( 114d).

The data error checking circuit 114a may generate error information err indicating whether an error is included in the read data RDT based on the error vector ERV. In an embodiment, the data error checking circuit 114a may generate error information err by determining whether at least one of each bit of the error vector EVR is “1”. In an embodiment, a value of the error information (err) of "0" indicates that there is no error in the read data (RDT), and a value of the error information (err) of "1" indicates an error in the read data (RDT). can indicate that there is

The syndrome check circuit 114b may generate syndrome information SYD_0 based on whether all bits of the syndrome SYD are “0”. If all bits of the syndrome (SYD) are “0” (that is, if the syndrome (SYD) is all-zero), it indicates that there is no error in the read data (RDT) and parity data (PRT), and the syndrome (SYD) ) may indicate that there is an error in the read data RDT or the parity data PRT. In an embodiment of the present invention, for convenience of explanation, when each bit of the syndrome (SYD) is all “0” (ie, when the syndrome (SYD) is all-zero), the syndrome information (SYD_0) is “1”. ", and when at least one bit of the syndrome SYD is not all "0" (ie, when the syndrome SYD is non-zero), it is assumed that the syndrome information SYD_0 is "0".

The parity error check circuit 114c may output parity error information PRT_ERR based on whether an error is included in the parity data PRT. In an embodiment, the parity error check circuit 114c may generate parity error information PRT_ERR based on an n × n identity matrix and the syndrome SYD. However, n is the same as the size (ie, number of bits) of the syndrome (SYD).

The decoding state flag detection circuit 114d may generate a decoding state flag DSF based on error information err, syndrome information SYD_0, and parity error information PRT_ERR. For example, the decoding status flag (DSF) may indicate a decoding status of an ECC decoding result. The decoding state determines whether the final data output by the ECC decoder (ECC-DEC) (i.e., the error-corrected read data (RDT_cor)) is normal data (i.e., if there is no error in the read data (RDT) or if the read data (RDT ) contains a correctable error), or whether an uncorrectable error is included. Hereinafter, for convenience of description, a decoding result or a decoding state when the read data RDT includes an uncorrectable error is referred to as UE (Uncorrectable Error), and the read data RDT includes a correctable error. A decoding result or decoding state in this case is referred to as CE (Correctable Error), and a decoding result or decoding state in the case where the read data RDT does not include an error is referred to as NE (Non-Error).

As a more detailed example, the error information (err) is “0” (ie, there is no error in the read data (RDT)) and the syndrome information (SYD_0) is “0” (ie, the read data (RDT) or parity data). (PRT has an error), and the parity error information (PRT_ERR) is "0" (ie, there is no error in the parity data (PRT)), the decoding state will be UE. In this case, the decoding status flag (DSF) may be set to "1". In a combination of information different from the case described above, error-corrected read data RDT_cor output from the ECC decoder (ECC-DEC) may be normal data (ie, no error or error normally corrected). there is. In this case (ie, NE or CE), the decoding status flag (DSF) may be set to "0".

Again, as shown in FIG. 4A , in step S40, the ECC decoder (ECC-DEC) may output error-corrected read data (RDT_cor) and a decoding status flag (DSF). In an embodiment, the error-corrected read data RDT_cor and the decoding status flag DSF may be provided to the memory controller 11 through the input/output circuit 170 (see FIG. 2). In one embodiment, the memory controller 11 may determine the decoding state of the received data based on the decoding state flag DSF, and may perform various operations according to the determination result. For example, the memory controller 11 may perform read retry or reset or other various maintenance operations for the UE.

In one embodiment, the operation of the ECC decoder (ECC-DEC) described with reference to FIGS. 4A to 4C may be implemented through various logic operation circuits. For example, the operation of step S10 (ie, syndrome generation operation) is performed through a 6-stage XOR operation circuit, and the operation of step S20 (ie, syndrome decoding operation) is performed through a 3-stage AND operation circuit, The operation of step S31 (ie, error correction operation) is performed through a first-stage XOR calculation circuit. In the operation of step S32 (that is, the operation of generating the decoding status flag DSF), the data error check circuit 114a is implemented through a 7-stage XOR operation circuit, and the syndrome check circuit 114b is implemented using a 4-stage AND. The parity error check circuit 114c is implemented through a 3-stage AND operation circuit and a 3-stage OR operation circuit, and the decoding status flag detection circuit 114d is a 1-stage OR operation circuit, 1 It can be implemented through a stage INV (invert) calculation circuit and a first stage AND calculation circuit.

Since the operation of step S32 uses an error vector (ERV), it is performed after the operation of step S20 is completed. In this case, from the point at which the syndrome decoding operation is completed, the latency required for the operation of step S32 to be completed corresponds to a total of 7-stage OR calculation circuits, 1-stage INV calculation circuit, and 1-stage AND calculation circuit. It may be a delay time to

The operation of step S32 is performed in parallel with the operation of step S31. In this case, since the delay time for the operation of step S32 is relatively longer than the delay time for the operation of step S31, performance degradation occurs according to the operation of step S32 (that is, the operation of generating the decoding status flag).

5A is a flowchart showing the operation of the ECC decoder of FIG. 3; 5B is a block diagram showing an ECC decoder configured to perform operations on the flowchart of FIG. 5A. Figure 5c is a block diagram showing the fast DSF generator of Figure 5b. Hereinafter, for convenience of description, detailed descriptions of the components described above are omitted.

3, 5a, 5b, and 5c, in step S110, the ECC decoder (ECC-DEC-1) generates a syndrome (SYD) based on read data (RDT) and parity data (PRT). can do. For example, as shown in FIG. 5B , the ECC decoder (ECC-DEC) may include a syndrome generator 111. The operation of step S110 of FIG. 5A may be similar to that of step S10 of FIG. 4A, and the syndrome generator 111 of FIG. 5B may perform an operation similar to that of the syndrome generator 111 of FIG. 4B.

In step S120, the ECC decoder (ECC-DEC-1) may generate an error vector (ERV) by decoding the syndrome (SYD). For example, as shown in FIG. 5B , the ECC decoder (ECC-DEC-1) may include a syndrome decoding circuit 112. The operation of step S120 of FIG. 5A may be similar to that of step S20 of FIG. 4A, and the syndrome decoding circuit 112 of FIG. 5B may perform an operation similar to that of the syndrome decoding circuit 112 of FIG. 4B.

In step S130, the ECC decoder (ECC-DEC-1) may correct an error of the read data (RDT) based on the error vector (ERV). For example, as shown in FIG. 5B , the ECC decoder (ECC-DEC-1) may include a correction logic circuit 113. The operation of step S130 of FIG. 5A may be similar to that of step S31 of FIG. 4A, and the correction logic circuit 113 of FIG. 5B may perform an operation similar to that of the correction logic circuit 113 of FIG. 4B.

In step S140, the ECC decoder (ECC-DEC-1) may generate a decoding status flag (DSF) based on the syndrome and a simplified H-matrix.

In step S150, the ECC decoder (ECC-DEC-1) may output error-corrected read data (RDT_cor) and a decoding status flag (DSF). The operation of step S150 of FIG. 5A may be similar to the operation of step S40 of FIG. 4A.

In one embodiment, according to the embodiments of FIGS. 5A to 5C , the fast DSF generator 150 may generate the decoding status flag (DSF) using only the syndrome (SYD) without an error vector (ERV). That is, since the fast DSF generator 150 does not use the error vector (ERV) to generate the decoding status flag (DSF), it can operate in parallel or together with the syndrome decoding operation (eg, the operation of step S120). can

For example, as shown in FIG. 5B , the ECC decoder (ECC-DEC-1) may include a fast DSF generator 116. The fast DSF generator 116 may receive the syndrome SYD from the syndrome decoding circuit 112 and generate a decoding status flag DSF based on the received syndrome SYD. As a more detailed example, as shown in FIG. 5C, the high-speed DSF generator 115 includes a syndrome check circuit 115b, a parity error check circuit 115c, a DSF detection circuit 115d, and a high-speed data error check circuit ( 115e). The syndrome check circuit 115b, parity error check circuit 115c, and DSF detection circuit 115d of FIG. 5C are identical to the syndrome check circuit 114b, parity error check circuit 114c, and DSF detection circuit 114d of FIG. 4C. Similar actions can be performed.

In one embodiment, the DSF generator 114 of FIG. 4C uses an error vector (ERV) to generate error information (err) for read data (RDT). On the other hand, the high-speed data error check circuit 115e of FIG. 5C may generate error information DT_ERR for the read data RDT using the syndrome SYD. As a more detailed example, the high-speed data error check circuit 115e may generate error information DT_ERR for the read data RDT by comparing at least some bits of the syndrome SYD with the reduced H-matrix. . The reduced H-matrix may be generated based on the H-matrix used by the syndrome decoding circuit 112 or partial information of the H-matrix. The configuration of the abbreviated H-matrix will be described in more detail with reference to FIGS. 6 to 8 below.

As described above, the fast DSF generator 115 according to an embodiment of the present invention may generate the decoding status flag (DSF) using only the syndrome (SYD) without an error vector (ERV). Accordingly, since the operation of generating the decoding state flag DSF is performed in parallel with the operation of decoding the syndrome, the overall delay time of the ECC decoder ECC-DEC-1 can be reduced.

For example, as described with reference to FIGS. 4A to 4C , the delay time required to generate the decoding status flag (DSF) from the point at which the syndrome decoding operation is completed is a total of 7 stages of OR operation circuits, 1 stage of INV It is the delay time corresponding to the arithmetic circuit and the 1st-stage AND arithmetic circuit.

On the other hand, as described with reference to FIGS. 5A to 5C, the delay time required to generate the decoding status flag (DSF) from the time when the syndrome decoding operation is completed by the high-speed DSF generator 115 is a total of four stages. is the delay time corresponding to the OR operation circuit of , the INV operation circuit of the first stage, and the AND operation circuit of the first stage. That is, since the decoding status flag (DSF) is generated using only the syndrome (SYD) without the error vector (ERV), the overall delay time of the ECC decoder (ECC-DEC-1) can be reduced.

6, 7a, 7b, and 7c are diagrams showing some examples of H-matrices used by the syndrome decoding circuit of FIG. 5a. 8 is a diagram showing some examples of an abbreviated H-matrix generated based on the H-matrices of FIGS. 6 to 7C. In one embodiment, the reduced H-matrices (sim-H-mat) may be used by the fast DSF generator 115e.

In one embodiment, the H-matrices described with reference to FIGS. 6 to 8 are some examples of H-matrices for single bit error correction (SEC). However, it is understood that the scope of the present invention is not limited thereto, and that the H-matrix and the abbreviated H-matrix according to the present invention can be variously modified according to the implementation method of the memory device 100 or the ECC circuit 110. It will be.

First, referring to FIGS. 6 to 7C , an H-matrix (H-mat) may include a plurality of submatrices SM00 to SM15 and a parity matrix PR. The parity matrix PR may be an identity matrix (IM) having a size of 8 × 8. For example, as shown in FIG. 7A , the parity matrix PR may have an identity matrix (IM) having a size of 8×8. Each row of the parity matrix PR may correspond to each bit (eg, S0, S1, S2, S3, S4, S5, S6, and S7) of the syndrome SYD.

Each of the plurality of partial matrices SM00 to SM15 may have a size of 8 × 8. In an embodiment, the plurality of partial matrices SM00 to SM15 may be arranged according to a certain rule. For example, three rows of each of the plurality of submatrices SM00 to SM15 may be the A0th submatrix A0. That is, three rows of each of the plurality of partial matrices SM00 to SM15 may have the same repetition pattern. The remaining five rows of the plurality of submatrices SM00 to SM15 may be the B00th to B15th submatrices B00 to B15, respectively. Each of the B00th to 15th partial matrices B00 to B15 may have the same column.

As a more detailed example, as shown in FIG. 7B, each row of the H-matrix (H-mat) is each bit of the syndrome (SYD) (eg, S0, S1, S2, S3, S4, S5 , S6, S7) may correspond. In the 1st sub-rows (eg, rows corresponding to S0, S1, and S2) of the 00th sub-matrix SM00 of the H-matrice (H-mat), the A0 sub-matrix ( A0) may be disposed, and in 1st sub-rows (eg, rows corresponding to S0, S1, and S2) of the 01st sub-matrix SM01, the A0 sub-matrix A0 ) can be placed. Similarly, the A0 sub-matrix A0 may be disposed in the first sub-rows (eg, rows corresponding to S0, S1, and S2) of the fifteenth sub-matrix SM15. . In the second sub-rows (2nd sub-Rows) (eg, rows corresponding to S3, S4, S5, S6, and S7) of the 00th sub-matrix SM00 of the H-mat, A B00 sub-matrix B00 may be disposed, and 2nd sub-rows (eg, rows corresponding to S3, S4, S5, S6, and S7) of the 01-th sub-matrix SM01 , the B01th sub-matrix B01 may be disposed. Similarly, in the second sub-rows (2nd sub-Rows) (eg, rows corresponding to S3, S4, S5, S6, and S7) of the fifteenth sub-matrix SM15, the B15 sub-matrix B15 is can be placed.

That is, in the first sub-rows (eg, rows corresponding to S0, S1, and S3) of the H-matrix (H-mat), sub-matrix units (ie, 8 column units) Has a pattern in which the same matrix is repeatedly arranged as , and the second sub-rows (2nd sub-Rows) (eg, S3, S4, S5, S6, and S7 corresponding rows ) may have a pattern in which different submatrices are arranged in units of submatrices (ie, units of 8 columns). At this time, in the same sub-matrix of the second sub-rows (eg, rows corresponding to S3, S4, S5, S6, and S7) of the H-matrice, each column may be identical to each other.

Combining the parity matrix PR and the partial matrices SM00 to SM15 described with reference to FIGS. 7A and 7B, the H-matrices can be implemented as shown in FIG. 7C. The syndrome decoding circuit 112 may generate an error vector ERV of 128b by comparing each bit of the syndrome SYN with each column of the H-matrices of FIG. 7C. For example, the syndrome decoding circuit 112 may search for the same column as the syndrome SYD among a plurality of columns of the H-matrix (H-mat), and generate an error vector (ERV) based on the search result. . A bit at a position corresponding to the same column as the syndrome SYD among a plurality of columns of the H-matrix H-mat may indicate an error occurring in the read data RDT.

In one embodiment, all the bits of the syndrome SYN are not “0” (ie, non-zero), but there is no column identical to the syndrome SYD among the plurality of columns of the H-matrix H-mat, It may indicate that the read data RDT includes an error that cannot be corrected.

In one embodiment, the H-matrices shown in FIG. 7C are some examples of H-matrices for single bit error correction (SEC), and it will be understood that the scope of the present invention is not limited thereto.

When the H-matrice is implemented as shown in FIG. 7c, a simplified H-matrix (sim-H-mat) may be generated or determined as shown in FIG. 8. For example, referring to FIG. 8 , an abbreviated H-matrix (sim-H-mat) includes some rows (eg, second sub-rows) of the H-matrix (H-mat). It can be generated based on the information of

As a more detailed example, as described above, the H-matrix (H-mat) may be divided into a plurality of sub-matrices SM00 to SM15. Each of the plurality of partial matrices SM00 to SM15 may have a size of 8 × 8. That is, the H-matrix (H-mat) may be divided into units of 8 columns (ie, units of 8b). At this time, in each of the plurality of sub-matrices SM00 to SM15, the first sub-rows (rows corresponding to S0, S1, and S2) are composed of the same A0-th sub-matrix A0. , and each column of the A0th sub-matrix A0 represents all combinations that can be represented by three bits. In other words, the first sub-rows (rows corresponding to S0, S1, and S2) of the H-matrix (H-mat) are compared with S0, S1, and S2 of the syndrome (SYD). By doing so, it has a function of specifying the exact location of the error, and does not determine whether or not the error has occurred.

On the other hand, the second sub-rows (rows corresponding to S3, S4, S5, S6, and S7) of the H-matrice are the B00 to B15 sub-matrices (B00 to B15). B15). At this time, each of the B00 to B15th submatrices (B00 to B15) has different bit streams, but in the same submatrix, all columns have the same value. In this case, 16 bit strings for the second sub-rows (rows corresponding to S3, S4, S5, S6, and S7) of the H-matrix (H-mat) can be represented. At this time, 32 bit strings are combinable through 5 bits. That is, in the second sub-rows (rows corresponding to S3, S4, S5, S6, and S7) of the H-matrix (H-mat), each column is S3, S4 of the syndrome (SYD). , S5, S6, and S7, it can be determined whether or not an error has been detected.

According to an embodiment of the present invention, the abbreviated H-matrix (sim-H-mat), as described above, except for the rows necessary for specifying the error location in the H-matrix (H-mat), and some of the remaining information can be used to generate a reduced H-matrix (sim-H-mat). In this case, as shown in FIG. 8 , the reduced H-matrix (sim-H-mat) may include the B00th to B15th submatrices B00 to B15 and the parity matrix PR. The B00 to B15 submatrices B00 to B15 are [11000] ^T , [00111] ^T , [10100] ^T , [01011] ^T , [01100] ^T , [10011] ^T , [11100] ^T , [ The bit strings of 00011] ^T , [100111] ^T , [01101] ^T , [01010] ^T , [10101] ^T , [11010] ^T , [00101] ^T , [00110] ^T , and [11001] ^T are 8, respectively. It may have a structure that is repeated one by one (ie, repeated in 8b). The parity matrix (PR) may be an 8 × 8 identity matrix (IM).

In one embodiment, for the H-matrice described with reference to FIGS. 6 to 7C, a shortened H-matrix (sim-H-mat) as shown in FIG. 8 can be generated, , Some bits (S3, S4, S5, S6, S7) of the syndrome (SYD) are compared with each column of an abbreviated H-matrix (sim-H-mat) to check whether there is an error in the read data (RDT). It can be.

In one embodiment, the abbreviated H-matrix (sim-H-mat) as shown in FIG. 8 is a partial example, and the scope of the present invention is not limited thereto. For example, the abbreviated H-matrix (sim-H-mat) as shown in FIG. 8 constitutes a plurality of submatrices by dividing the H-matrix (H-mat) in units of 8b, but the H-matrix ( mat), it may be divided into units of 4b, units of 16 bits, or units of N bits (where N is a natural number). In this case, the size of the reduced H-matrix can be varied.

9 to 13 below, components of a fast DSF generator configured to generate a decoding status flag (DSF) based on the reduced H-matrix (sim-H-mat) of FIG. Some examples of the syndrome check circuit 115b, the parity error check circuit 115c, the high-speed data error check circuit 115e, and the DSF detection circuit 115d are shown and described.

However, the scope of the present invention is not limited thereto, and the configuration of the logical operation circuit for the components of the high-speed DSF generator may be variously varied depending on the implementation method or the H-matrix or the abbreviated H-matrix.

In addition, for brevity of the drawings and convenience of description, in the following drawings, the syndrome SYD may have a size of 8b, and each bit of the syndrome SYD is S0, S1, S2, S3, S4, and S5. , S6, and S7, and inverted bits of the syndrome (SYD) are denoted as S0B, S1B, S2B, S3B, S4B, S5B, S6B, and S7B.

9 is a diagram showing some examples of a syndrome check circuit of the high-speed DSF generator of FIG. 5c. The syndrome check circuit 115b may check whether all bits S0 to S7 of the syndrome SYD are “0” (ie, all-zero). For example, the syndrome check circuit 115b is configured for S0B, S1B, S2B, S3B, S4B, S5B, S6B, and S7B, which are inverted values of each bit (eg, each of S0 to S7) of the syndrome SYD. It can be configured to perform an AND operation. In this case, as seven AND gates having two input terminals are connected in a three-level structure, it can be checked whether all bits S0 to S7 of the syndrome SYD are “0” (ie, all-zero). .

When all bits S0 to S7 of the syndrome SYD are “0”, the syndrome information SYD_0 is output as “1” by the syndrome check circuit 115b of FIG. 9, and the When at least one bit (at least one of S0 to S7) is “1”, the syndrome information SYD_0 is output as “0” by the syndrome check circuit 115b of FIG. 9 .

In other words, if the syndrome information SYD_0 is output as “1” by the syndrome check circuit 115b of FIG. 9, there is no error in the read data RDT and parity data PRT corresponding to the syndrome SYD. , and the syndrome information (SYD_0) is output as “0” by the syndrome check circuit 115b of FIG. means to exist

10 is a diagram showing some examples of a parity error check circuit of the high-speed DSF generator of 5c. Referring to FIGS. 5C and 10 , the parity error check circuit 115c may detect whether there is an error in the parity data PRT based on the syndrome SYD.

In one embodiment, whether or not there is an error in the parity data (PRT) is the parity matrix (PR) of the abbreviated H-matrix (sim-H-mat) described with reference to FIG. 8 or described with reference to FIG. 7A. It can be detected based on the parity matrix (PR). For example, the parity error check circuit 115b may include a plurality of AND operation circuits AS10 to AS17. Each of the plurality of AND operation circuits AS10 to AS17 is a parity matrix PR of an abbreviated H-matrix (sim-H-mat) described with reference to FIG. 8 or a parity matrix PR described with reference to FIG. 7A. ), it can be connected to each bit S0 to S7 of the syndrome SYD.

As a more detailed example, the 10th AND operation circuit AS10 corresponds to the 0th column of the parity matrix PR (ie, [1, 0, 0, 0, 0, 0, 0, 0] ^T ), It can be connected to each bit of the syndrome (SYD). That is, the tenth AND operation circuit AS10 receives S0, S1B, S2B, S3B, S4B, S5B, S6B, and S7B as inputs, and outputs "1" when all of the received inputs are "1", , otherwise (that is, when at least one is 0), output "0". The eleventh AND operation circuit AS11 corresponds to the first column (ie, [0, 1, 0, 0, 0, 0, 0, 0] ^T ) of the parity matrix PR, so that each of the syndromes SYD Bits can be connected. That is, the tenth AND operation circuit AS10 receives S0B, S1, S2B, S3B, S4B, S5B, S6B, and S7B as inputs, and outputs “1” when all of the received inputs are “1”; , otherwise (that is, when at least one is 0), output "0". Similarly, the twelfth to seventeenth AND operation circuits A12 to AS17 are connected to respective bits of the syndrome SYD to correspond to the second to seventh columns of the parity matrix PR, respectively, and have respective inputs If all are "1", output "1"; otherwise (ie, at least one is 0), output "0".

That is, through the plurality of AND operation circuits AS10 to AS17, the syndrome SYD is compared with each column of the parity matrix PR, and it can be determined whether a column of bits identical to that of the syndrome SYD exists. The presence of the same column as the syndrome SYD among the columns of the parity matrix PR may mean that an error exists in the parity data PRT.

The parity error check circuit 115c includes a plurality of OR gates and performs an OR operation on the outputs of the plurality of AND operation circuits AS10 to AS17 through the plurality of OR gates to obtain parity error information (PRT_ERR). ) can be output. In one embodiment, when at least one of the outputs of the plurality of AND operation circuits AS10 to AS17 is “1”, the parity error information PRT_ERR is “1” and the plurality of AND operation circuits AS10 to AS17 is “1”. When all of the outputs of AS17) are "0", the parity error information (PRT_ERR) is "0".

In one embodiment, if the parity error information (PRT_ERR) is “1”, it indicates that an error exists in the parity data (PRT) corresponding to the syndrome (SYD), and if the parity error information (PRT_ERR) is “0”, it indicates that the syndrome (SYD) has an error. Indicates that there is no error in (SYD) and the corresponding parity data (PRT).

11 is a diagram showing some examples of a high-speed data error check circuit of the high-speed DSF generator of 5c. Referring to FIGS. 5C and 11 , the high-speed data error checking circuit 115e may determine whether there is an error in data based on the syndrome SYD.

In an embodiment, whether an error exists in data may be detected based on the abbreviated H-matrix (sim-H-mat) described with reference to FIG. 8 . For example, the high-speed data error check circuit 115e may include a plurality of AND operation circuits AS20 to AS2f. Each of the plurality of AND operation circuits AS20 to AS2f may be connected to some bits S3 to S7 of the syndrome SYD based on the abbreviated H-matrix (sim-H-mat) described with reference to FIG. 8 . can

As a more detailed example, the twentieth AND operation circuit AS20 calculates the columns (ie, [1, 1, 0, 0, 0] ^T ), it may be connected to some bits S3 to S7 of the syndrome SYD. That is, the twentieth AND operation circuit AS20 receives S3, S4, S5B, S6B, and S7B as inputs, and outputs “1” when all of the received inputs are “1”, and otherwise (i.e. , if at least one is 0), "0" is output. The 21st AND operation circuit AS21 calculates columns (ie, [0, 0, 1, 1, 1] ^T It may be connected to some bits S3 to S7 of the syndrome SYD to correspond to . That is, the twenty-first AND operation circuit AS20 receives S3B, S4B, S5, S6, and S7 as inputs, and outputs “1” when all of the received inputs are “1”, and otherwise (i.e. , if at least one is 0), "0" is output. Similarly, the 22nd to 22f AND operation circuits AS22 to AS2f respectively correspond to columns of the B02 to B15 submatrices B00 to B15 of the abbreviated H-matrix (sim-H-mat) of FIG. 8 . Correspondingly, some bits S3 to S7 of the syndrome SYN are connected. Each of the 22nd to 22f AND operation circuits AS22 to AS2f outputs "1" when all received inputs are "1", and otherwise (ie, when at least one is 0), " outputs 0".

That is, each column of an H-matrix (sim-H-mat) in which some bits (eg, S3 to S7) of the syndrome SYD are abbreviated through the plurality of AND operation circuits AS20 to AS2f, or It may be compared with each sub-matrix, and it may be determined whether a column identical to some bits S3 to S7 of the syndrome SYD exists. In the abbreviated H-matrix (sim-H-mat), the existence of the same column as some of the bits S3 to S7 of the syndrome SYD may mean that there is an error in the read data RDT. However, since only some bits of the syndrome (SYD) are compared through the shortened H-matrix (sim-H-mat), the occurrence position of the error is not detected.

The high-speed data error check circuit 115e may further include a plurality of OR gates. The high-speed data error check circuit 115e may output data error information DT_ERR by performing an OR operation on the outputs of the plurality of AND operation circuits AS20 to AS2f through a plurality of OR gates. In one embodiment, when at least one of the outputs of the plurality of AND operation circuits AS20 to AS2f is “1”, the data error information DT_ERR is output as “1”, and the plurality of AND operation circuits ( When all outputs of AS20 to AS2f) are "0", the data error information (DT_ERR) is output as "0".

In one embodiment, when the data error information DT_ERR is “1”, it indicates that there is an error in the read data RDT, and when the data error information DT_ERR is “0”, there is no error in the read data RDT. points to

12 is a diagram showing some examples of the DST detection circuit of the high-speed DSF generator of 5c. 5c and 12, the DST detection circuit 115d receives syndrome information (SYD_0) from the syndrome check circuit 115b and parity error information (PRT_ERR) from the parity error check circuit 115c, Data error information DT_ERR may be received from the high-speed data error check circuit 115e.

The DST detection circuit 115d may include OR gates, INV gates, and AND gates. The DST detection circuit 115d performs an OR operation on the syndrome information (SYD_0) and the parity error information (PR_ERR) through an OR gate, INV gates, and an AND gate, and performs an OR operation on the result of the OR operation and an inversion value and data error. The decoding status flag DSF may be generated by performing an AND operation on the inverted value of the information DT_ERR.

When the generated decoding status flag (DSF) is "1", it indicates that the decoding status is UE, and when the decoding status flag (DSF) is "0", it indicates that the decoding status is CE or NE.

For example, according to the DST detection circuit 115d shown in FIG. 12, the syndrome information (SYN_0) is "0", the parity error information (PRT_ERR) is "0", and the data error information (DR_ERR) is "0". ", the decoding status flag (DSF) will be "1". In other words, the existence of an error in the read data RDT or the parity data PRT is confirmed by the syndrome information SYN_0 of “0”, and the parity data PRT_ERR by the parity error information PRT_ERR of “0” When it is confirmed that there is no error in (PRT) and the data error information (DT_ERR) of “0” confirms that there is no error in the data, since the conditions for each information do not match each other, the final output error It may be determined that the corrected read data RDT_cor includes an error that cannot be corrected (ie, the decoding state is UE). In the remaining cases other than the above-mentioned case, the decoding status flag DSF is output as “0”, and at this time, the error-corrected read data RDT_cor finally output is normal data or error-corrected data (i.e., , the decoding state can be determined to be CE or NE).

As described above, according to the present invention, the fast DSF generator 115 can generate the decoding status flag (DSF) using the syndrome (SYD) without the error vector (ERV) generated by the syndrome decoding circuit 112. can In this case, since the high-speed DSF generator 115 operates in parallel with the syndrome decoding circuit 112, the overall delay time for the ECC decoder (ECC-DEC-1) can be reduced. In addition, since the high-speed data error check circuit 115e of the high-speed DSF generator 115 compares some bits of the syndrome SYD with a reduced H-matrix (sim-H-mat), each bit of the syndrome SYD Wiring complexity for can be reduced.

13 is a block diagram showing some examples of DSF detection circuitry of the high-speed DSF generator of FIG. 5C. For convenience of description, detailed descriptions of components described with reference to FIG. 12 are omitted. Referring to FIGS. 5C and 13 , the DSF detection circuit 115d-1 may generate the decoding status flag DSF of 1b through a method similar to that described with reference to FIG. 12 . At this time, the generated first decoding status flag DSF1 may be similar to the decoding status flag DSF described with reference to FIG. 12 . That is, when the first decoding state flag DSF1 is "1", the decoding state is UE, and when the first decoding state flag DSF1 is "0", it indicates that the decoding state is NE or CE.

The DSF detection circuit 115d-1 of FIG. 13 may generate a second decoding status flag DSF2 of 1b by inverting the syndrome information SYD_0. That is, when the second decoding status flag DSF2 is “1”, it indicates that an error is included in the read data RDT or parity data PRT, and when the second decoding status flag DSF2 is “0”, it indicates that the read data RDT or parity data PRT contains an error. It may indicate that there are no errors in (RDT) and parity data (PRT). In other words, when the second decoding status flag DSF2 is “1”, the decoding status is CE or UE, and when the second decoding status flag DSF2 is “0”, the decoding status is NE.

The DSF detecting circuit 115d-1 of FIG. 13 may combine the first and second decoding status flags DSF1 and DSF2 to output a decoding status flag DSF of 2b. For example, the least significant bit (LSB) of the decoding state flag DSF may correspond to the first decoding state flag DSF1DP, and the most significant bit (MSB) may correspond to the second decoding state flag DSF2. In this case, the decoding state flag (DSF) of 2b is “00” means that the decoding result is NE, “10” means that the decoding result is CE, and “11” means that the decoding result is UE. can It will be understood that the above-described bit combinations and bit values are merely examples and may be modified in various ways according to an implementation method of an ECC decoder.

As described above, the DSF detection circuit 115d-1 may inform the memory controller 11 of decoding results (eg, UE, CE, and NE) by generating a decoding status flag (DSF) of 2b. .

14 is a diagram showing some examples of an abbreviated H-matrix according to an embodiment of the present invention. In one embodiment, the abbreviated H-matrix (sim-H-mat) described with reference to FIG. 8 is the second partial rows (2nd) of the H-matrix (H-mat) used by the syndrome decoding circuit 112 sub-Rows) is created based on the information. On the other hand, the abbreviated H-matrix (sim-H-mat-UE) for UE determination shown in FIG. 14 is not included in the information of the second sub-rows of the H-matrix (H-mat). It can be created based on information that does not exist. For example, as described with reference to FIG. 8, the B00 to B15 submatrices (B00 to B15) included in the abbreviated H-matrix (sim-H-mat) are [11000] ^T , [ [00111] ^T , [10100] ^T , [01011] ^T , [01100] ^T , [10011] ^T , [11100] ^T , [00011] ^T , [100111] ^T , [01101] ^T , [01010] ^T , [ It can be implemented as columns of 10101] ^T , [11010] ^T , [00101] ^T , [00110] ^T , and [11001] ^T , and the B00 to B15 submatrices B00 to B15 are H-matrices (H -mat) may constitute second sub-rows.

On the other hand, as shown in FIG. 14, the abbreviated H-matrix (sim-H-Mat-UE) for UE determination is [01001] ^T , [01110] ^T , [10001] ^T , [10110] ^T , [ 10000] ^T , [01000] ^T , [00100] ^T , [00010] ^T , [00001] ^T , [01111] ^T , [10111] ^T , [11011] ^T , [11101] ^T , [11110] ^T , and [11111] can be implemented with submatrices such as ^T. Sub-matrices of the shortened H-matrix (sim-H-mat-UE) for UE determination are sub-matrices included in the 2nd sub-rows (ie, B00 ~B15) and other columns. As a more detailed example, each column included in the second sub-rows (2nd sub-Rows) of the H-matrix (H-mat) described with reference to FIGS. 7A to 7C is a total of 16 (parity matrix (PR) excluded). At this time, since the total number of combinations of bit strings through 5 bits is 2 ⁵ =32, bit strings that do not correspond to submatrices (ie, B00 to B15) are organized into 32-16 = 16 columns. At this time, since the column of [00000] ^T can correspond to the case where the syndrome (SYD) is all-zero (ie, there is no error), the abbreviated H-matrix for UE determination (sim-H-mat-UE ) are excluded. Accordingly, the abbreviated H-matrix (sim-H-mat-UE) for UE determination may include sub-matrices each composed of the aforementioned 10 columns and a parity matrix (PR).

In this case, if the columns of the third to seventh bits (S3 to S7) of the syndrome (SYD) match at least one of the columns of the shortened H-matrix (sim-H-mat-UE) for UE detection, This means that the syndrome SYD does not match all of the columns of the H-matrix H-mat (that is, the error location is not determined). Therefore, by comparing the columns of the third to seventh bits (S3 to S7) of the syndrome (SYD) with the columns of the abbreviated H-matrix (sim-H-mat-UE) for UE detection, it is possible to determine whether or not an error has occurred in the data. can be identified. Alternatively, in some cases, by comparing the columns of the third to seventh bits (S3 to S7) of the syndrome (SYD) with the columns of the abbreviated H-matrix (sim-H-mat-UE) for UE detection, the data It can be determined whether an uncorrectable error is included, that is, whether the decoding result is a UE.

FIG. 15 is a diagram showing some examples of a high-speed data error checking circuit using the shortened H-matrix for UE determination of FIG. 14; Referring to FIG. 15 , the high-speed data error check circuit 115e-2 may include a plurality of AND operation circuits AS30 to AS3e. Each of the plurality of AND operation circuits AS30 to AS3e is based on the abbreviated H-matrix (sim-H-mat-UE) for UE determination described with reference to FIG. S3 ~ S7) can be connected.

For example, the 30th AND operation circuit AS30 ^selects some bits ( S3 ~ S7) can be connected. That is, the thirtieth AND operation circuit AS30 receives S3B, S4, S5B, S6B, and S7 as inputs, and outputs "1" when all of the received inputs are "1", and otherwise (at least If one is "0"), output "0". The remaining AND operation circuits AS31 to AS3e use some bits S3 to S7 to correspond to columns of the abbreviated H-matrix sim-H-mat-UE for UE determination described with reference to FIG. 14, respectively. and outputs "1" when all of the input signals are "1", and outputs "0" otherwise (when at least one is "0").

The high-speed data error check circuit 115e-2 may include a plurality of OR gates. The high-speed data error check circuit 115e-2 may output data error information DT_ERR-2 by performing an OR operation on the outputs of the plurality of AND operation circuits AS30 to AS3a through a plurality of OR gates. there is. In one embodiment, when at least one of the outputs of the plurality of AND operation circuits AS30 to AS3a is "1", the data error information DT_ERR-2 is "1", otherwise (ie, all outputs are "0"), the data error information (DT_ERR-2) is "0".

In one embodiment, the data error information DT_ERR-2 of “1” may indicate that an error exists in the read data RDT or the parity data PRT. When the data error information DT_ERR-2 is “0”, it may indicate that there is no error in the read data RDT or there is an error that can be corrected.

16 is a diagram showing some examples of a DSF detection circuit using data error information from the high-speed data error check circuit of FIG. 15; Referring to FIGS. 14, 15, and 16 , the DSF detection circuit 115d-2 may include INV gates and AND gates. The DSF detection circuit 115d - 2 may invert the syndrome information SYN_0 through the first INV gate. The DSF detection circuit 115d - 2 may perform an AND operation on the output of the first INV gate (ie, the inverted syndrome information) and the data error information DT_ERR-2 through the first AND gate. The DSF detection circuit 115d - 2 may invert the parity error information PRT_ERR through the second INV gate. In one embodiment, the parity error information (PRT_ERR) may be calculated by the parity error check circuit 115c described with reference to FIG. 10 and is information indicating whether there is a 1-bit error in the parity data (PRT).

The DSF detection circuit 115d - 2 may generate the decoding state information DSF by performing an AND operation on the output of the first AND gate and the output of the second INV gate through the second AND gate. When the decoding state information (DSF) is “1”, it indicates that the decoding state is UE, and when the decoding state information (DSF) is “0”, it may indicate that the decoding state is NE or CE.

For example, if the decoding status information (DSF) is "1", the syndrome information (SYD_0) is "0", the data error information (DT_ERR-2) is "1", and the parity error information (PR_ERR) is " This is the case of 0". This means that an error in the data and parity data is detected by the syndrome information (SYD_0), an uncorrectable error in the data or parity data is detected in the data error information (DT_ERR-2), and a parity error This means that no error is detected in the parity data PRT by the information PR_ERR. In this case, the ECC decoding result will be UE. On the other hand, in the remaining cases except for the case described above, the ECC decoding result will be NE or CE.

In one embodiment, it is detected that there is an error in the data and parity data by the syndrome information (SYD_0), and the existence of an uncorrectable error in the data or parity data is detected in the data error information (DT_ERR-2), , When it is detected that the parity data PRT has an error by the parity error information PR_ERR, the decoding status flag DSF will be "0" (ie, NE or CE). In this case, the error included in the parity data PRT may indicate a 1-bit error. If the error included in the parity data PRT exceeds 2 bits or exceeds the error correction capability of the ECC engine, the decoding status flag DSF may be determined to be “1” (ie UE).

FIG. 17 is a diagram showing some examples of a DSF detection circuit using data error information from the high-speed data error check circuit of FIG. 15; 15 and 17, the DSF detection circuit 115d-3 performs a first decoding status flag (ie, / SYD_0 * DT_ERR-2) * / PR_ERR) through an operation similar to that described with reference to FIG. 16 DSF1) can be created. The DSF detection circuit 115d - 3 may generate a second decoding status flag DSF2 by inverting the syndrome information SYD_0. The DSF detecting circuit 115d - 3 may generate a decoding status flag DSF of 2b by combining the first and second decoding status flags DSF1 and DSF2 . The meanings of the first decoding status flag DSF1 of 1b, the second decoding status flag DSF2 of 1b, and the decoding status flag DSF of 2b are similar to those described with reference to FIG. A detailed description thereof is omitted.

As described above, the ECC decoder (ECC-DEC) according to the present invention may generate a decoding status flag (DSF) based on information not included in some rows of the H-matrix. In one embodiment, the high-speed data error check circuit 115e-2 described with reference to FIGS. 14 and 15 assigns each column of a shortened H-matrix (sim-H-mat-UE) for UE determination a syndrome (SYD). ), it is possible to determine whether an error has occurred in the read data RDT. At this time, since each column of the abbreviated H-matrix (sim-H-mat-UE) for UE determination is based on information not included in the H-matrix (H-mat), some bits of the syndrome (SYD) The fact that it is identical to any one of the columns of the abbreviated H-matrix (sim-H-mat-UE) for judgment (ie, DT_ERR-2 is output as “1”) indicates that the read data (RDT) cannot be corrected. It may mean that an error is included (i.e., the decoding state is UE), and that some bits of the syndrome (SYD) are different from all of the columns of the shortened H-matrix (sim-H-mat-UE) for UE determination. (that is, DT_ERR-2 is output as “0”) means that the read data (RDT) does not contain an error or contains an error that can be corrected (that is, the decoding status is NE or CE). can That is, the data error information DT_ERR-2 generated by the high-speed data error check circuit 115e-2 described with reference to FIGS. 14 and 15 is the DSF detection circuit 115d described with reference to FIGS. 16 and 17 -2, 115d-3) and can be used as a decoding status flag (DSF).

In one embodiment, the configuration of the above-described ECC decoder is implemented based on a specific H-matrix, and according to the structure and characteristics of the H-matrix, the configuration of the ECC decoder (in particular, the decoding state flag generator) according to the present invention It can be modified in various ways.

18 is a flowchart for explaining a method of generating a reduced H-matrix according to an embodiment of the present invention. In one embodiment, the flowchart of FIG. 18 may be performed by a design tool for an ECC circuit in a manufacturing step of the memory device 100 .

Referring to FIG. 18 , in step S210, an H-matrix may be determined. For example, an H-matrix used in the ECC circuit 110 (in particular, an ECC decoder) may be determined according to reliability or performance of the memory device 100 . In one embodiment, the H-matrix may be determined in various ways considering various factors such as an implementation method of the ECC circuit 110, an error correction algorithm, or error correction capability.

In step S220, a reduced H-matrix (sim-H-mat) may be extracted based on the characteristics or partial information of the H-matrix. For example, it is assumed that the H-matrices are the H-matrices described with reference to FIGS. 6, 7A, 7B, and 7C. In this case, the H-matrix is implemented in units of 8 columns, the first partial rows (rows corresponding to S0 to S3) are repeated with identical partial matrices, and the second partial rows (rows corresponding to S4 to S7) is implemented with a plurality of submatrices containing the same columns. In this case, instead of comparing the entire column of the H-matrix (H-mat) with the syndrome (SYD), only some information (that is, the second partial rows (rows corresponding to S4 to S7)) By comparing with some bits S4 to S7 of (SYD), whether the syndrome SYD matches at least one of the columns of the H-matrix H-mat (that is, read data RDT) or parity data PRT It can be determined whether there is an error in ). That is, it may be determined whether an error exists in the read data RDT or the parity data PRT by comparing only some bits of the syndrome SYD and some information of the H-matrix.

As described above, the characteristics of the H-matrice may vary depending on how the H-matrice is implemented, and may not be divided in specific row units or specific column units. For example, in a reduced H-matrix (sim-H-mat) generated based on some H-matrices (H-mat), for column 0, S0, S1, S2, S3, and S4 may be compared, and for the first column, values corresponding to S0, S2, S4, S6, and S7 of the syndrome SYD may be compared. In one embodiment, when the size of the read data RDT is 128b, the size of the H-matrix may have a size of 8 × 128 + 8 × 8 (parity matrix). In this case, when the H-matrix is divided into units of 8b, the reduced H-matrix (sim-H-mat) may have a size of (8-log ₂ 8) × (128/8). Alternatively, when the H-matrix is divided into 16b units, the reduced H-matrix (sim-H-mat) may have a size of (8-log ₂ 16) × (128/16).

In one embodiment, a shortened H-matrix (sim-H-mat) may be generated based on partial information included in the H-matrix. Alternatively, an abbreviated H-matrix (sim-H-mat) may be generated based on partial information included in the H-matrix and other information (ie, partial information not included in the H-matrix). In this case, the reduced H-matrix (sim-H-mat) may be extracted or generated as described with reference to FIGS. 14 and 15, and in this case, the reduced H-matrix indicates that the decoding state is UE. can be identified.

In one embodiment, a shortened H-matrix (sim-H-mat) may be generated through various logical operations (OR, AND, XOR, etc.) on specific columns of the H-matrix.

In step S330, a high-speed DSF generator may be constructed based on the reduced H-matrix (sim-H-mat). For example, as described with reference to FIGS. 1 to 17 , based on the reduced H-matrix (sim-H-mat), a high-speed data error check circuit can be implemented, and the high-speed DSF generator is A decoding status flag (DSF) is generated based on the output of the error check circuit (ie, data error information), the output of the syndrome check circuit (ie, syndrome information), and the output of the parity error check circuit (ie, parity error information). can do.

In one embodiment, it is understood that the H-matrix may be variously changed according to the implementation method or performance of the ECC circuit, and the implementation method of the reduced H-matrix may also be variously modified according to the transformation of the H-matrix. It will be.

19 is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring to FIG. 19 , a memory system 1000 may include a memory controller 1100 , an ECC circuit 1200 , and a memory device 1300 . The memory controller 1100 may store data in the memory device 1300 or read data stored in the memory device 1200 .

In an embodiment, the ECC circuit 1200 may be located in a data path between the memory controller 1100 and the memory device 1300 . The ECC circuit 1200 may be configured to correct errors in data transmitted and received between the memory controller 110 and the memory device 1300 . In one embodiment, the ECC circuit 1200 may generate a decoding state flag (DSF) based on the operating method described with reference to FIGS. 1 to 18 .

20 is a block diagram showing a memory system according to an embodiment of the inventive concept. Referring to FIG. 20 , a memory system 2000 may include a memory controller 2100 and a memory device 2200 . The memory controller 2100 may include an ECC circuit 2110 . The ECC circuit 2110 may be configured to generate parity data for data to be stored in the memory device 2200 or to correct errors in data read from the memory device 2200 and based on the parity data. The ECC circuit 2110 may generate a decoding status flag (DSF) based on the method described with reference to FIGS. 1 to 18 .

21 is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring to FIG. 21 , a memory system 3000 may include a memory controller 3100 and a memory device 3200 . The memory controller 3100 may include a controller ECC circuit 3110 . The controller ECC circuit 3110 generates first parity for write data to be stored in the memory device 3200 and corrects errors in the read data based on the read data received from the memory device 3200 and the first parity. can

The memory device 3200 may include a memory ECC circuit 3210 . The memory ECC circuit 3210 generates second parity for the write data and the first parity received from the memory controller 3100 and based on the read data, the first parity, and the second parity stored in the memory device 3200. It is possible to correct errors in the read data and the first parity.

In one embodiment, each of the controller ECC circuit 3110 and the memory ECC circuit 3210 may generate a decoding status field (DSF) based on the method described with reference to FIGS. 1 to 18 .

In one embodiment, in the embodiments described with reference to FIGS. 1 to 18, the ECC circuit 110 has been described as an on-die ECC (OD-ECC) circuit included in the memory device 100, but the present invention The scope of is not limited thereto. For example, as described with reference to FIGS. 19 to 21 , the ECC circuit may be located inside or outside the memory device or within the memory controller.

22 is a diagram showing some examples of a memory package according to an embodiment of the present invention. Referring to FIG. 22 , a memory package 4000 may include a plurality of memory dies 4110 to 4140 and a buffer die 4200 . Each of the plurality of memory dies 4110 to 4140 may be a DRAM device. The plurality of memory dies 4110 to 4140 and the buffer die 4200 may be implemented in a stacked structure, and may be electrically connected to each other and communicate with each other through a through silicon via (TSV).

In one embodiment, the memory package 4000 may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) ), etc., and may be provided as a single semiconductor package.

The buffer die 4200 may communicate with an external host device (or memory controller). The buffer data 4200 may be configured to temporarily store data to be stored in the plurality of memory dies 4110 to 4140 or to temporarily store data read from the plurality of memory dies 4110 to 4140 . In one embodiment, the buffer die 4200 may include ECC circuitry 4210. The ECC circuit 4210 may generate parity for data to be stored in the memory dies 4110 to 4140 or correct errors in data read from the memory dies 4110 to 4140 . In one embodiment, the ECC circuit 4210 may be implemented based on the method described with reference to FIGS. 1 to 18 or generate a decoding status flag (DSF).

23 is a diagram showing some examples of a memory package according to an embodiment of the present invention. Referring to FIG. 23 , a memory package 5000 may include a plurality of memory dies 5110 to 5140 and a host die 5200 . The plurality of memory dies 5110 to 5140 are electrically connected to each other through micro bumps (MCBs), may have a stacked structure, and may be directly stacked on the host die 5200 . Host die 5200 may be an SoC, CPU, or GPU. In one embodiment, each of the plurality of memory dies 5110 to 5140 or the host die 5200 may include the ECC circuit described with reference to FIGS. 1 to 18 .

24 is a block diagram exemplarily showing a memory module 6000 to which a memory device according to the present invention is applied. Referring to FIG. 24 , a memory module 6000 may include a register clock driver (RCD 6100), a plurality of memory devices 6210 to 6290, and a plurality of data buffers DB.

The RCD 6100 may receive a command/address CA and a clock signal CK from an external device (eg, host or memory controller). The RCD 6100 may transfer a command/address CA to the plurality of memory devices 6210 to 6290 and control the plurality of data buffers DB based on the received signals.

Each of the plurality of memory devices 6210 to 6290 may be respectively connected to a plurality of data buffers DB through memory data lines MDQ.

In one embodiment, each of the plurality of memory devices 6210 to 6290 includes the ECC circuit described with reference to FIGS. 1 to 18 , and a decoding state flag based on the method described with reference to FIGS. 1 to 18 . (DSF) can be created. The plurality of data buffers DB may transmit and receive data to and from an external device (eg, a host or a memory controller) through a plurality of data lines DQ.

In one embodiment, the memory module 6000 shown in FIG. 24 may have a load reduced dual in-line memory module (LR-DIMM) form factor. However, the scope of the present invention is not limited thereto, and the memory module 6000 may have a registered DIMM (RDIMM) form factor in which a plurality of data buffers DB are omitted.

In one embodiment, the memory module 6000 may further include an ECC circuit located outside the plurality of memory devices 6210 to 6290, and a decoding status flag based on the method described with reference to FIGS. 1 to 18 (DSF).

In one embodiment, any one of the plurality of memory devices 6210 to 6290 may be configured to store parity data. The parity data may be provided from an external device (eg, a host or a memory controller), and in this case, the external device includes the ECC circuit described with reference to FIGS. 1 to 18 or refers to FIGS. 1 to 18 Based on the method described above, a decoding status flag (DSF) can be generated.

25 is a diagram illustrating a system 7000 to which a storage device according to an embodiment of the present invention is applied. The system 7000 of FIG. 25 is basically a mobile phone such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an internet of things (IOT) device. (mobile) system. However, the system 7000 of FIG. 25 is not necessarily limited to a mobile system, and can be used for vehicles such as a personal computer, a laptop computer, a server, a media player, or a navigation system. It may be an automotive device or the like.

Referring to FIG. 25 , a system 7000 may include a main processor 7100, memories 7200a and 7200b, and storage devices 7300a and 7300b, and additionally includes an image capturing device. 7410, user input device 7420, sensor 7430, communication device 7440, display 7450, speaker 7460, power supplying device 7470 and connections It may include one or more of the connecting interfaces 7480.

The main processor 7100 may control the overall operation of the system 7000, and more specifically, the operation of other components constituting the system 7000. The main processor 7100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 7100 may include one or more CPU cores 7110 and may further include a controller 7120 for controlling the memories 7200a and 7200b and/or the storage devices 7300a and 7300b. Depending on embodiments, the main processor 7100 may further include an accelerator 7130 that is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 7130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be physically independent from other components of the main processor 7100. It may be implemented as a separate chip.

The memories 7200a and 7200b may be used as main memory devices of the system 7000 and may include volatile memories such as SRAM and/or DRAM, but may include nonvolatile memories such as flash memory, PRAM, and/or RRAM. may be The memories 7200a and 7200b may also be implemented in the same package as the main processor 7100 .

In one embodiment, the memories 7200a and 7200b may be a memory device including the ECC circuit described with reference to FIGS. 1 to 18, and based on the method described with reference to FIGS. 1 to 18, the decoding state A flag (DSF) can be created.

The storage devices 7300a and 7300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 7200a and 7200b. The storage devices 7300a and 7300b may include storage controllers 7310a and 7310b and non-volatile memories (NVMs) 7320a and 7320b that store data under the control of the storage controllers 7310a and 7310b. can The non-volatile memories 7320a and 7320b may include flash memory of a 2-dimensional (2D) structure or a 3-dimensional (3D) V-NAND (Vertical NAND) structure, but may include other types of memory such as PRAM and/or RRAM. It may also include non-volatile memory.

The storage devices 7300a and 7300b may be included in the system 7000 while being physically separated from the main processor 7100 or may be implemented in the same package as the main processor 7100 . In addition, the storage devices 7300a and 7300b have a form such as a solid state device (SSD) or a memory card, so that other components of the system 7000 can be accessed through an interface such as a connection interface 7480 to be described later. It may also be coupled to be detachable with the . The storage devices 7300a and 7300b may be devices to which standards such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. It's not.

The photographing device 7410 may capture still images or moving images, and may be a camera, camcorder, and/or webcam.

The user input device 7420 may receive various types of data input from a user of the system 7000, and may use a touch pad, a keypad, a keyboard, a mouse, and/or It may be a microphone or the like.

The sensor 7430 can detect various types of physical quantities that can be acquired from the outside of the system 7000 and convert the detected physical quantities into electrical signals. The sensor 7430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device 7440 may transmit and receive signals with other devices outside the system 7000 according to various communication protocols. Such a communication device 7440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).

The display 7450 and the speaker 7460 may function as output devices that output visual information and auditory information to the user of the system 7000, respectively.

The power supply device 7470 may appropriately convert power supplied from a battery (not shown) and/or an external power source built into the system 7000 and supply the power to each component of the system 7000 .

The connection interface 7480 may provide a connection between the system 7000 and an external device connected to the system 7000 and capable of exchanging data with the system 7000. The connection interface 7480 is an Advanced Technology (ATA) Attachment), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, It can be implemented in various interface methods such as USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded universal flash storage), CF (compact flash) card interface, etc. there is.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined by the following claims as well as those equivalent to the claims of this invention.

Claims (20)

In the memory device,
a memory cell array configured to store first data and first parity data;
an ECC circuit configured to perform error correction code decoding based on the first data and first parity data, and output error-corrected data and a decoding status flag; and
an input/output circuit configured to provide the error corrected data and the decoding flag to a memory controller;
The ECC circuit is:
a syndrome generator configured to generate a syndrome based on the first data and first parity data;
a syndrome decoding circuit configured to decode the syndrome to generate an error vector;
correction logic circuitry configured to generate the error corrected data based on the error vector and the first data; and
and a fast decoding status flag (DSF) generator configured to generate the decoding status flag based on the syndrome, without the error vector.
According to claim 1,
wherein the syndrome decoding circuit and the fast decoding status flag generator operate in parallel.
According to claim 1,
The memory device of claim 1 , wherein the syndrome decoding circuit generates the error vector by comparing the syndrome with each column of a parity-check matrix.
According to claim 3,
The fast decoding status flag generator is:
a syndrome check circuit configured to determine whether the syndrome is all-zero and output syndrome information;
a parity error check circuit configured to compare the syndrome with each column of a parity matrix to determine an error in the first parity data and output parity error information;
a high-speed data error check circuit configured to determine an error of the first data or first parity data by comparing a portion of the syndrome with each column of a reduced-parity check matrix and output data error information; and
and a decoding status flag detection circuit configured to output the decoding status flag based on the syndrome information, the parity error information, and the data error information.
According to claim 4,
The syndrome information indicates that the syndrome is not all-zero, the parity error information indicates that there is no error in the first parity data, and the data error information indicates that there is no error in the first data or first parity data. When indicated, the decoding status flag indicates that the first data has an uncorrectable error.
According to claim 4,
The syndrome information indicates that the syndrome is not all-zero, the parity error information indicates that there is no error in the first parity data, and the data error information indicates that there is no error in the first data or first parity data. When indicated, the decoding status flag indicates that there is an uncorrectable error in the first data;
If the syndrome information indicates that the syndrome is not all-zero and the parity error information does not indicate that there is no error in the first parity data, or the data error information indicates that the first data or an error in the first parity data If not indicating none, the decoding status flag indicates that there is a correctable error in the first data;
The syndrome information does not indicate that the syndrome is not all-zero, the parity error information does not indicate that there is no error in the first parity data, or the data error information does not indicate that the first data or the first parity data If it does not indicate that there is no error, the decoding status flag indicates that the first data does not contain an error (non-error).
According to claim 4,
The parity matrix is an n × n unit matrix, where n is the number of bits included in the syndrome,
The reduced parity-check matrix includes only information of some rows of the parity-check matrix used by the syndrome decoding circuit.
According to claim 7,
The first data is 128b, the first parity data is 8b, the syndrome is 8b, the parity-check matrix has a size of 8×128, and the reduced parity check matrix is (8-log ₂ m) A memory device having a size × (128 × m), where m is an integer greater than 1.
According to claim 4,
The parity matrix is an n × n unit matrix, where n is the number of bits included in the syndrome,
The reduced parity-check matrix includes only information not included in some rows of the parity-check matrix used by the syndrome decoding circuit.
According to claim 9,
The syndrome information indicates that the syndrome is not all-zero, the parity error information indicates that the syndrome is different from all columns of the parity matrix, and the data error information indicates that a part of the syndrome is the reduced parity-check matrix. When indicating that it corresponds to at least one column of , the decoding status flag indicates that there is an uncorrectable error in the first data,
The syndrome information indicates that the syndrome is not all-zero, the parity error information indicates that the syndrome corresponds to at least one column of the parity matrix, and the data error information indicates that a part of the syndrome corresponds to the reduced parity- When indicating that it corresponds to at least one column of a check matrix, the decoding status flag indicates that the first data has a correctable error or that the first data does not contain an error (non-error). memory device pointed to.
According to claim 1,
The ECC circuit is:
The memory device further comprising an ECC encoder configured to generate the first parity data for the first data based on a basis bit.
According to claim 1,
a command and address buffer configured to receive and buffer command and address signals (CA) from the memory controller;
an address decoder configured to receive address signals from the command and address buffers and to decode the address signals;
a command decoder configured to receive a command signal from the command and address decoder and to decode the command signal;
a row decoder configured to control a plurality of word lines connected to the memory cell array according to a result of the address decoding by the address decoder;
a column decoder configured to control a plurality of bit lines connected to the memory cell array according to a result of the address decoding by the address decoder; and
Sense configured to store the first data and the first parity data in the memory cell array or read the first data and the first parity data stored in the memory cell error, under the control of the command decoder. A memory device further comprising an amplifier and a write driver.
An error correction code (ECC) circuit configured to correct first data based on first data and first parity data stored in a memory device,
a syndrome generator configured to generate a syndrome based on the first data from the memory device and the first parity data;
syndrome decoding circuitry configured to compare the syndrome with each column of a parity-check matrix to generate an error vector;
correction logic circuitry configured to generate the error corrected data based on the error vector and the first data; and
a high-speed decoding status flag (DSF) generator configured to generate a decoding status flag indicating a decoding status for the error corrected data based on the syndrome and a reduced parity-check matrix;
The reduced parity-check matrix includes only some information of the parity-check matrix.
According to claim 13,
wherein the fast decoding status flag generator operates in parallel with the syndrome decoding circuit and the correction logic circuit.
According to claim 13,
The parity-check matrix has a size of a × b, where each of a and b is a natural number,
The reduced parity-check matrix has a size of c × d, where c is a natural number smaller than a, and d is a natural number smaller than d;
The c rows of the reduced parity-check matrix include information on first partial rows among the a rows of the parity-check matrix, and the number of the first partial rows is c. ECC circuit.
According to claim 13,
The fast decoding status flag generator is:
a syndrome check circuit configured to determine whether the syndrome is all-zero and output syndrome information;
a parity error check circuit configured to compare the syndrome with each column of a parity matrix to determine an error in the first parity data and output parity error information;
a high-speed data error check circuit configured to determine an error in the first data or first parity data by comparing a portion of the syndrome with each column of the reduced-parity check matrix and output data error information; and
and a decoding status flag detection circuit configured to output the decoding status flag based on the syndrome information, the parity error information, and the data error information.
According to claim 13,
The ECC circuit further comprising an ECC encoder configured to generate the first parity data for the first data based on a basis bit before the first data is stored in the memory device.
According to claim 13,
The ECC circuit is an on-die ECC (OD-ECC) circuit included in the memory device.
A method of operating an error correction code (ECC) circuit configured to correct first data based on first data and first parity data stored in a memory device,
generating a syndrome based on the first data and the first parity data;
generating an error vector based on the syndrome and the parity-check matrix;
generating error-corrected data by performing a logic operation on the error vector and the first data;
generating a decoding status flag based on the syndrome and the reduced parity-check matrix; and
Transmitting the error-corrected data and the decoding status flag to a memory controller;
The generating of the error vector and the generating of the decoding status flag are performed in parallel.
According to claim 19,
Generating a decoding status flag based on the syndrome and the reduced parity-check matrix comprises:
determining whether the syndrome is all-zero and generating syndrome information;
generating parity error information including information about an error of the first parity data by comparing the syndrome with each column of a parity matrix;
comparing a part of the syndrome with each column of the reduced parity-check matrix to generate data error information including an error of the first data or information about an error of the first parity data; and
generating the decoding state flag based on the syndrome information, the parity error information, and the data error information;
The syndrome information indicates that the syndrome is not all-zero, the parity error information indicates that there is no error in the first parity data, and the data error information indicates that there is no error in the first data or first parity data. If indicated, the decoding status flag indicates that there is an uncorrectable error in the first data.

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