KR20230000816A - Structure of GaN power device consisting of self-aligned n-p junction gate and its fabrication method - Google Patents

Abstract

The present invention relates to a power semiconductor element and a manufacturing method thereof. The power semiconductor element includes: an active layer (3) having a part in which a 2DEG layer (7) is formed; a spacer layer (4) located in an upper part of the active layer (3); a gate located on a portion of an upper part of the spacer layer (4) and having a p-GaN epi layer (5) and an n-GaN epi layer (6) stacked therein; an n-type source (10) formed on the spacer layer (4) in a lower part of one side of the gate; an n-type drain (9) located on a side opposite to the source (10) with respect to the gate, while located in a part of the spacer layer (4) spaced apart from the gate; an SPF thin film (8) deposited on the front surface of the gate and the spacer layer (4); and metal electrodes (13, 14) coming in ohmic contact with the drain (9) and the source (10) through a window formed on the SPF thin film (8), respectively. Therefore, the present invention is capable of increasing thermal stability, reliability and efficiency.

Description

GaN power semiconductor device consisting of self-aligned n-p junction gate and its fabrication method {Structure of GaN power device consisting of self-aligned n-p junction gate and its fabrication method}

The present invention relates to a GaN power semiconductor device and a manufacturing method thereof, and more particularly, to a high-performance power semiconductor using a HEMT epitaxial structure of a wide bandgap semiconductor.

Until now, most power semiconductor devices have been developed and used using Si semiconductors, which are inexpensive and have long-term reliability and stability. Recently, however, the importance of environment and energy efficiency has increased, and the electric vehicle, drone, and robot industries are growing.

These highly mobile applications and systems require more efficient, smaller and lighter power semiconductors. Therefore, attempts to develop and apply power semiconductors using WBG (Wide Band Gap) semiconductor materials such as SiC, GaN, and Ga ₂ O ₃ are active.

U.S. Patent Publication US2010/0019279A1 (published on Jan. 28, 2010) proposed a GaN HEMT device in which a rectifier is made with an anode connected to an ohmic and a schottky, and at the same time the same schottky is made as a gate.

To drive the enhancement mode (normally-off), a method of controlling the threshold voltage by implanting F ^- ions into the lower Schottky area is used. However, the problem with this device is that the Schottky gate formed of F ^- ions controls the threshold voltage to move to some positive (+) value, but this reduces the transconductance or sufficiently secures the reliability of device operation. No problems remain.

In addition, European Patent Publication EP01965433A3 (published on July 29, 2009) suggests a device structure in which successive primary, secondary, and tertiary field plates are applied to form a gate, A high-voltage GaN transistor exhibiting performance of driving from 600V to 900V with a low resistance of 5 to 6.6 mΩ-cm ² is described. However, trench etch is applied to adjust the threshold voltage of the gate, but this method is very disadvantageous in securing reproducibility and uniformity.

As another prior art, US Patent Publication US2009/0267078A1 (published on October 29, 2009) grows an AlXN (X = Ga or In) layer doped with Si on top of a conventional AlGaN / GaN epitaxial, and trenches the gate Etching and a rather complex structure for fabricating a MIS-type gate using an insulator thin film were presented.

It provides the advantage of enabling enhancement driving by increasing the threshold voltage and lowering the on-resistance of the channel. However, the gate insulating film contacts the lower channel (2DEG-derived layer) to reduce the mobility of the carrier or the position where the insulating film is formed must be very precise, but there is a problem of insufficient reproducibility to adjust it.

In addition, the recessed-gate structure approach toward normally off high-voltage AlGaN / GaN HEMT for power electronic applications (S. Saito, Y. Takada, I. Omura, IEEE Trans. on Electronic Devices. 2006) It relates to a device fabricated with a recessed gate structure. Similar to trench etching, recess etching also has problems in reproducibility and uniformity, and furthermore, since the recessed area is large, source-gate resistance and gate-drain resistance increase, thereby reducing device performance.

And High-performance normally off p-GaN gateHEMT with composite AlN/Al _0.17 Ga _0.83 N/Al _0.3 Ga _0.7 N barrier layersdesign (HC Chiu, YS Chang, BH Li, HC Wang, HL Kao, AR Xuan, J. of Electron Devices Society Vol. The reducing effect was presented. Many research results have been published on the same device structure, and in this paper, the problem of reducing the threshold voltage from 2.1V to 1.7V was shown.

As described above, the conventional technology is evolving in various forms. An attempt was made to apply a horizontal type, vertical type, metal-semiconductor junction, and field amplifier plate using a heterojunction HEMT structure WBG semiconductor. However, GaN FET power semiconductor devices that operate high-frequency and high-power signals with high efficiency still require performance improvement through many technological developments.

As described above, the conventional device according to the prior art has a low operating speed and a large characteristic fluctuation range according to a change in temperature, so there is a limit to manufacturing a high-performance device.

A technical problem to be solved by the present invention is to provide a power semiconductor device capable of high operating speed and minimizing variation in characteristics due to temperature changes and a manufacturing method thereof.

Specifically, an object of the present invention is to provide a power semiconductor device capable of increasing driving voltage and driving current and a manufacturing method thereof.

In addition, another object of the present invention is to provide a power semiconductor device that is thermally stable and exhibits linear operating characteristics and a manufacturing method thereof.

In addition, the present invention is to provide a power semiconductor device capable of generating less heat and increasing reliability and efficiency, and a manufacturing method thereof.

Specifically, in terms of reliability and efficiency, the present invention provides a threshold voltage (V _th ) and a gate driving voltage (V _G ) of 3 to 5V or 3 to 10V compatible with Si CMOS circuits. A power semiconductor device and its manufacture in providing a way.

A power semiconductor device according to one aspect of the present invention for solving the above problems includes an active layer 3 in which a 2DEG layer 7 is partially formed, and a spacer layer located on top of the active layer 3 (4), a gate located on an upper portion of the spacer layer (4), on which the p-GaN epitaxial layer (5) and the n-GaN epitaxial layer (6) are stacked, and the spacer under one side of the gate An n-type source 10 formed on the layer 4, and an n-type source 10 located on the opposite side of the gate to the source 10, but located on a part of the spacer layer 4 spaced apart from the gate. of the drain 9, the SPF thin film 8 deposited on the entire surface of the gate and spacer layer 4, and the drain 9 and the source 10 through a window formed in the SPF thin film 8 It may include metal electrodes 13 and 14 in ohmic contact with each other.

In an embodiment of the present invention, an n-type gate ion implantation layer 11 formed on a portion of the n-GaN epitaxial layer 6 may be further included.

In an embodiment of the present invention, a metal electrode 15 in ohmic contact with the gate ion implantation layer is further included, wherein the metal electrode 15 extends toward the metal electrode 13 connected to the drain to form a field plate. can form

In an embodiment of the present invention, the p-GaN epitaxial layer 5 is doped with p-type impurities in a range of 10 ¹⁷ to 10 ¹⁹ cm ^-3 , and the n-GaN epitaxial layer 6 is doped with n-type impurities. It may be doped with 10 ¹⁶ to 10 ¹⁸ cm ^-3 .

In an embodiment of the present invention, the SPF thin film 8 may be a SiO ₂ dielectric thin film with a thickness of 30 to 200 nm.

In addition, a power semiconductor device manufacturing method according to another aspect of the present invention, a) an AlGaN spacer layer 4 on top of an active layer 3, which is an undoped GaN layer, and a p-GaN epitaxial doped with p-type impurities A layer 5 and an n-GaN epitaxial layer 6 doped with n-type impurities are sequentially grown and patterned to form a p-GaN epitaxial layer 5 and n-GaN positioned on a part of the upper part of the spacer layer 4 forming a gate having a stacked structure of epitaxial layers 6; b) implanting and activating n-type impurity ions into the spacer layer 4 to form a source 10 and a drain 9; c) Depositing an SPF thin film 8 on the product of step c), removing a portion of the SPF thin film to expose the source 10, drain 9, and gate, and then forming the source 10, drain ( 9) and forming metal electrodes 14, 13, and 15 in ohmic contact with each gate.

In the embodiment of the present invention, in step b), n-type impurity ions are also implanted and activated into the n-GaN epitaxial layer 6 to form a gate ion implantation layer 11, thereby forming the metal electrode 15 This may make ohmic contact with the gate ion implantation layer 11 .

In an exemplary embodiment of the present invention, the metal electrode 15 may be formed to extend toward the metal electrode 13 making ohmic contact with the drain 9 to form a field plate.

In an embodiment of the present invention, in step a), the p-GaN epitaxial layer 5 is formed by growing GaN doped with a p-type impurity of 10 ¹⁷ to 10 ¹⁹ cm ^-3 , and n-type The n-GaN epitaxial layer 6 may be formed by growing GaN doped with an impurity of 10 ¹⁶ to 10 ¹⁸ cm ⁻³ .

In an embodiment of the present invention, in step c), the SPF thin film 8 may be formed by depositing a SiO ₂ dielectric thin film having a thickness of 30 to 200 nm.

The present invention has a relatively high operating speed, a high driving voltage and a high current, and an effect of increasing thermal stability, reliability, and efficiency compared to the prior art.

In particular, by designing to have compatibility with the Si CMOS circuit, there is an effect applicable to various technical fields.

1 to 8 are cross-sectional views of power semiconductor device manufacturing processes according to a preferred embodiment of the present invention.
9 is a partial cross-sectional view of a power semiconductor device according to a preferred embodiment of the present invention.
FIG. 10 is a cross-sectional view showing the resistance component of FIG. 9 .
11 is a comparison diagram of bandgap characteristics of a conventional power semiconductor device using a p-GaN epitaxial layer as a gate and a power semiconductor device of the present invention using n-GaN and p-GaN epitaxial layers as a gate.
12 is a graph of IV characteristics of the power semiconductor device of the present invention and the conventional power semiconductor device.
13 is a graph comparing current driving characteristics between the present invention and the prior art.
14 is a graph comparing conductance V characteristics of the present invention and the prior art.

Hereinafter, a power semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art, and the embodiments described below may be modified in many different forms, and the embodiments of the present invention The scope is not limited to the examples below. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

Terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Also, when used herein, "comprise" and/or "comprising" specifies the presence of the recited shapes, numbers, steps, operations, elements, elements, and/or groups thereof. and does not exclude the presence or addition of one or more other shapes, numbers, operations, elements, elements and/or groups. As used herein, the term "and/or" includes any one and all combinations of one or more of the listed items.

Although terms such as first and second are used in this specification to describe various members, regions, and/or regions, it is obvious that these members, parts, regions, layers, and/or regions are not limited by these terms. . These terms do not imply any particular order, top or bottom, or superiority or inferiority, and are used only to distinguish one element, region or region from another element, region or region. Thus, a first element, region or region described in detail below may refer to a second element, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to drawings schematically illustrating embodiments of the present invention. In the drawings, variations of the depicted shape may be expected, depending, for example, on manufacturing techniques and/or tolerances. Therefore, the embodiments of the present invention should not be construed as being limited to the specific shape of the region shown in this specification, but should include, for example, a change in shape caused by manufacturing.

1 to 8 are cross-sectional views of a manufacturing process of a power semiconductor device according to a preferred embodiment of the present invention.

First, as shown in FIG. 1, a buffer layer 2, an active layer 3, a spacer layer 4, a p-GaN epitaxial layer 5, and an n-GaN epitaxial layer ( 6) are formed sequentially.

As the semiconductor substrate 1, known substrates such as Si, sapphire, SiC, and AlN can be used.

The present invention is to grow an AlGaN/GaN HEMT epitaxial structure, and stress is generated between the substrate and the epitaxial layer due to differences in lattice constants and thermal expansion coefficients according to the types of semiconductor substrates listed above.

Since the entire substrate is bent by this stress and cracks occur in severe cases, a buffer layer 2 is grown on the semiconductor substrate 1 in the process of epitaxial growth to prevent damage to the device.

The buffer layer 2 may be formed by growing a low-temperature GaN, Al _y Ga _1-y N, or GaN/Al _y Ga _1-y N superlattice layer, and may have a multilayer structure in which these are combined.

Then, an active layer 3, which is an undoped GaN layer, is formed on top of the buffer layer 2. A spacer layer 4, which is an Al _x Ga _1-x N epitaxial layer, is grown on the active layer 3.

Here, Al _x Ga _1-x N controlled by x, the Al content, can be simplified and expressed as AlGaN. The Al content (x) is controlled between 0.1 and 0.4 and the thickness is controlled between 10 and 40 nm to control the density and mobility of 2DEG, the channel layer of the carrier.

In the present invention, the density of electrons in the 2DEG layer is 9x10 ¹² cm ^-2 to 1x10 ¹⁴ cm ^-2 , and the mobility is 1900 to 2100 cm ² /Vsec.

A p-GaN epitaxial layer 5 doped with 10 ¹⁷ to 10 ¹⁹ cm ^-3 of p-type impurities is grown on top of the AlGaN spacer layer ⁴ , and then n-type impurities are grown on top of it. An n-GaN epitaxial layer 6 doped with 10 ¹⁸ cm ⁻³ is grown.

According to this structure, a 2DEG is formed toward the active layer 3 between the GaN active layer 3 and the Al _x Ga _1-x N spacer layer 4 as a boundary, thereby completing the HEMT epitaxial structure for device fabrication.

Then, as shown in FIG. 2, a photoresist (PR) pattern is formed by phototransfer, and the n-GaN epitaxial layer 6 and the p-GaN epitaxial layer 5 are sequentially etched using the PR pattern, Form an n-p junction gate.

Therefore, when the 2DEG layer 7, which is an n-type channel on the lower side of the p-GaN epitaxial layer 5 forming the n-p junction gate, is included, an n-p-n junction structure is formed.

As a pattern used as an etching mask here, photoresist uses a process commonly used in the semiconductor process called photophototransfer. In addition, optical photo-transfer is also used in the following manufacturing process steps, and since it is not a technique specifically limited to the present invention and is one of conventional techniques, detailed description will not be given in relation to optical photo-transfer in the entire manufacturing process below.

2 shows a state in which the semiconductor substrate 1 and the buffer layer 2 are omitted.

Then, as shown in FIG. 3, an SPF thin film is formed on the entire top and side surfaces of the gate made of the n-GaN epitaxial layer 6 and the p-GaN epitaxial layer 5 and the entire upper surface of the exposed spacer layer 4 (surface passivation film: oxide, nitride, 8) is deposited.

Here, the SPF thin film 8 may use a SiO ₂ dielectric thin film, and the thickness is adjusted to a level of 30 to 200 nm. The SPF thin film 8 stabilizes the surface to eliminate current collapse, and maintains Schottky contact characteristics.

The SPF thin film (8) for surface stabilization changes the unstable state of the WBG semiconductor surface while the electrical properties are in operation, so passivation on the interface and surface and passivation by thin film deposition are very important in manufacturing stable devices Do. Atomic bonds or traps present on the surface of the semiconductor cause a shape in which carriers are captured or released according to the voltage applied to the semiconductor, thereby changing the current density flowing through the device.

Then, as shown in FIG. 4, Si ⁺ , an n-type impurity, is ion-implanted into each part of the AlGaN spacer layer 4 and the n-GaN epitaxial layer 6 under a low energy condition of 10 to 30 keV. , ion implantation layers 9, 10 and 11 are formed.

Then, as shown in FIG. 5, a silicon nitride film (Si ₃ N ₄ , 12) is deposited on the entire surface of the upper surface of the SPF thin film 8, and the silicon nitride film 12 is used as a passivation at 900 to 1200 The ion implanted layers 9, 10 and 11 are activated by heat treatment at a high temperature of °C for 1 to 5 minutes.

At this time, the ion implantation layers 9, 10, and 11 are activated as the drain 9, the source 10, and the gate ion implantation layer 11, respectively. Substantially, the ion-implanted layers 9, 10, and 11 are functionally named as the drain 9, the source 10, and the gate ion-implanted layer 11, and are regarded as descriptions of the same reference numerals for the same configuration.

Then, as shown in FIG. 6, after the silicon nitride film 12 is removed, a pattern defining the ohmic junction is formed by photo-transfer to form an ohmic junction, and a part of the SPF thin film 8 is dry-processed. Etching to form an ohmic junction window.

The ohmic junction window exposes part or all of the upper portion of the drain 9 , the source 10 , and the gate ion implantation layer 11 .

At this time, in order to solve the problem of plasma-induced defects in the ohmic contact area, ICP (Inductive Coupled Plasma) dry etching and wet etching are combined and etched.

Then, as shown in FIG. 7, a metal thin film is deposited for an ohmic junction, and metal electrodes 13, 14, and 15 forming an ohmic junction are formed through an optical pre-transfer and etching process.

At this time, the metal electrode 13 is connected to the drain 9, the metal electrode 14 is connected to the source 10, and the metal electrode 15 is connected to the gate ion implantation layer 11. In particular, the metal electrode 15 connected to the gate ion implantation layer 11 extends toward the metal electrode 13 connected to the drain 9 to form a field plate.

The metal electrodes 13, 14, and 15 include a single layer of metal such as Ti, Ni, Al, Pt, Pd, Mo, or Ta or two or more composite layers such as Ti/TiN or Ti/Ni/Ti/Al. can be used The metal electrodes 13, 14, and 15 are subjected to rapid heat treatment at a high temperature of 800° C. or higher for 1 to 5 minutes to form an ohmic contact with low resistance.

In order to use Au as the metal electrodes 13, 14, and 15, a lift-off process may be used. Lithography for forming a PR pattern for lift-off is required, Au is deposited, and lift-off may be performed with a solvent solution.

By forming the metal electrodes 13, 14, and 15 by ohmic contact, contact resistance for minimizing heat generated when constant current flows can be reduced.

In addition, in order for the device to operate stably from electric shock and thermal shock, it is possible to provide a structure with low contact resistance and a physically stable electro-migration resistant structure.

Then, referring to FIG. 8, an interlayer insulating film 16 such as SiO ₂ is deposited and formed in the configuration of FIG. A pattern exposing upper portions of the metal electrodes 14 and 13 connected to is formed.

Next, to form the plugs 17 and 18 on the etched portion of the interlayer insulating film 16, tungsten is deposited and polished through a chemical mechanical polishing (CMP) process.

Then, a metal thin film having a thickness of 2 to 6 μm is deposited to form a pattern and etched to form metal pads 19 connected to the plugs 17 and 18, respectively.

At this time, the metal thin film may be used by combining various metal materials such as Ai, Ti/Al, Ni/Au, Ti/Al/Ni/Au in a single layer or multiple layers.

A lift-off process can also be used at this time.

The structure and operation of the power semiconductor device of the present invention manufactured as described above will be described in more detail below.

9 is a cross-sectional view of main parts of the power semiconductor device of the present invention.

Referring to FIG. 9, the power semiconductor device of the present invention includes an active layer 3 on which a 2DEG layer 7 is partially formed, a spacer layer 4 located on top of the active layer 3, and the spacer A gate located on a part of the upper portion of the layer 4, in which the p-GaN epitaxial layer 5 and the n-GaN epitaxial layer 6 are stacked, and a source formed on the spacer layer 4 below one side of the gate (10), a drain (9) located on the opposite side of the source (10) around the gate, but located in a part of the spacer layer (4) spaced apart from the gate, and the n-GaN epitaxial layer The drain ( 9), the source 10, and the gate ion implantation layer 11 are configured to include metal electrodes 13, 14, and 15 in ohmic contact, respectively.

FIG. 10 is a cross-sectional view showing resistance components between elements in the configuration of FIG. 9 .

The characteristic of the power semiconductor device of the present invention is that the gate is composed of a double layer of a p-GaN epitaxial layer 5 and an n-GaN epitaxial layer 6 to form an n-p-n junction structure.

According to the n-p-n junction structure, current flows through diffusion and recombination at the p-n junction to which reverse voltage is applied, and therefore, even when voltage is applied to the gate, most of the electric field exists at the n-p-n junction, and ohmic junction metal electrodes At the junction interface between the and the source, drain, and gate ion implantation layers, collisions by high-energy electrons are negligibly small.

Therefore, the problem of reliability deterioration due to the collision of high-energy carriers does not occur at the semiconductor-metal interface.

11 is a comparison diagram of bandgap characteristics of a conventional power semiconductor device using a p-GaN epitaxial layer as a gate and a power semiconductor device of the present invention using n-GaN and p-GaN epitaxial layers as a gate.

Figures 11 (a) and (c) show the conventional bandgap between a state in which no bias is applied to the gate and a state in which a bias is applied to the gate, and (b) and (d) of Fig. 11 show no bias applied to the gate of the present invention. The band gaps of the unapplied state and the applied state are respectively shown.

As shown, when a voltage is applied to the gate, which is in the Schottky junction state in the conventional structure, the p-GaN band structure is depleted and a high electric field exists at the semiconductor-metal interface.

During the transmission of the carrier, current flows while TE (Thermal emission) and QT (Quantum Tunneling) increase at the metal-semiconductor interface. In this case, electrons are accelerated while flowing from the channel to p-GaN, and severe physical collision occurs at the metal-semiconductor interface, resulting in damage, which reduces the reliability of the device.

This indicates that the high gate current and the instability of the metal-semiconductor interface in the conventional device structure using the p-GaN gate deteriorate the reliability.

However, as described above, the gate and the active region form an n-p-n junction, that is, p-GaN exists between the n-type gate and the n-type channel to form an n-p-n junction. In this case, current flows through diffusion and recombination at the p-n junction to which the reverse voltage is applied. Therefore, even when a voltage is applied to the gate, most of the electric field exists at the n-p-n junction, and collisions by high-energy electrons are negligible in the ohmic junction metal-semiconductor junction. there is no problem with

12 is an I-V characteristic graph of the power semiconductor device of the present invention and the conventional power semiconductor device.

As shown in FIG. 12 (a), the conventional power semiconductor device has a low threshold voltage, a large gate leakage current, and a gate driving voltage of about 6V or less.

That is, in the prior art, a simple p-n junction is formed with the 2DEG layer by using the p-GaN epitaxial layer alone as a gate, the threshold voltage is limited to 2.0V or less, and the gate driving voltage is also limited to 5 to 7V. Therefore, a specially designed driving circuit chip is required to drive such a conventional GaN power semiconductor device.

This has a problem in that compatibility is lowered because a gate driver using an existing CMOS cannot be used.

On the other hand, the I-V characteristic of the present invention shown in (b) of FIG. 12 is formed with an n-p-n junction to block the flow of current to a considerably high voltage in both directions to which voltage is applied, and at the same time raise the threshold voltage to 2.0V or more. do. Even if a high voltage is applied to the gate, the flow of current is small, so a high voltage of 10V or more can be applied to the gate, and thus the existing CMOS driving circuit can be used in common.

13 is a graph comparing current driving characteristics between the present invention and the prior art.

Referring to FIG. 13, the present invention can maximize the efficiency of the device with a small on-resistance (R _on ) in forward operation by increasing the current driving force by minimizing the resistive ohmic junction and the R _SG component. As such, the current driving capability of the device is 100 mA/mm or more, and the on-resistance (R _on ) is controlled to 5 mΩcm ² or less.

This decrease in on-resistance is due to a phenomenon in which the resistance is minimized by self-alignment by ion implantation between the source and the gate.

14 is a graph comparing conductance V characteristics of the present invention and the prior art.

Compared to the prior art, the present invention exhibits characteristics of high threshold voltage (V _th ) and transconductance (Gm). This threshold voltage is made possible by the gate-channel junction structure operating in an npn structure.

In addition, since the gate current is low even if the gate voltage is increased, the gate driving voltage can be increased up to 10V.

As described above, in the present invention, the high-mobility carrier of the 2DEG of the HEMT structure provides a cause for the operation of the device with high conduction at high frequency and high voltage. This increases the efficiency and reduces the size of the passive element in the circuit of the same class, thereby minimizing the volume of the high-power system. The performance and advantages of the device of the present invention can be said to be essential for high frequency-high power wireless circuits operating at high speed.

It is obvious to those skilled in the art that the present invention is not limited to the above embodiments and can be variously modified or modified and implemented within the scope of the technical gist of the present invention. will be.

1: semiconductor substrate 2: buffer layer
3: active layer 4: spacer layer
5: p-GaN epitaxial layer 6: n-GaN epitaxial layer
7: 2DEG layer 8: SPF thin film
9: Drain 10: Source
11: gate ion implantation layer 12: silicon nitride film
13, 14, 15: metal electrode

Claims (10)

an active layer 3 in which the 2DEG layer 7 is partially formed;
a spacer layer 4 located on top of the active layer 3;
a gate located on a part of the upper portion of the spacer layer 4 and having a p-GaN epitaxial layer 5 and an n-GaN epitaxial layer 6 stacked thereon;
an n-type source 10 formed on the spacer layer 4 below one side of the gate;
an n-type drain 9 positioned on the opposite side of the gate to the source 10 and positioned on a part of the spacer layer 4 spaced apart from the gate;
an SPF thin film (8) deposited on the entire surface of the gate and spacer layer (4); and
A power semiconductor device including two metal electrodes (13, 14) in ohmic contact with the drain (9) and the source (10) through a window formed in the SPF thin film (8). According to claim 1,
The power semiconductor device further comprises an n-type gate ion implantation layer (11) formed on a part of the n-GaN epitaxial layer (6). According to claim 2,
Further comprising a metal electrode 15 in ohmic contact with the gate ion implantation layer,
The metal electrode (15) extends toward the metal electrode (13) connected to the drain to form a field plate. According to claim 1,
The p-GaN epitaxial layer 5 is doped with a p-type impurity of 10 ¹⁷ to 10 ¹⁹ cm ^-3 ,
The n-GaN epitaxial layer 6 is doped with n-type impurities in a range of 10 ¹⁶ to 10 ¹⁸ cm ⁻³ . According to claim 1,
The SPF thin film 8 is a power semiconductor device, characterized in that a SiO ₂ dielectric thin film having a thickness of 30 to 200 nm. a) an AlGaN spacer layer 4 on top of the active layer 3, which is an undoped GaN layer, a p-GaN epitaxial layer 5 doped with p-type impurities, and an n-GaN epitaxial layer doped with n-type impurities Step of sequentially growing and patterning the layer 6 to form a gate composed of a stacked structure of a p-GaN epitaxial layer 5 and an n-GaN epitaxial layer 6 located on a portion of the upper portion of the spacer layer 4;
b) forming a source 10 and a drain 9 by implanting and activating n-type impurity ions into the spacer layer 4; and
c) Depositing an SPF thin film 8 on the product of step c), removing a portion of the SPF thin film to expose the source 10, drain 9, and gate, and then forming the source 10, drain ( 9) and forming metal electrodes (14, 13, 15) in ohmic contact with each of the gates. According to claim 6,
In step b),
The n-GaN epitaxial layer 6 is also implanted with n-type impurity ions and activated to form a gate ion implantation layer 11,
The method of manufacturing a power semiconductor device, characterized in that the metal electrode (15) is in ohmic contact with the gate ion implantation layer (11). According to claim 7,
The method of manufacturing a power semiconductor device, characterized in that the metal electrode (15) extends toward the metal electrode (13) in ohmic contact with the drain (9) to form a field plate. According to claim 6,
In step a),
The p-GaN epitaxial layer 5 is formed by growing GaN doped with a p-type impurity of 10 ¹⁷ to 10 ¹⁹ cm ⁻³ ,
A method of manufacturing a power semiconductor device, characterized in that the n-GaN epitaxial layer 6 is formed by growing GaN doped with n-type impurities in a range of 10 ¹⁶ to 10 ¹⁸ cm ⁻³ . According to claim 6,
In step c),
A method for manufacturing a power semiconductor device, characterized in that the SPF thin film (8) is formed by depositing a SiO ₂ dielectric thin film having a thickness of 30 to 200 nm.

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