KR20220089995A - Display apparatus - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, a plurality of light-emitting devices disposed on the plurality of sub-pixels and sharing an organic layer and a cathode, and a cathode between each of the plurality of light-emitting devices a bank disposed on , a plurality of wirings disposed between the bank and the substrate, and a first pattern disposed in the bank and overlapping at least one of the plurality of wirings, wherein the cathode is disposed in the first pattern. Accordingly, as the length of the cathode and the organic layer increases in the first pattern, the length of the path through which the leakage current flows may increase, and deterioration of display quality due to the leakage current may be minimized.

Description

display device {DISPLAY APPARATUS}

The present invention relates to a display device, and more particularly, to a display device capable of improving color mixing of light emitted from a plurality of light emitting devices.

As we enter the information age in earnest, the field of display devices that visually display electrical information signals is rapidly developing, and research to develop performance such as thinness, weight reduction, and low power consumption for various display devices is continuing.

Among these various display devices, an organic display device is a self-emission type display device, and unlike a liquid crystal display device, it does not require a separate light source, and thus can be manufactured in a lightweight and thin form. In addition, the organic display device is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent color realization, response speed, viewing angle, and contrast ratio (CR), and thus is being studied as a next-generation display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of minimizing leakage current when the display device is driven.

Another object of the present invention is to provide a display device in which emission of light due to leakage current from some light emitting devices among a plurality of light emitting devices having a common layer is minimized.

Another problem to be solved by the present invention is to provide a display device capable of improving image display quality in low grayscale.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment includes a substrate on which a plurality of sub-pixels are defined, a plurality of light emitting devices disposed on the plurality of sub-pixels, and a plurality of light emitting devices including an anode, an organic layer and a cathode, and between the plurality of sub-pixels at least one metal pattern disposed and a bank disposed between the metal pattern and the organic layer between each of the plurality of sub-pixels, wherein the plurality of light emitting devices share the organic layer and the cathode, and the metal pattern includes the sub-pixels adjacent to the metal pattern. is configured such that a voltage is applied during the light emission period of Accordingly, the metal pattern forms a capacitor by an applied voltage, and carriers of the leakage current are trapped by the formed capacitor, thereby minimizing display quality degradation due to the leakage current.

Details of other embodiments are included in the detailed description and drawings.

The present invention can improve current leakage through a common layer of a plurality of light emitting devices.

According to the present invention, color reproducibility can be improved by minimizing unintentional light emission from a light emitting device when driving a display device.

According to the present invention, it is possible to improve display quality by minimizing the recognition of spots or color abnormalities when displaying a low grayscale image.

According to the present invention, a luminance increase can be minimized when driving at a low gray level in a high-speed driving and high-resolution display device.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention.
2A is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment.
2B is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
3A is an enlarged plan view of a display device according to an exemplary embodiment.
3B is a cross-sectional view taken along line IIIb-IIIb' of FIG. 3A.
4 is a schematic cross-sectional view of a display device according to another exemplary embodiment.
5A is an enlarged plan view of a display device according to another exemplary embodiment.
5B is a cross-sectional view taken along Vb-Vb' of FIG. 5A.
6A is an enlarged plan view of a display device according to another exemplary embodiment.
6B is a cross-sectional view taken along VIb-VIb' of FIG. 6A.
7 is a schematic cross-sectional view of a display device according to still another exemplary embodiment.
8 is a schematic cross-sectional view of a display device according to another exemplary embodiment.
9A to 9D are graphs for explaining a leakage current in a display device according to a comparative example and another exemplary embodiment of the present invention.
10 is an enlarged plan view of a display device according to another exemplary embodiment.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'includes', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of the other device or layer.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention. In FIG. 1 , only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated among various components of the display device 100 for convenience of explanation.

Referring to FIG. 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN. , and a timing controller TC controlling the gate driver GD and the data driver DD.

The gate driver GD supplies the plurality of scan signals to the plurality of scan lines SL according to the plurality of gate control signals GCS provided from the timing controller TC. The plurality of scan signals may include a first scan signal SCAN1 and a second scan signal SCAN2, and the scan signal may include an emission control signal. In FIG. 1 , one gate driver GD is illustrated as being spaced apart from one side of the display panel PN, but the gate driver GD may be disposed in a GIP (Gate In Panel) method. The number and arrangement of GD) are not limited thereto.

The data driver DD converts the image data RGB input from the timing controller TC into a data signal using a reference gamma voltage according to a plurality of data control signals DCS provided from the timing controller TC. In addition, the data driver DD may supply the converted data signal to the plurality of data lines DL.

The timing controller TC aligns the image data RGB input from the outside and supplies it to the data driver DD. The timing controller TC generates a gate control signal GCS and a data control signal DCS using an externally input synchronization signal SYNC, for example, a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. can do. In addition, the timing controller TC supplies the generated gate control signal GCS and the data control signal DCS to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD. can be controlled

The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, the plurality of scan lines SL and the plurality of data lines DL cross each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power line PL, a low potential power line, an initialization signal line IL, a light emission control signal line EL, and the like.

The plurality of sub-pixels SP is a minimum unit constituting a screen, and each of the plurality of sub-pixels SP includes a light emitting device and a pixel circuit for driving the plurality of sub-pixels. The plurality of light emitting devices may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an organic light emitting display panel, the light emitting device includes an organic light emitting device including an anode, an organic layer, and a cathode. It may be a light emitting device. In addition, a quantum dot light-emitting diode (QLED) including a quantum dot (QD) may be further used as the light emitting device. Hereinafter, it is assumed that the light emitting device is an organic light emitting device, but the type of the light emitting device is not limited thereto.

The pixel circuit is a circuit for controlling the driving of the light emitting element. The pixel circuit may include, for example, a plurality of transistors and capacitors, but is not limited thereto.

Hereinafter, the pixel circuit of the sub-pixel SP will be described in more detail with reference to FIG. 2 .

2A is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment. 2B is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A , the pixel circuit of the plurality of sub-pixels SP includes a driving transistor DT, first to sixth transistors T1, T2, T3, T4, T5, and T6, and one capacitor Cst. may include

The light emitting element ED emits light by a driving current supplied from the driving transistor DT. The anode of the light emitting element ED may be electrically connected to the fourth node n4 , and the cathode of the light emitting element ED may be electrically connected to the input terminal of the base voltage EVSS corresponding to the low potential driving voltage.

The driving transistor DT controls the driving current applied to the light emitting device ED according to the gate-source voltage Vgs. The driving transistor DT may be, for example, a P-type transistor. In this case, the source electrode of the driving transistor DT may be connected to the first node n1 , the gate electrode may be connected to the second node n2 , and the drain electrode may be connected to the third node n3 .

The first transistor T1 may be electrically connected between the second node n2 and the third node n3 . That is, the first transistor T1 may be electrically connected between the gate electrode and the drain electrode of the driving transistor DT.

A drain electrode or a source electrode of the first transistor T1 may be electrically connected to the second node n2 , and a source electrode or a drain electrode of the first transistor T1 may be electrically connected to a third node n3 . . The gate electrode of the first transistor T1 may be electrically connected to the n-th scan line SL[N].

The first transistor T1 electrically connects the gate electrode and the drain electrode of the driving transistor DT in response to the n-th scan signal SCAN[N] applied through the n-th scan line SL[N]. can connect you Here, the electrical connection between the gate electrode and the drain electrode of the driving transistor DT may be referred to as a diode connection.

The second transistor T2 may be electrically connected between the data line DL and the first node n1 . That is, the second transistor T2 may be electrically connected to the data line DL and the source electrode of the driving transistor DT.

A drain electrode or a source electrode of the second transistor T2 may be electrically connected to the first node n1 , and a source electrode or a drain electrode of the second transistor T2 may be electrically connected to the data line DL. The gate electrode of the second transistor T2 may be electrically connected to the n-th scan line SL[N].

The second transistor T2 receives the data voltage Vdata supplied from the data line DL in response to the nth scan signal SCAN[N] supplied through the nth scan line SL[N]. It can be transmitted to the first node n1.

The gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 may be commonly connected to the same n-th scan line SL[N]. Accordingly, the first transistor T1 and the second transistor T2 may be turned on and off together.

The third transistor T3 may be electrically connected between the driving voltage line DVL and the first node n1 . That is, the third transistor T3 may be electrically connected between the driving voltage line DVL and the source electrode of the driving transistor DT.

A source electrode or a drain electrode of the third transistor T3 may be electrically connected to the driving voltage line DVL, and a drain electrode or a source electrode of the third transistor T3 may be electrically connected to the first node n1 . . A gate electrode of the third transistor T3 may be electrically connected to the emission control line EML.

The third transistor T3 may transmit the high potential driving voltage EVDD to the first node n1 in response to the emission control signal EM supplied through the emission control line EML.

The fourth transistor T4 may be electrically connected between the third node n3 and the fourth node n4 . That is, the fourth transistor T4 may be electrically connected between the drain electrode of the driving transistor DT and the anode of the light emitting device ED.

A source electrode or a drain electrode of the fourth transistor T4 may be electrically connected to the third node n3 , and a drain electrode or a source electrode of the fourth transistor T4 may be electrically connected to the fourth node n4 . . The gate electrode of the fourth transistor T4 may be electrically connected to the emission control line EML.

The fourth transistor T4 forms a current path between the third node n3 and the fourth node n4 in response to the emission control signal EM supplied through the emission control line EML.

The gate electrode of the third transistor T3 and the gate electrode of the fourth transistor T4 may be commonly connected to the same emission control line EML. Accordingly, the third transistor T3 and the fourth transistor T4 may be turned on and off together.

The fifth transistor T5 may be electrically connected between the second node n2 and the initialization voltage line VIL. That is, the fifth transistor T5 may be electrically connected between the gate electrode of the driving transistor DT and the initialization voltage line VIL.

A source electrode or a drain electrode of the fifth transistor T5 may be electrically connected to the initialization voltage line VIL, and a drain electrode or a source electrode of the fifth transistor T5 may be electrically connected to the second node n2 . . The gate electrode of the fifth transistor T5 may be electrically connected to the (n−1)th scan line SL[N−1].

The fifth transistor T5 responds to the (n−1)th scan signal SCAN[N−1] supplied through the (n−1)th scan line SL[N−1] to the initialization voltage Vini ) to the second node n2.

The sixth transistor T6 may be electrically connected between the initialization voltage line VIL and the fourth node n4 . That is, the sixth transistor T6 may be electrically connected between the initialization voltage line VIL and the anode electrode of the light emitting device ED.

A source electrode or a drain electrode of the sixth transistor T6 may be electrically connected to the initialization voltage line VIL, and a drain electrode or a source electrode of the sixth transistor T6 may be electrically connected to the fourth node n4 . . The gate electrode of the sixth transistor T6 may be electrically connected to the n-th scan line SL[N].

The sixth transistor T6 may transmit the initialization voltage Vini to the fourth node n4 in response to the n-th scan signal SCAN[N] supplied through the n-th scan line SL[N]. have.

The first to sixth transistors T1 to T6 are a type of switching transistor. The storage capacitor Cst may include a first plate electrically connected to the second node n2 and a second plate electrically connected to the driving voltage line DVL.

In the example of FIG. 2A , seven transistors are illustrated as P-type transistors, but for convenience of description, all seven transistors may be N-type transistors, and some of the seven transistors are P-type transistors, and some of the seven transistors are P-type transistors. may be an N-type transistor.

Each sub-pixel structure illustrated in FIG. 2A is only an example for description, and may be transformed into various forms (eg, 4T1C, 4T2C, 6T1C, 6T2C, 8T1C, etc.) including two or more transistors and one or more capacitors. can Alternatively, each of the plurality of sub-pixels may have the same structure, and some of the plurality of sub-pixels may have a different structure.

Referring to FIG. 2B , the driving period of each sub-pixel SP may include an initialization period S10, a writing/sensing period S20, and an emission period S30. can During the initialization period S10, among the n-1 th scan signal SCAN[N-1], the n-th scan signal SCAN[N], and the emission control signal EM, the n-1 th scan signal SCAN[ N-1]) only has a turn-on level voltage. Accordingly, during the initialization period S10 , the fifth transistor T5 is turned on. The remaining transistors DT, T1, T2, T3, T4, and T6 are in an off state.

Accordingly, the initialization voltage Vini is applied to the second node n2. That is, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. During the writing/sensing period S20, among the n-1 th scan signal SCAN[N-1], the n-th scan signal SCAN[N], and the emission control signal EM, the n-th scan signal SCAN[ N]) only has a turn-on level voltage. During the write/sensing period S20 , the first and second transistors T1 and T2 and the sixth transistor T6 are turned on. The remaining transistors T3, T4, and T5 are in an off state.

During the write/sensing period S20 , the initialization voltage Vini may be applied to the anode of the light emitting device ED corresponding to the fourth node n4 according to the turn-on of the sixth transistor T6 . Also, during the write/sensing period S20 , according to the turn-on of the first transistor T1 , the gate electrode and the drain electrode of the driving transistor DT may be electrically connected to each other. This state of the driving transistor DT is referred to as a diode connection state.

During the write/sensing period S20 , the driving transistor DT operates like a diode by diode connection. As the second transistor T2 is turned on, the data voltage Vdata applied to the source electrode of the driving transistor DT is transferred to the gate electrode through the diode connection. Accordingly, the voltage of the gate electrode (corresponding to n2 ) of the driving transistor DT has the data voltage Vdata-|Vth| for which the threshold voltage Vth is compensated.

Here, since the driving transistor DT is a P-type transistor, the threshold voltage Vth of the driving transistor DT may have a negative value.

Accordingly, the voltage of the gate electrode (corresponding to n2) of the driving transistor DT becomes Vdata+Vth (=Vdata-|Vth|=Vdata-(-Vth)=Vdata+Vth). Accordingly, the voltage of the gate electrode (corresponding to n2) of the driving transistor DT becomes Vdata+Vth (=Vdata-|Vth|=Vdata-(-Vth)=Vdata+Vth).

During the emission period S30, among the n-1 th scan signal SCAN[N-1], the n-th scan signal SCAN[N], and the emission control signal EM, which are the first type of scan signals, emission control is performed. Only the signal EM has a turn-on level voltage. Accordingly, during the light emission period S30 , the third and fourth transistors T3 and T4 are turned on. In addition, the driving transistor DT is also turned on. The remaining transistors T1, T2, T5, and T6 are in an off state.

A driving current path is formed from the driving voltage line DVL to the light emitting device ED by the third transistor T3 , the driving transistor DT and the fourth transistor T4 in the turned-on state. Accordingly, the light emitting element ED emits light.

Hereinafter, the sub-pixel SP of the display device 100 according to an exemplary embodiment will be described in more detail with reference to FIGS. 3A and 3B .

3A is an enlarged plan view of a display device according to an exemplary embodiment. 3B is a cross-sectional view taken along line IIIb-IIIb' of FIG. 3A. 3A and 3B , the display device 100 according to an embodiment of the present invention includes a substrate 110 , a buffer layer 111 , a gate insulating layer 112 , an interlayer insulating layer 113 , and a passivation layer ( 114 ), a planarization layer 115 , a bank 116 , a fourth transistor T4 , a light emitting device ED, and a metal pattern 140 . In FIG. 3A , only the anode ANO among the components disposed in the sub-pixel SP is illustrated for convenience of explanation. In FIG. 3B , only the fourth transistor T4 among the plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and DT and the capacitor Cst of the pixel circuit is illustrated for convenience of description.

Referring to FIG. 3A , each of the plurality of sub-pixels SP is an individual unit emitting light, and a light emitting device ED is disposed in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP includes a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 may be a blue sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a red sub-pixel.

The plurality of first sub-pixels SP1 may be arranged in a plurality of columns. That is, the plurality of first sub-pixels SP1 may be arranged in the same column. In addition, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be disposed between each of the plurality of columns in which the plurality of first sub-pixels SP1 are disposed. For example, the plurality of first sub-pixels SP1 may be disposed in one column, and the second sub-pixel SP2 and the third sub-pixel SP3 may be disposed together in an adjacent column. In addition, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be alternately disposed in the same column. However, in the present specification, the plurality of sub-pixels SP has been described as including the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , but the plurality of sub-pixels SP The arrangement, number, and color combination of the elements may be variously changed depending on the design, but is not limited thereto.

At least one metal pattern 140 is disposed between the plurality of sub-pixels SP. The metal pattern 140 may be configured such that a voltage is applied during the light emission period S30 of the sub-pixel adjacent to the metal pattern 140 .

The metal pattern 140 is a portion extending in the column direction between the plurality of sub-pixels SP. The metal pattern 140 may be a portion extending in the column direction between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3 .

The leakage current from the plurality of light emitting devices ED may be minimized by the at least one metal pattern 140 disposed between the plurality of sub-pixels SP, which will be described in more detail with reference to FIG. 3B . do.

Referring to FIG. 3B , the substrate 110 is a support member for supporting other components of the display device 100 , and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. In addition, the substrate 110 may include a polymer or plastic such as polyimide (PI), or may be made of a material having flexibility.

A buffer layer 111 is disposed on the substrate 110 . The buffer layer 111 may reduce penetration of moisture or impurities through the substrate 110 . The buffer layer 111 may be formed of, for example, a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of the substrate 110 or the type of the transistor, but is not limited thereto.

A fourth transistor T4 is disposed on the buffer layer 111 . The fourth transistor T4 includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the active layer ACT is formed of an oxide semiconductor, the active layer ACT includes a channel region, a source region, and a drain region, and the source region and the drain region may be a conductive region, but is limited thereto. doesn't happen

A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT and the gate electrode GE, and may be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is limited thereto. doesn't happen

A gate electrode GE is disposed on the gate insulating layer 112 . The gate electrode GE may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, it is not limited thereto.

An interlayer insulating layer 113 is disposed on the gate electrode GE. A contact hole for connecting the source electrode SE and the drain electrode DE to the active layer ACT is formed in the interlayer insulating layer 113 . The interlayer insulating layer 113 may be formed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode SE and a drain electrode DE are disposed on the interlayer insulating layer 113 . The source electrode SE and the drain electrode DE disposed to be spaced apart from each other may be electrically connected to the active layer ACT. The source electrode SE and the drain electrode DE may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or the like. It may be composed of an alloy for, but is not limited thereto.

A passivation layer 114 is disposed on the source electrode SE and the drain electrode DE. The passivation layer 114 is an insulating layer for protecting the structure under the passivation layer 114 . For example, the passivation layer 114 may be formed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 114 may be omitted according to embodiments.

A planarization layer 115 is disposed on the passivation layer 114 . The planarization layer 115 is an insulating layer that planarizes an upper portion of the substrate 110 . The planarization layer 115 may be made of an organic material, for example, may be formed of a single layer or a multilayer of polyimide or photo acryl, but is not limited thereto.

A plurality of light emitting devices ED are disposed in each of the plurality of sub-pixels SP on the planarization layer 115 . The light emitting device ED includes an anode ANO, an organic layer 120 and a cathode CAT.

An anode ANO is disposed on the planarization layer 115 . The anode ANO may be electrically connected to a transistor of the pixel circuit, for example, the second transistor T2 and the fifth transistor T5 to receive a driving current. Since the anode ANO supplies holes to the organic layer 120 , it may be made of a conductive material having a high work function. The anode ANO may be formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

Meanwhile, the display device 100 may be implemented in a top emission method or a bottom emission method. In the case of the top emission method, a metal material having excellent reflection efficiency is provided under the anode ANO so that light emitted from the organic layer 120 is reflected by the anode ANO and is directed upward, that is, toward the cathode CAT side. , for example, a reflective layer made of a material such as aluminum (Al) or silver (Ag) may be added. Conversely, when the display device 100 is a bottom emission type, the anode ANO may be formed of only a transparent conductive material. Hereinafter, it is assumed that the display device 100 according to an embodiment of the present invention is a top emission type.

A bank 116 is disposed on the anode ANO and the planarization layer 115 . The bank 116 is an insulating layer disposed between the plurality of sub-pixels SP to separate the plurality of sub-pixels SP. The bank 116 includes an opening exposing a portion of the anode ANO. The bank 116 may be formed of an organic insulating material disposed to cover an edge or an edge portion of the anode ANO. The bank 116 may be made of, for example, polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

The organic layer 120 is disposed on the anode ANO and the bank 116 . The organic layer 120 includes an emission layer 123 and common layers 121 , 122 , and 124 . The emission layer 123 is an organic layer for emitting light of a specific color, in which different emission layers 123 are disposed in each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . may be For example, a blue emission layer may be disposed on the first sub-pixel SP1 , a green emission layer may be disposed on the second sub-pixel SP2 , and a red emission layer may be disposed on the third sub-pixel SP3 .

In addition, a plurality of light-emitting layers emitting light of the same color may be stacked on one sub-pixel. For example, two blue light-emitting layers are stacked on the first sub-pixel SP1 , two green light-emitting layers are stacked on the second sub-pixel SP2 , and two red light-emitting layers are disposed on the third sub-pixel SP3 . can be In this case, a charge generation layer (CGL) may be disposed between each of the plurality of light emitting layers to smoothly supply electrons or holes to each of the plurality of light emitting layers. That is, the charge generation layer may be disposed between the two blue light emitting layers, between the two green light emitting layers, and between the two red light emitting layers.

The common layers 121 , 122 , and 124 are layers disposed to improve the luminous efficiency of the light emitting layer 123 . The common layers 121 , 122 , and 124 may be formed as one layer over the plurality of sub-pixels SP, so that the plurality of light emitting devices ED may be shared with each other. That is, the common layers 121 , 122 , and 124 of each of the plurality of sub-pixels SP may be connected to each other and formed integrally. The common layers 121 , 122 , and 124 may include, but are not limited to, a hole injection layer 121 , a hole transport layer 122 , an electron transport layer 124 , and the like.

A cathode CAT is disposed on the organic layer 120 . Since the cathode CAT supplies electrons to the organic layer 120 , it may be formed of a conductive material having a low work function. The cathode CAT may be formed as one layer across the plurality of sub-pixels SP. That is, the cathodes CAT of each of the plurality of sub-pixels SP may be connected to each other and formed integrally. The cathode (CAT) is formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal alloy such as MgAg or a ytterbium (Yb) alloy. and may further include a metal doped layer, but is not limited thereto. Meanwhile, although not shown in the drawings, the cathode CAT may be electrically connected to the low potential power wiring to receive the low potential power signal EVSS.

A metal pattern 140 is disposed under the bank 116 . The metal pattern 140 may be disposed on the same layer as the plurality of anodes ANO between the plurality of light emitting devices ED disposed in the plurality of sub-pixels SP. The metal pattern 140 may be configured in the form of an independent wiring.

The metal pattern 140 may be configured such that a voltage is applied during the light emission period S30 of the sub-pixel adjacent to the metal pattern 140 . For example, the metal pattern 140 is configured such that a DC voltage is applied during the emission period S30 of the first sub-pixel SP1 adjacent to the metal pattern 140 , and during the emission period ( S30 ) of the first sub-pixel SP1 . During the initialization period ( S10 ) and the writing/sensing period ( S20 ), which are periods excluding S30 ), it may be floated.

Meanwhile, the common layers 121 , 122 , and 124 of the plurality of light emitting devices ED are formed as a single layer over the entire plurality of sub-pixels SP. In this case, since the light emitting device ED of the plurality of sub-pixels SP is formed in a structure that shares the common layers 121 , 122 , and 124 , when the light emitting device ED of a specific sub-pixel SP emits light A phenomenon in which current flows to the light emitting element ED of the adjacent sub-pixel SP, that is, a current leakage phenomenon may occur. The current leakage phenomenon may cause the light emitting device ED of another sub-pixel SP to emit light, which may cause color mixing between the plurality of sub-pixels SP and increase power consumption. In addition, color abnormality and unevenness may be visually recognized due to leakage current, and thus display quality may be deteriorated. For example, when only the first sub-pixel SP1 among the plurality of sub-pixels SP emits light, some of the current supplied to drive the light-emitting device ED of the first sub-pixel SP1 is transferred to the common layer ( The second sub-pixel SP2 and the third sub-pixel SP3 may leak through 121 , 122 , and 124 .

In addition, the light-emitting layers 123 arranged separately for each of the plurality of sub-pixels SP have different turn-on voltages. For example, the turn-on voltage for driving the first sub-pixel SP1 on which the blue emission layer is disposed is the largest, and the turn-on voltage for driving the third sub-pixel SP3 on which the red emission layer is disposed is the highest. can be small In addition, since the barrier through which a current can flow is lower in the second sub-pixel SP2 or the third sub-pixel SP3 having a smaller turn-on voltage than the first sub-pixel SP1 having the largest turn-on voltage, the common layer The current leaked through 121 , 122 , and 124 easily flows from the first sub-pixel SP1 having a large turn-on voltage to the second sub-pixel SP2 and the third sub-pixel SP3 having a low turn-on voltage. flow, and when the first sub-pixel SP1 is driven, the second sub-pixel SP2 and the third sub-pixel SP3 having a small turn-on voltage may emit light together.

In particular, during low grayscale driving, the luminance of light emitted from the driven sub-pixel SP is low, so that the light emitted from the neighboring sub-pixel SP can be more easily recognized. That is, when the low gray level is driven, color abnormalities and unevenness due to leakage current may be more easily recognized, and thus display quality may be seriously deteriorated. In addition, when displaying low grayscale white light, the third sub-pixel SP3 having the lowest turn-on voltage through the common layers 121 , 122 , and 124 emits light first, so that the light is first emitted from a red color instead of a pure white light. A redish phenomenon in which white with light is displayed may occur.

Accordingly, in the display device 100 according to an embodiment of the present invention, the metal pattern 140 is disposed to minimize leakage current through the common layers 121 , 122 , and 124 of the light emitting device ED. 2B and 3B , a light emission control signal EM is applied to the metal pattern 140 and a voltage is applied to the anode ANO during the light emission period S30 in which the light emitting element ED emits light. ) and a DC voltage may be applied to the adjacent metal pattern 140 . Accordingly, carriers of leakage current may be trapped by the capacitor formed between the metal pattern 140 and the cathode CAT during the light emission period S30 . Specifically, the metal pattern 140 to which the DC voltage is applied during the light emission period S30 may form a capacitor with the cathode CAT. In addition, carriers of leakage current flowing to the neighboring sub-pixels SP are trapped by the capacitor formed between the cathode CAT and the metal pattern 140 , so that the leakage current flowing to the neighboring sub-pixels SP can be minimized.

Meanwhile, in the display device 100 according to an embodiment of the present invention, the metal pattern 140 is floated during the initialization period S10 and the writing/sensing period S20 to solve the luminance lift phenomenon during black driving or low gray scale driving. can For example, when a voltage is applied to the metal pattern 140 even during the initialization period S10 and the writing/sensing period S20 , the metal pattern 140 and various transistors under the metal pattern 140 , for example For example, a parasitic capacitance may be generated between the driving transistor and the first to sixth transistors. As such, when the parasitic capacitance is generated, the voltage charge amount of the transistors may be reduced. For example, when the parasitic capacitance between the metal pattern 140 and the gate electrode of the driving transistor increases, the voltage charge of the gate electrode of the driving transistor decreases. In this case, the luminance increases during black driving or low gray scale driving, and thus a luminance lift phenomenon may occur. In particular, in the case of a high-speed driving or high-resolution display device in which a voltage charging time is limited, the luminance excitation phenomenon may be further exacerbated. Accordingly, in the display device 100 according to an embodiment of the present invention, the metal pattern 140 is floated during the initialization period S10 and the writing/sensing period S20 to reduce parasitic capacitance between the metal pattern 140 and the transistors. It is possible to reduce the luminance, and it is possible to suppress a luminance lift phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

Meanwhile, refer to [Table 1] below in order to explain the effect related to the luminance lift phenomenon in which the luminance increases during black driving or low gray scale driving.

I _oled comparative example 33.12 pA Example 21.26 pA

The embodiment is a display device according to an embodiment of the present invention, and a voltage corresponding to the high potential driving voltage EVDD is applied to the metal pattern during the light emission period S30 . In the comparative example, a voltage corresponding to the high potential driving voltage EVDD was applied to the metal pattern not only during the light emission period S30 but also during the initialization period S10 and the writing/sensing period S20 . [Table 1] shows the measurement of the driving current _Ioled flowing through the light emitting device of the first sub-pixel during low grayscale driving.

Referring to [Table 1], the driving current (I _oled ) is increased by 11.86 pA in the comparative example compared to the embodiment. In general, since the size of the driving current I _oled required per 1 nit is about 16.578 pA, the luminance excitation phenomenon occurs in the comparative example, in which the luminance is increased by about 1 nit than in the embodiment. However, in the embodiment, the metal pattern may be floated during the initialization period S10 and the writing/sensing period S20 to prevent the luminance lifting phenomenon in which the luminance increases during low grayscale driving.

4 is a cross-sectional view of a display device according to another exemplary embodiment. Compared to the display device 100 of FIGS. 1 to 3B , the display device 200 of FIG. 4 has only a metal pattern 240 different from that of the display device 100 of FIGS. 1 to 3B , and other configurations are substantially the same, so a redundant description will be omitted.

Referring to FIG. 4 , in the display device 200 according to another embodiment of the present invention, a metal pattern 240 is disposed under the bank 116 . The metal pattern 240 may be disposed on the same layer as the plurality of anodes ANO between the plurality of light emitting devices ED disposed in the plurality of sub-pixels SP. The metal pattern 240 may be configured in the form of an independent wiring.

The metal pattern 240 may be thicker than the thickness of the anode ANO. The metal pattern 240 may be formed of a material different from that of the anode ANO by a different process, and thus the metal pattern 240 may be formed to be thicker than the thickness of the anode ANO. In this case, since the bank 116 disposed on the metal pattern 240 is formed of an organic insulating material, the top surface of the bank 116 in the area where the metal pattern 240 is disposed and the area around the metal pattern 240 may be flat. can

The metal pattern 240 may be configured such that a voltage is applied during the light emission period S30 of the sub-pixel adjacent to the metal pattern 240 . For example, the metal pattern 240 is configured such that a DC voltage is applied during the emission period S30 of the first sub-pixel SP1 adjacent to the metal pattern 240 , and during the emission period ( S30 ) of the first sub-pixel SP1 . During the initialization period ( S10 ) and the writing/sensing period ( S20 ), which are periods excluding S30 ), it may be floated.

Accordingly, in the display device 200 according to another embodiment of the present invention, the metal pattern 240 is disposed to minimize leakage current through the common layers 121 , 122 , and 124 of the light emitting device ED. A DC voltage may be applied to the metal pattern 240 adjacent to the anode ANO during the light emission period S30 . Accordingly, carriers of leakage current may be trapped by the capacitor formed between the metal pattern 240 and the cathode CAT during the light emission period S30 . When the distance between the metal pattern 240 and the cathode CAT is reduced by making the thickness of the metal pattern 240 thicker than the anode ANO, the capacitance between the metal pattern 240 and the cathode CAT increases, resulting in more leakage current may be trapped between the metal pattern 240 and the cathode CAT. Accordingly, in the display device 200 according to another embodiment of the present invention, the leakage current flowing to the adjacent sub-pixel SP by the capacitor formed between the cathode CAT and the metal pattern 240 may be minimized.

In addition, in the display device 200 according to another embodiment of the present invention, the metal pattern 240 is floated during the initialization period S10 and the writing/sensing period S20 to reduce parasitic capacitance between the metal pattern 240 and the transistors. It is possible to reduce the luminance, and it is possible to suppress a luminance lift phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

5A is an enlarged plan view of a display device according to another exemplary embodiment. 5B is a cross-sectional view taken along Vb-Vb' of FIG. 5A. The display device 300 of FIGS. 5A and 5B has only a metal pattern 340 different from that of the display device 100 of FIGS. 1 to 3B , and other configurations are substantially the same, so a redundant description will be omitted.

5A and 5B , in the display device 300 according to another embodiment of the present invention, a metal pattern 340 is disposed under the bank 116 . The metal pattern 340 may be disposed on the same layer as the plurality of anodes ANO between the plurality of light emitting devices ED disposed in the plurality of sub-pixels SP. In this case, the metal pattern 340 may be connected to the anode ANO. That is, the metal pattern 340 may be formed of the same material as the anode ANO at the same time, and the anode ANO may have an extended shape. The metal pattern 340 may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 , and between the first sub-pixel SP1 and the third sub-pixel SP3 .

The metal pattern 340 may be connected to the anode ANO of the first sub-pixel SP1 . That is, the metal pattern 340 may be connected to the anode ANO of the first sub-pixel SP1 which is a sub-pixel having the largest turn-on voltage among the plurality of sub-pixels.

Accordingly, the metal pattern 340 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied. Specifically, the metal pattern 340 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied during the emission period S30 of the first sub-pixel SP1 . For example, the metal pattern 340 is configured such that a DC voltage equal to the DC voltage applied to the anode ANO is applied during the light emission period S30 of the first sub-pixel SP1, and the first sub-pixel SP1 During the initialization period S10 and the writing/sensing period S20 , which are periods excluding the light emission period S30 of , the anode may be floated in the same manner as the anode ANO.

Accordingly, in the display device 300 according to another exemplary embodiment of the present invention, the metal pattern 340 connected to the anode of the first sub-pixel SP1 having the largest turn-on voltage is disposed to provide a common feature of the light emitting device ED. Leakage current through layers 121 , 122 , 124 may be minimized. In general, a leakage current flows from a sub-pixel having a relatively high turn-on voltage to a sub-pixel having a relatively low turn-on voltage, so that the sub-pixel having a relatively low turn-on voltage emits light. For example, during the light emission period of the first sub-pixel SP1 having a relatively high turn-on voltage, the second sub-pixel (SP1) having a relatively low turn-on voltage due to leakage current from the first sub-pixel SP1 SP2) or the third sub-pixel SP3 may emit light. Accordingly, in the display device 300 according to another embodiment of the present invention, a DC voltage may be applied to the metal pattern 340 connected to the anode ANO of the first sub-pixel SP1 during the light emission period S30 . . Accordingly, carriers of the leakage current from the first sub-pixel SP1 may be trapped by the capacitor formed between the metal pattern 340 and the cathode CAT during the emission period S30 of the first sub-pixel SP1 . Accordingly, in the display device 300 according to another exemplary embodiment of the present invention, from the first sub-pixel SP1 having a relatively high turn-on voltage to the second sub-pixel SP2 or the second sub-pixel SP2 having a relatively low turn-on voltage A leakage current flowing to the third sub-pixel SP3 may be minimized.

In addition, in the display device 300 according to another embodiment of the present invention, the metal pattern 340 is floated during the initialization period S10 and the write/sensing period S20 to generate parasitic capacitance between the metal pattern 340 and transistors. can be reduced, and it is possible to suppress a luminance lifting phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

Meanwhile, although the metal pattern 340 is illustrated as being connected to the anode ANO of the first sub-pixel SP1 in FIGS. 5A and 5B , a plurality of metal patterns 340 are provided, and some metal patterns 340 are It may be disposed to be connected to the anode ANO of the second sub-pixel SP2 , and some other metal patterns 340 may be disposed to be connected to the anode ANO of the third sub-pixel SP3 . Accordingly, leakage currents from all sub-pixels may be minimized through the metal pattern 340 .

6A is an enlarged plan view of a display device according to another exemplary embodiment. 6B is a cross-sectional view taken along VIb-VIb' of FIG. 6A. Compared to the display device 300 of FIGS. 5A and 5B , the display device 400 of FIGS. 6A and 6B only has a different metal pattern 440 , and other configurations are substantially the same, so a redundant description will be omitted.

5A and 5B , in the display device 300 according to another embodiment of the present invention, a metal pattern 340 is disposed under the bank 116 . The metal pattern 340 may be disposed on the same layer as the plurality of anodes ANO between the plurality of light emitting devices ED disposed in the plurality of sub-pixels SP. In this case, the metal pattern 340 may be connected to the anode ANO. That is, the metal pattern 340 may be formed of the same material as the anode ANO at the same time, and the anode ANO may have an extended shape.

The metal pattern 340 may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 , and between the first sub-pixel SP1 and the third sub-pixel SP3 . In this case, two metal patterns 340 may be disposed between two sub-pixels adjacent to each other. That is, as shown in FIGS. 6A and 6B , between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3 in cross-section, respectively, as shown in FIGS. 6A and 6B , respectively. Two metal patterns 340 may be disposed. However, the number of the metal patterns 340 is not limited thereto, and may be three or more.

The metal pattern 340 may be connected to the anode ANO of the first sub-pixel SP1 . That is, the metal pattern 340 may be connected to the anode ANO of the first sub-pixel SP1 which is a sub-pixel having the largest turn-on voltage among the plurality of sub-pixels. Accordingly, the metal pattern 340 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied. Specifically, the metal pattern 340 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied during the emission period S30 of the first sub-pixel SP1 .

Accordingly, in the display device 300 according to another embodiment of the present invention, the plurality of metal patterns 340 connected to the anode ANO of the first sub-pixel SP1 having the largest turn-on voltage are formed to be adjacent to each other. By disposing between the pixels, leakage current through the common layers 121 , 122 , and 124 of the light emitting device ED may be minimized. That is, during the emission period S30 , a plurality of metal patterns 340 to which the same DC voltage as that of the anode ANO of the first sub-pixel SP1 is applied may be disposed between adjacent sub-pixels. Accordingly, in the display device 300 according to another exemplary embodiment of the present invention, the capacitance between the cathode CAT and the metal pattern 340 is increased, so that the first sub-pixel SP1 having a relatively large turn-on voltage is increased. Therefore, a leakage current flowing into the second sub-pixel SP2 or the third sub-pixel SP3 having a low turn-on voltage may be minimized.

In addition, in the display device 300 according to another embodiment of the present invention, the metal pattern 340 is floated during the initialization period S10 and the write/sensing period S20 to generate parasitic capacitance between the metal pattern 340 and transistors. can be reduced, and it is possible to suppress a luminance lifting phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

7 is a schematic cross-sectional view of a display device according to still another exemplary embodiment. The display device 500 of FIG. 7 is different from the display device 400 of FIGS. 6A and 6B only in the bank 116 and the metal pattern 540 , and other configurations are substantially the same, so a redundant description will be omitted. .

Referring to FIG. 7 , in the display device 500 according to another embodiment of the present invention, a metal pattern 540 is disposed under the bank 116 . The metal pattern 540 may be disposed on the same layer as the plurality of anodes ANO between the plurality of light emitting devices ED disposed in the plurality of sub-pixels SP. In this case, the metal pattern 540 may be connected to the anode ANO. That is, the metal pattern 540 may have an extended anode ANO.

The metal pattern 540 may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 , and between the first sub-pixel SP1 and the third sub-pixel SP3 . In this case, two metal patterns 540 may be disposed between two sub-pixels adjacent to each other.

The metal pattern 540 may be thicker than the thickness of the anode ANO. For example, the metal pattern 540 may be formed of a plurality of layers, of which some layers are formed of the same material in the same process as the anode (ANO), and other partial layers may be formed through a process such as separate deposition. have. Alternatively, although the anode ANO and the metal pattern 540 are formed in the same process, a thickness deviation between the anode ANO and the metal pattern 540 may be generated by using a halftone mask or the like. At this time, since the bank 116 disposed on the metal pattern 540 is formed of an organic insulating material, the top surface of the bank 116 in the area where the metal pattern 540 is disposed and the area around the metal pattern 540 may be flat. can

The metal pattern 540 may be connected to the anode ANO of the first sub-pixel SP1 . That is, the metal pattern 540 may be connected to the anode ANO of the first sub-pixel SP1 which is a sub-pixel having the largest turn-on voltage among the plurality of sub-pixels. Accordingly, the metal pattern 540 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied. Specifically, the metal pattern 540 may be configured such that the same voltage as that of the anode ANO of the first sub-pixel SP1 is applied during the emission period S30 of the first sub-pixel SP1 .

Accordingly, in the display device 500 according to another embodiment of the present invention, the plurality of metal patterns 540 connected to the anode ANO of the first sub-pixel SP1 having the largest turn-on voltage are formed to be thick with each other. It is disposed between adjacent sub-pixels to minimize leakage current through the common layers 121 , 122 , and 124 of the light emitting device ED. That is, during the light emission period S30 , a plurality of metal patterns 540 to which the same DC voltage as that of the anode ANO of the first sub-pixel SP1 is applied may be disposed between the sub-pixels adjacent to each other, and the metal pattern ( The distance between the 540 and the cathode CAT may be reduced. Accordingly, in the display device 500 according to another embodiment of the present invention, the capacitance between the cathode CAT and the metal pattern 540 is increased, so that the first sub-pixel SP1 has a relatively large turn-on voltage. Therefore, a leakage current flowing into the second sub-pixel SP2 or the third sub-pixel SP3 having a low turn-on voltage may be minimized.

In addition, in the display device 500 according to another embodiment of the present invention, the metal pattern 540 is floated during the initialization period S10 and the writing/sensing period S20 to generate parasitic capacitance between the metal pattern 540 and transistors. can be reduced, and it is possible to suppress a luminance lifting phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

8 is a schematic cross-sectional view of a display device according to another exemplary embodiment. Compared to the display device 500 of FIG. 7 , the display device 600 of FIG. 8 differs only in the bank 616 , the common layers 621 , 622 , 624 , and the cathode CAT, and other configurations are substantially the same. Therefore, redundant description is omitted.

Referring to FIG. 8 , a trench may be formed in the bank 616 disposed between the two metal patterns 540 . That is, the bank 616 will be formed such that the thickness of the bank 616 disposed between the two metal patterns 540 is smaller than the thickness of the bank 616 disposed between the metal pattern 540 and the anode ANO. can

The common layers 621 , 622 , and 624 and the cathode CAT disposed on the bank 616 may be disposed along the shape of the top surface of the bank 616 . Accordingly, the common layers 621 , 622 , and 624 are disposed along the trench shape of the bank 616 , and the length of the common layers 621 , 622 , and 624 is increased compared to the case where the top surface of the bank 616 is planarized. can do. In addition, the cathode CAT is disposed along the top surfaces of the common layers 621 , 622 , and 624 , so that the distance from the cathode CAT may be reduced compared to the case where the top surface of the bank 616 is planarized.

Accordingly, in the display device 600 according to another embodiment of the present invention, a bank 616 having a trench shape is disposed between the two metal patterns 540 to form the common layers 621 , 622 , and the light emitting device ED. 624) can be minimized. A DC voltage may be applied to the metal pattern 540 adjacent to the anode ANO during the light emission period S30 . Accordingly, carriers of the leakage current may be trapped by the capacitor formed between the metal pattern 540 and the cathode CAT during the light emission period S30 . At this time, by the trench structure of the bank 616 , the gap between the metal pattern 540 and the cathode CAT is reduced to increase the capacitance between the metal pattern 540 and the cathode CAT, and the common layers 621 , 622 , and 624 . ) to increase the resistance of the common layers 621 , 622 , and 624 , the effect of reducing leakage current flowing through the common layers 621 , 622 , and 624 may be further increased.

In addition, in the display device 600 according to another embodiment of the present invention, the metal pattern 540 is floated during the initialization period S10 and the writing/sensing period S20 to generate parasitic capacitance between the metal pattern 540 and transistors. can be reduced, and it is possible to suppress a luminance lifting phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

9A to 9D are graphs for explaining a leakage current in a display device according to a comparative example and another exemplary embodiment of the present invention. 9A is a graph for explaining a leakage current in a comparative example in which a metal pattern 140 is excluded from the display device 100 according to an exemplary embodiment of the present invention. FIG. 9B is a graph for explaining a leakage current in the display device 400 according to another exemplary embodiment illustrated in FIGS. 6A and 6B . FIG. 9C is a graph for explaining a leakage current in the display device 500 according to another embodiment of the present invention shown in FIG. 7 . FIG. 9D is a graph for explaining a leakage current in the display device 600 according to another embodiment of the present invention shown in FIG. 8 . 9A to 9 show the third sub-pixel SP1 from the first sub-pixel SP1 while increasing the voltage applied to the anode ANO of the first sub-pixel SP1 in a state in which the third sub-pixel SP3 is turned off. 3 is a graph in which leakage current flowing to the sub-pixel SP3 is measured. 9A to 9D , the X-axis is the voltage applied to the anode ANO of the first sub-pixel SP1 and the Y-axis is the leakage current flowing into the adjacent third sub-pixel SP3.

Referring to FIG. 9A , in the comparative example, the leakage current starts to rapidly increase when the voltage applied to the anode ANO of the first sub-pixel SP1 is about 1V. Accordingly, even when a very low voltage, such as about 1V, is applied to the anode ANO of the first sub-pixel SP1 , a leakage current flows in the third sub-pixel SP3 so that the third sub-pixel SP3 may emit light. .

Referring to FIG. 9B , in the display device 400 according to another exemplary embodiment illustrated in FIGS. 6A and 6B , the voltage applied to the anode ANO of the first sub-pixel SP1 is about 3V. leakage current begins to surge. Accordingly, when the voltage applied to the anode ANO of the first sub-pixel SP1 is low, that is, leakage current from the first sub-pixel SP1 to the third sub-pixel SP3 does not occur during low grayscale driving. can confirm.

Referring to FIG. 9C , in the display device 500 according to another embodiment of the present invention shown in FIG. 7 , leakage occurs when the voltage applied to the anode ANO of the first sub-pixel SP1 is about 3.3V. The current starts to surge. Accordingly, when the voltage applied to the anode ANO of the first sub-pixel SP1 is low, that is, leakage current from the first sub-pixel SP1 to the third sub-pixel SP3 does not occur during low grayscale driving. can confirm.

Referring to FIG. 9D , in the display device 600 according to another embodiment of the present invention shown in FIG. 8 , leakage occurs when the voltage applied to the anode ANO of the first sub-pixel SP1 is about 3.6V. The current starts to surge. Accordingly, when the voltage applied to the anode ANO of the first sub-pixel SP1 is low, that is, leakage current from the first sub-pixel SP1 to the third sub-pixel SP3 does not occur during low grayscale driving. can confirm.

10 is an enlarged plan view of a display device according to another exemplary embodiment. The display device 700 of FIG. 10 differs from the display device 300 of FIGS. 5A and 5B only in the plurality of sub-pixels SP and the metal pattern 740 , but other configurations are substantially the same. is omitted.

Referring to FIG. 10 , the plurality of sub-pixels SP includes a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 .

The plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 may be alternately disposed in the same column or in the same row. For example, the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same column, and the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same row can be

The plurality of second sub-pixels SP2 are disposed in different columns and different rows from the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 . For example, a plurality of second sub-pixels SP2 are arranged in one row, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 are alternately arranged in a row adjacent to one row. can be placed as A plurality of second sub-pixels SP2 may be disposed in one column, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 may be alternately disposed in a column adjacent to one column. The plurality of first sub-pixels SP1 and the second sub-pixels SP2 may face each other in a diagonal direction, and the plurality of third sub-pixels SP3 and the second sub-pixels SP2 may also face each other in a diagonal direction. Accordingly, the plurality of sub-pixels SP may be arranged in a grid shape.

However, in FIG. 10 , the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are arranged in the same column and in the same row, and the plurality of second sub-pixels SP2 are the plurality of first sub-pixels. Although it is illustrated that the plurality of sub-pixels SP are disposed in different columns and different rows from those of SP1 and the plurality of third sub-pixels SP3, the arrangement of the plurality of sub-pixels SP is not limited thereto.

Referring to FIG. 10 , the plurality of metal patterns 740 may be disposed in a closed curve shape surrounding the plurality of sub-pixels SP. In detail, the plurality of metal patterns 740 may extend from the anode ANO of the first sub-pixel SP1 having the highest turn-on voltage and may be disposed in a closed curve shape surrounding the first sub-pixel. In the display device 700 according to another embodiment of the present invention, the metal pattern 740 may be disposed to minimize leakage current through the common layers 121 , 122 , and 124 of the light emitting device ED. A DC voltage may be applied to the metal pattern 740 connected to the anode ANO of the first sub-pixel during the light emission period S30 . Accordingly, carriers of the leakage current may be trapped by the capacitor formed between the metal pattern 740 and the cathode CAT during the light emission period S30 .

In addition, in the display device 700 according to another embodiment of the present invention, the metal pattern 740 is floated during the initialization period S10 and the write/sensing period S20 to generate parasitic capacitance between the metal pattern 740 and transistors. can be reduced, and it is possible to suppress a luminance lifting phenomenon that occurs due to an increase in luminance during black driving or low grayscale driving.

A display device according to various embodiments of the present disclosure may be described as follows.

According to an embodiment of the present invention, a plurality of light emitting devices disposed on a substrate on which a plurality of sub-pixels are defined, a plurality of sub-pixels, and a plurality of light emitting devices including an anode, an organic layer and a cathode, and at least one disposed between each of the plurality of sub-pixels and a bank disposed between the metal pattern and the organic layer between each of the plurality of sub-pixels, wherein the plurality of light-emitting devices share the organic layer and a cathode, and the metal pattern includes a light-emitting period of the sub-pixel adjacent to the metal pattern. is configured to be applied while the voltage is applied.

Another feature of the present invention is that the metal pattern may be configured such that a DC voltage is applied during an emission period of a sub-pixel adjacent to the metal pattern.

Another feature of the present invention is that the metal pattern may be floated for a period excluding the light emission period of the sub-pixel adjacent to the metal pattern.

Another feature of the present invention is that the metal pattern may be connected to the anode of the sub-pixel adjacent to the metal pattern so that the same voltage as the anode may be applied.

Another feature of the present invention is that the metal pattern is disposed on the same layer as the anode, and may be made of the same material as the anode.

Another feature of the present invention is that the metal pattern may be thicker than the anode.

Another feature of the present invention is that the metal pattern is disposed on the same layer as the anode, and may include a first layer made of the same material as the anode and a second layer disposed on the first layer.

Another feature of the present invention is that a plurality of metal patterns may be disposed between sub-pixels adjacent to each other.

Another feature of the present invention is that the bank may have a trench structure disposed between a plurality of metal patterns.

Another feature of the present invention is that the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors, and the first sub-pixel, the second sub-pixel and the second sub-pixel A turn-on voltage may decrease in the order of the three sub-pixels, and the metal pattern may be disposed between the first sub-pixel and the third sub-pixel.

Another feature of the present invention is that the metal pattern may be configured such that the same voltage as that of the anode disposed in the first sub-pixel is applied.

According to another feature of the present invention, a plurality of metal patterns may be disposed between the first sub-pixel and the third sub-pixel.

According to another feature of the present invention, the metal pattern may be further disposed between the first sub-pixel and the second sub-pixel and between the second sub-pixel and the third sub-pixel.

Another feature of the present invention is that the metal pattern may be configured such that the same voltage as an anode disposed in a sub-pixel having a higher turn-on voltage among two adjacent sub-pixels is applied.

Another feature of the present invention is that a plurality of metal patterns are disposed between sub-pixels adjacent to each other, and the metal patterns may be configured such that the same voltage as an anode disposed in a closer sub-pixel among adjacent sub-pixels is applied. .

Another feature of the present invention is that the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a red sub-pixel.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 200, 300, 400, 500, 600, 700: display device
110: substrate
111: buffer layer
112: gate insulating layer
113: interlayer insulating layer
114: passivation layer
115: planarization layer
116, 616: bank
ANO: anode
120, 620, 720: organic layer
121, 621: hole injection layer
122, 622: hole transport layer
123: light emitting layer
124, 624: electron transport layer
140, 240, 340, 440, 540, 740: metal pattern
CAT: cathode
ED: light emitting element
PN: display panel
GD: gate driver
DD: data driver
TC: Timing Controller
SP: sub pixel
SP1: first sub-pixel
SP2: second sub-pixel
SP3: third sub-pixel
SL: scan wiring
SL1: first scan wiring
SL2: second scan wiring
DL: data wiring
PL: high potential power wiring
EL: Light emission control signal wiring
IL: Initialization signal wiring
Cst: capacitor
T1: first transistor
T2: second transistor
T3: third transistor
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
DT: driving transistor
ACT: active layer
GE: gate electrode
DE: drain electrode
SE: source electrode
RGB: image data
GCS: gate control signal
DCS: data control signal
SYNC: Sync signal
EVDD: high potential power signal
SCAN1: first scan signal
SCAN2: second scan signal
Vdata: data signal
EM: light emission control signal
Vini: initialization signal
VIL: Initialization voltage line
EML: Emission Control Line
DVL: drive voltage line

Claims (16)

a substrate on which a plurality of sub-pixels are defined;
a plurality of light emitting devices disposed on the plurality of sub-pixels and including an anode, an organic layer, and a cathode;
at least one metal pattern disposed between each of the plurality of sub-pixels; and
a bank disposed between the metal pattern and the organic layer between each of the plurality of sub-pixels;
The plurality of light emitting devices share the organic layer and the cathode,
The metal pattern is configured such that a voltage is applied during an emission period of a sub-pixel adjacent to the metal pattern. According to claim 1,
The metal pattern is configured such that a DC voltage is applied during an emission period of a sub-pixel adjacent to the metal pattern. According to claim 1,
The metal pattern is floated for a period excluding an emission period of a sub-pixel adjacent to the metal pattern. According to claim 1,
The metal pattern is connected to the anode of a sub-pixel adjacent to the metal pattern, and the same voltage as that of the anode is applied thereto. 5. The method of claim 4,
The metal pattern is disposed on the same layer as the anode and made of the same material as the anode. 5. The method of claim 4,
and the metal pattern is thicker than the anode. 7. The method of claim 6,
The metal pattern is
a first layer disposed on the same layer as the anode and made of the same material as the anode; and
and a second layer disposed on the first layer. According to claim 1,
A plurality of the metal patterns are disposed between sub-pixels adjacent to each other. 9. The method of claim 8,
and the bank has a trench structure disposed between the plurality of metal patterns. According to claim 1,
The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors;
a turn-on voltage decreases in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
The metal pattern is disposed between the first sub-pixel and the third sub-pixel. 11. The method of claim 10,
The metal pattern is configured such that the same voltage as that of the anode disposed in the first sub-pixel is applied. 12. The method of claim 11,
A plurality of the metal patterns are disposed between the first sub-pixel and the third sub-pixel. 11. The method of claim 10,
The metal pattern is further disposed between the first sub-pixel and the second sub-pixel and between the second sub-pixel and the third sub-pixel. 14. The method of claim 13,
The metal pattern is configured to apply the same voltage as the anode disposed in a sub-pixel having a higher turn-on voltage among two adjacent sub-pixels. 14. The method of claim 13,
A plurality of the metal patterns are disposed between the sub-pixels adjacent to each other,
The metal pattern is configured such that the same voltage as that of the anode disposed in a closer sub-pixel among adjacent sub-pixels is applied. 11. The method of claim 10,
the first sub-pixel is a blue sub-pixel;
the second sub-pixel is a green sub-pixel;
and the third sub-pixel is a red sub-pixel.

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