KR20220059879A - Semiconductor device including chalcogen compound and semiconductor appratus inclduing the same - Google Patents

Abstract

Provided are a chalcogen compound layer showing an ovonic threshold switching characteristic, and a switching device, semiconductor device, and/or semiconductor apparatus including the same. The switching device and/or semiconductor device can include two or more chalcogen compound layers with different energy bandgaps. Or the switching device and/or semiconductor device can include a chalcogen compound layer in which elements of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) have a concentration gradient in a thicknesswise direction. The switching device and/or semiconductor device are able to realize stable switching characteristics while having a low off current value (leakage current value).

Description

A semiconductor device comprising a chalcogen compound layer and a semiconductor device including the same

To a semiconductor device including a chalcogen compound layer and a semiconductor device including the same.

Demand for high integration of semiconductor devices is increasing according to the trend of light, thin and compact electronic products. Accordingly, various types of semiconductor devices have been proposed, for example, a semiconductor device including a variable resistance layer and a selection device layer.

Provided are a chalcogen compound layer exhibiting ovonic threshold switching characteristics and a switching device including the same.

A semiconductor device, and/or a semiconductor device, having a low off-state current and excellent reliability (durability) is provided.

A semiconductor device according to an embodiment may include a selection device layer exhibiting an ovonic threshold switching characteristic. The selection device layer may include two or more chalcogen compound layers having different energy band gaps.

Specifically, the selection device layer may include a first chalcogen compound layer and a second chalcogen compound layer having different compositions, and the chalcogen compound layers are each independently germanium (Ge) and/or tin (Sn). It may include a first element and a second element including sulfur (S), selenium (Se), and/or tellurium (Te).

The first chalcogen compound layer and/or the second chalcogen compound layer are each independently selected from the group consisting of arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi). It may contain more elements. In addition, the second chalcogen compound layer is one or more selected from the group consisting of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In). It may further include an element, and the first chalcogen compound layer is one or two or more selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). It may further include 5 elements.

The first chalcogenide compound layer may have an energy bandgap of 0.1 eV or more and 1.0 eV or less than the second chalcogen compound layer.

The first chalcogen compound layer may include a compound of Formula 1, Formula 3, and/or Formula 4, and the second chalcogen compound layer may include a compound of Formula 1 and/or Formula 2.

[Formula 1]

A _a B _b C _c

[Formula 2]

A _a B _b C _c D _d

[Formula 3]

A _a B _b

[Formula 4]

A _a B _b C _c E _e

a≤ 0.70, 0.05≤ b≤ 0.70일 수 있다.In Formula 1, Formula 2, Formula 3, or Formula 4, A is a first element, B is a second element, C is a third element, D is a fourth element, E is a fifth element, and in Formula 1, a+b +c=1, a+b+c+d=1 in Formula 2, a+b=1 in Formula 3, a+b+c+e=1 in Formula 4. In Formula 1, Formula 2, or Formula 4, 0.05≤a≤0.30, 0.20≤b≤0.70, 0.05≤c≤0.50, 0.01≤d≤0.10, 0.01≤e≤0.10. 0.05 in Formula 3

a ≤ 0.70 and 0.05 ≤ b ≤ 0.70.

The semiconductor device may further include a variable resistance layer. Specifically, the semiconductor device further includes a first electrode layer, a second electrode layer, and a third electrode layer, wherein the selection device layer is between the first electrode layer and the second electrode layer, and the variable resistance layer is between the second electrode layer and the third electrode layer. can be placed.

The variable resistance layer may include a material capable of reversibly changing a crystalline phase and an amorphous phase according to a change in temperature. The variable resistance layer is one or more of the group consisting of Te and/or Se and Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O and C. It may include compounds in which elements are combined.

A chalcogen compound layer exhibiting ovonic threshold switching characteristics may be provided.

A switching element, semiconductor element, and/or semiconductor device having excellent durability while having a low off-state current value (leakage current value) can be provided. Such devices and/or devices may realize an improved degree of integration and may contribute to miniaturization of electronic devices.

1 is an equivalent circuit diagram of a semiconductor device according to an exemplary embodiment.
2 is a graph schematically illustrating a voltage-current curve of a material having an ovonic threshold switching characteristic.
3A to 3C are schematic diagrams of a semiconductor device and/or a switching device according to example embodiments.
4A is a perspective view of a semiconductor device according to an exemplary embodiment.
4B is a cross-sectional view taken along lines 1X-1X' and 1Y-1Y' of the semiconductor device of FIG. 3A.
4C is a schematic cross-sectional view of a semiconductor device according to another embodiment.
5A to 5C are schematic diagrams illustrating a manufacturing process of a semiconductor device according to an exemplary embodiment.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the technical idea. What is described as "upper" or "upper" may include those directly above/below/left/right in contact as well as above/below/left/right in non-contact.

The singular expression includes the plural expression unless the context clearly dictates otherwise. Terms such as "comprises" or "have" are intended to indicate that the features, numbers, steps, operations, components, parts, components, materials, or combinations thereof described in the specification exist unless otherwise stated. , one or more other features, or numbers, steps, acts, elements, parts, components, materials, or combinations thereof, or combinations thereof, are not to be understood as precluding the possibility of addition.

Terms such as "first", "second", "third", etc. may be used to describe various elements, but are used only for the purpose of distinguishing one element from other elements, and the order of elements; The type and the like are not limited. In addition, terms such as "unit", "means", "module", "unit", etc. mean a unit of a comprehensive configuration that processes any one function or operation, which is implemented as hardware or software, or It can be implemented by a combination of and software.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the sizes (widths, thicknesses, etc. of layers, regions, etc.) of each component in the drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments.

According to one aspect, a semiconductor device having excellent reliability (durability) and a semiconductor device including the same are provided. Specifically, the semiconductor device may include a plurality of semiconductor elements between two spaced apart electrode lines, and the semiconductor elements may include a variable resistance layer and a selection element layer electrically connected to each other. Also, the semiconductor device may have a three-dimensional structure in which two electrode lines have cross points. Such a semiconductor device and/or a semiconductor device may be a memory device.

1 is an equivalent circuit diagram of a semiconductor device according to an exemplary embodiment.

Referring to FIG. 1 , the semiconductor device 100 may include a plurality of first electrode lines WL1 and WL2 extending parallel to each other in a first direction (X direction). Also, in the semiconductor device 100 , the first electrode lines WL1 and WL2 are spaced apart from each other in the third direction (Z direction), and the second electrode lines BL1 , BL2 , and BL3 extending parallel to each other in the second direction. , BL4). The semiconductor device MC may be disposed between the first electrode lines WL1 and WL2 and the second electrode lines BL1 , BL2 , BL3 and BL4 . Specifically, the semiconductor devices MC may be electrically connected to the first electrode lines WL1 and WL2 and the second electrode lines BL1 , BL2 , BL3 and BL4 and disposed at intersections between these lines, respectively. . Also, the semiconductor device MC may include a variable resistance layer ME and a selection device layer SW that are electrically connected to each other. For example, the variable resistance layer ME and the selection element layer SW may be disposed to be connected in series along the third direction (Z direction), and the selection element layer SW may include the first electrode line WL1, WL2) and one of the second electrode lines BL1, BL2, BL3, and BL4 may be electrically connected, and the variable resistance layer ME may be electrically connected to the other electrode line.

Briefly describing the driving method of the semiconductor device 100 , the variable resistance layer ME of the semiconductor element MC is provided through the first electrode lines WL1 and WL2 and the second electrode lines BL1 , BL2 , BL3 and BL4 . ), voltage is applied and current can flow. Specifically, an arbitrary semiconductor element MC can be addressed by selection of the first electrode lines WL1 and WL2 and the second electrode lines BL1, BL2, BL3, and BL4, and the first electrode line WL1, By applying a predetermined signal between WL2 and the second electrode lines BL1 , BL2 , BL3 , and BL4 , the semiconductor device MC may be programmed. In addition, by measuring the current value through the second electrode lines BL1, BL2, BL3, BL4, information according to the resistance value of the variable resistance layer ME of the corresponding semiconductor device MC, that is, programmed information, can be read. can

The variable resistance layer ME may serve to store information. Specifically, the resistance value of the variable resistance layer ME may vary according to an applied voltage. The semiconductor device MC may store or erase digital information such as '0' or '1' according to a change in the resistance of the variable resistance layer ME. For example, the semiconductor device MC may write data in the high resistance state of the variable resistance layer ME as '0' and the low resistance state as '1'. Here, writing from the high resistance state '0' to the low resistance state '1' can be referred to as a 'set operation', and writing from the low resistance state '1' to the high resistance state '0' is 'reset ( reset) operation'.

The selection element layer SW may serve to select (address) the semiconductor element MC by controlling the flow of current to the semiconductor element MC electrically connected to the selection element layer SW. . Specifically, the selection element layer SW may include a material whose resistance can change according to the magnitude of the voltage applied across both ends. For example, the selection element layer SW may have an Ovonic Threshold Switching (OTS) characteristic.

2 is a graph schematically illustrating a voltage-current curve of a selection device layer having an ovonic threshold switching characteristic. Referring to FIG. 2 , the first curve 21 represents a voltage-current relationship in a state in which little current flows in the selection element layer SW. When the voltage is gradually increased while the voltage and current are zero, the selection element layer SW is in a high resistance state, almost until the voltage reaches the threshold voltage V _th (the first voltage level 23 ). Current may not flow. However, as soon as the voltage exceeds the threshold voltage (V _th ), the selection element layer (SW) is in a low resistance state, the current flowing through the selection element layer (SW) can rapidly increase, and the selection element layer (SW) The applied voltage is reduced to the saturation voltage V _S (second voltage level 24 ). The second curve 22 represents a voltage-current relationship in a state in which current flows more smoothly in the selection element layer SW. As the current flowing through the selection element layer SW becomes greater than the first current level 26 , the voltage applied to the selection element layer SW may slightly increase than the second voltage level 24 . For example, while the current flowing through the selection element layer SW significantly increases from the first current level 26 to the second current level 27, the voltage applied to the selection element layer SW increases at the second voltage level ( 24) can be slightly increased. In other words, once the current flows through the selection element layer SW, the voltage applied to the selection element layer SW may be almost maintained as the saturation voltage V _S . If the current decreases below the holding current level (the first current level 26 ), the selection element layer SW is converted to a high resistance state again, and the current until the voltage increases to the threshold voltage V _th . can be effectively blocked. Due to these characteristics, the selection element layer SW may act as a switching element having a threshold voltage V _th of the first voltage level 23 .

However, even when a voltage lower than the threshold voltage V _th is applied to the semiconductor device (when the semiconductor device is in an off state), as shown in FIG. 2 , a certain level of current is generated in the selection device layer SW. can flow If the off-state current (leakage current) is large, it may be difficult to operate the semiconductor device at once as the number of semiconductor devices included increases. In addition, the selection element layer SW is reliable as the threshold voltage (V _th ) or the ratio of the on current (I _on / I _off ) to the off current (I on / I off ) changes depending on the accumulated use time of the semiconductor device, the accumulated on/off number, etc. , the durability may deteriorate.

The selection device layer (SW) according to an embodiment includes two or more chalcogenide compound layers, so that it has a low off-state current value (leakage current value) and can implement stable switching characteristics. Specifically, the selection device layer SW according to an embodiment includes a first element including germanium (Ge) and/or tin (Sn), sulfur (S), selenium (Se), and/or tellurium (Te). ) each independently including a second element including, and may include two or more chalcogen compound layers having different compositions.

The first-layer selective element layer (SW) made of chalcogenide and d water of three components of GeAsSe may have Ovonic Threshold Switching (OTS) characteristics, but a high off-state current value (leakage current value) and insufficient durability Therefore, it is difficult to apply it to an actual semiconductor device. The selection element layer (SW) according to an embodiment may include two or more chalcogen compound layers having different energy band gaps (Eg) and/or compositions, so as to have a low off current value (leakage current value) and improved durability. there is. Although not wishing to be bound by a particular theory, the selection device layer (SW) according to an embodiment has a low leakage by controlling electron movement between them through an energy bandgap difference between the chalcogen compound layers having an ovonic threshold switching characteristic. It can have a current value and improved durability.

3A to 3C are schematic diagrams of semiconductor devices according to example embodiments. Referring to FIG. 3A , the selection device layer SW may include two or more chalcogen compound layers each having different energy band gaps. In other words, the first chalcogen compound layer (SWa) may have a larger energy band gap than the second chalcogen compound layer (SWb). For example, the energy band gap of the first chalcogenide compound layer is 0.1eV or more, 0.2eV or more, 0.3eV or more, 0.4eV or more, 0.5eV or more, 0.6eV or more, 1.0eV or less, 0.9eV or more than the second chalcogen compound layer. or less, 0.8 eV or less, or 0.7 eV or less.

The first chalcogenide compound layer (SWa) and the second chalcogen compound layer (SWb) are each independently a first element including germanium (Ge) and / or tin (Sn), sulfur (S), selenium (Se) and/or a second element including tellurium (Te).

The first element content of the first chalcogenide compound layer (SWa) and the second chalcogen compound layer (SWb) may each independently be 5.0at% or more and 30.0at% or less relative to the total element content. For example, the content of the first element may be 7.0at% or more, 10.0at% or more, 25.0at% or less, 23.0at% or less, or 20.0at% or less relative to the total elements.

The content of the second element of the first chalcogenide compound layer (SWa) and the second chalcogen compound layer (SWb) may each independently exceed 0.0at% and 70.0at% or less with respect to the total element. For example, the content of the second element relative to the total element is 10.0at% or more, 15at% or more, 20.0at% or more, 25.0at% or more, 30.0at% or more, 35.0at% or more, 40.0at% or more, 65.0at% or less , 60.0at% or less, or 55.0at% or less.

The first chalcogenide compound layer (SWa) and / or the second chalcogen compound layer (SWb) is each independently one or It may further include a third element selected from two or more. The content of the third element of the first chalcogenide compound layer (SWa) and/or the second chalcogen compound layer (SWb) may each independently be 5.0at% or more and 50.0at% or less relative to the total element content. For example, the content of the third element may be 7.0at% or more, 10.0at% or more, 15.0at% or more, 20.0at% or more, 45.0at% or less, 40.0at% or less, or 35.0at% or less relative to the total element.

The second chalcogen compound layer SWb may further include a metal dopant. Specifically, the second chalcogen compound layer (SWb) is one or two from the group consisting of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In). It may further include a fourth element selected above. The content of the fourth element of the second chalcogenide compound layer (SWb) may be 0.1at% or more and 10.0at% or less relative to the total element content. For example, the content of the third element may be 0.5at% or more, 1.0at% or more, 1.5at% or more, 2.0at% or more, 7.0at% or less, 6.0at% or less, or 5.0at% or less relative to the total element.

The first chalcogenide compound layer SWa may further include a non-metal dopant. Specifically, the first chalcogen compound layer (SWa) is one or two or more selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S) a fifth element may further include. The content of the fifth element of the first chalcogenide compound layer (SWa) may be 0.1at% or more and 10.0at% or less relative to the total element content. For example, the content of the fifth element may be 0.5at% or more, 1.0at% or more, 1.5at% or more, 2.0at% or more, 7.0at% or less, 6.0at% or less, or 5.0at% or less relative to the total element.

The first chalcogen compound layer (SWa) may include a compound of Formula 1, Formula 3, and/or Formula 4. In addition, the second chalcogen compound layer (SWb) may include a compound of Formula 1 and/or Formula 2.

[Formula 1]

A _a B _b C _c

[Formula 2]

A _a B _b C _c D _d

[Formula 3]

A _a B _b

[Formula 4]

A _a B _b C _c E _e

a≤ 0.70, 0.05

b≤ 0.70일 수 있다.In Formula 1, Formula 2, Formula 3, or Formula 4, A is a first element, B is a second element, C is a third element, D is a fourth element, E is a fifth element, and in Formula 1, a+b +c=1, a+b+c+d=1 in Formula 2, a+b=1 in Formula 3, a+b+c+e=1 in Formula 4. In Formula 1, Formula 2, or Formula 4, 0.05≤a≤0.30, 0.20≤b≤0.70, 0.05≤c≤0.50, 0.01≤d≤0.10, 0.01≤e≤0.10. 0.05 in Formula 3

a≤ 0.70, 0.05

b≤0.70.

According to an embodiment, the second chalcogen compound layer (SWb) may include the compound of Formula 1, and the first chalcogen compound layer (SWa) may include the compound of Formula 3 and/or the compound of Formula 4. According to another embodiment, the second chalcogen compound layer (SWb) includes the compound of Formula 2, and the first chalcogen compound layer (SWa) includes the compound of Formula 1, the compound of Formula 3, and/or the compound of Formula 4 can do.

The first chalcogen compound layer (SWa) and/or the second chalcogen compound layer (SWb) may have an appropriate thickness depending on desired performance. For example, the thickness of the first chalcogenide compound layer (SWa) and / or the second chalcogen compound layer (SWb) is each independently 0.5 nm or more, 1.0 nm or more, 2.0 nm or more, 3.0 nm or more, 5.0 nm or more, 7.0 nm or more, 10.0 nm or more, 15.0 nm or more, 30.0 nm or less, 28.0 nm or less, 25.0 nm or less, 23.0 nm or less, 20.0 nm or less, 17.0 nm or less, 15.0 nm or less, 13.0 nm or less, 10.0 nm or less, or 8.0 nm may be below. In addition, the second chalcogenide compound layer (SWb) compared to the first chalcogen compound layer (SWa) 0.1 times or more, 0.2 times or more, 0.3 times or more, 0.5 times or more, 1.5 times or less, 1.2 times or less, 1.0 times or less, 0.8 times or more It may have the following volume ratio (or thickness ratio).

Referring to FIG. 3b , the selection element layer SW may further include a third chalcogen compound layer SWc disposed adjacent to the second chalcogen compound layer SWb and spaced apart from the first chalcogen compound layer SWa. there is. In other words, the selection device layer (SW) may have a stacked structure of the first chalcogen compound layer (SWa) / the second chalcogen compound layer (SWb) / the third chalcogen compound layer (SWc).

The third chalcogen compound layer (SWc) may include the aforementioned compounds of Formula 1, Formula 3, and/or Formula 4. The third chalcogen compound layer (SWc) may have a larger energy bandgap than the second chalcogen compound layer (SWb). In addition, the energy band gap of the third chalcogen compound layer (SWc) may be greater than or equal to that of the first chalcogen compound layer (SWa).

According to another embodiment, the selection element layer SW includes a first element, a second element, a third element, and a fourth element, and the fourth element has a concentration gradient in the thickness direction of the selection element layer SW. can have Specifically, referring to FIG. 3C , the selection element layer SW has a first surface SW1 and a second surface SW2 facing the first electrode 10 and the second electrode 20, respectively, and The four elements may have a concentration gradient in a thickness direction between the first surface SW1 and the second surface SW2 . For example, the concentration of the fourth element on the second surface SW2 may be greater or less than that on the first surface SW1, and the concentration of the fourth element on the first surface SW1 may be 0. . In addition, the fourth element may have a maximum concentration at a predetermined thickness position (between SW1′ and SW2′) and decrease or become zero as it goes toward the first surface SW1 and/or the second surface SW2 . Also, such a concentration gradient of the fourth element may appear from positions SW1 ′ and SW2 ′ separated by a predetermined thickness from the first surface (or second surface SW1 , SW2 ). In other words, the fourth element is present on the first (and/or second side) (SW1, SW2) and/or from the first (and/or second side) to a predetermined thickness SW1′, SW2′. may not exist in The positions of SW1` and SW2` are not particularly limited, but for example, more than 0%, 1% or more, 3% of the total thickness of the selection element layer (SW) from the first electrode 10 and the second electrode 20, respectively. or more, 5% or more, 7% or more, 10% or more, 15% or more, 20% or more, 75% or less, 70% or less, 65% or less, 60% or less, 58% or less, 55% or less, 53% or less, 50% or less, 48% or less, 45% or less, 43% or less, 40% or less, 38% or less, or 35% or less.

The selection element layer SW may further include a fifth element, and the fifth element may also have a concentration gradient in the thickness direction of the selection element layer SW. For example, the concentration of the fifth element on the first surface SW1 may be greater or less than that on the second surface SW2, and the concentration of the fifth element on the second surface SW2 may be 0. . In addition, the concentration of the fifth element may be minimum or zero at a predetermined thickness position (between SW1′ and SW2′). A concentration gradient direction of the fifth element may be different from that of the fourth element. For example, the direction may be opposite to that of the fourth element. Specifically, from the first surface SW1 to the second surface SW2 , the concentration of the fifth element may decrease and the concentration of the fourth element may increase.

The selection element layer SW according to an exemplary embodiment may have excellent thermal stability, and thus may be less damaged or deteriorated in a manufacturing process of a semiconductor device or the like. Specifically, the crystallization temperature of each chalcogen compound layer or the selection element layer SW may be 350 degrees C or more, and 600 degrees C or less. For example, the crystallization temperature may be 380 degrees C or more, 400 degrees C or more, 580 degrees C or less, or 550 degrees C or less. In addition, each chalcogen compound layer or the selection element layer (SW) may have a sublimation temperature of 250 degrees C or more, and 400 degrees C or less. For example, the sublimation temperature may be 280 degrees C or more, 300 degrees C or more, 380 degrees C or less, or 350 degrees C or less.

The semiconductor device and the semiconductor device according to an embodiment may further include an electrode electrically connecting each component. 4A and 4B are perspective and cross-sectional views of a semiconductor device according to an exemplary embodiment. 4A and 4B , the semiconductor device 100 may include a first electrode line layer 110L, a second electrode line layer 120L, and a semiconductor element layer MCL on a substrate 101 . .

The first electrode line layer 110L may include a plurality of first electrode lines 110 extending parallel to each other in the first direction (X direction). The second electrode line layer 120L may include a plurality of second electrode lines 120 that are spaced apart from the first electrode line layer 110L and extend parallel to each other in the second direction. The first direction and the second direction may be different from each other, and may cross each other perpendicularly as in the X direction and the Y direction of FIG. 4A , but is not limited thereto. In terms of driving the semiconductor device, the first electrode lines 110 may correspond to one of a word line and a bit line, and the second electrode lines 120 may correspond to the other.

The first electrode lines 110 and the second electrode lines 120 may each independently be formed of a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode lines 110 and the second electrode lines 120 are each independently W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni , Co, Cr, Sn, Zn, ITO, alloys thereof, or a combination thereof. In addition, the first electrode lines 110 and the second electrode lines 120 may each independently include a metal film and a conductive barrier layer covering a part or all of the metal film. The conductive barrier layer may be formed of, for example, Ti, TiN, Ta, TaN, or a combination thereof.

The semiconductor device layer MCL may include a plurality of semiconductor devices MC. The semiconductor devices MC may be disposed to be spaced apart from each other, and the first electrode lines 110 and the second electrode lines 120 may be disposed between the first electrode lines 110 and the second electrode lines 120 . It may have a three-dimensional structure disposed at these intersecting portions.

The semiconductor device MC may further include, between the selection device layer 143 (SW of FIG. 1 ) and the variable resistance layer 149 (ME of FIG. 1 ), an electrode layer electrically connecting them. In addition, an electrode layer may be further included between the first electrode lines 110 and the selection element layer 143 and/or between the second electrode lines 120 and the variable resistance layer 149 . Specifically, the selection element layer 143 is disposed between the first electrode layer 141 and the second electrode layer 145 , and the variable resistance layer 149 is disposed between the second electrode layer 145 and the third electrode layer 148 . can be placed.

The first electrode layer 141 , the second electrode layer 145 , and the third electrode layer 148 may serve as a passage through which current flows and may include a conductive material. The first electrode layer 141 , the second electrode layer 145 , and the third electrode layer 148 may each independently be formed of a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, they are each independently carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (TiCSiN), titanium aluminum nitride (TiAlN) , one or two or more of tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN) may be selected.

For the selection element layer 143, reference may be made to the above description. For example, the introduction positions of the first chalcogen compound layer 143a and the second chalcogen compound layer 143b are not particularly limited, but the first chalcogen compound layer 143a is the second chalcogen compound layer 143b compared to The first electrode layer 141 may be disposed closer to, or the second chalcogenide compound layer 143b may be disposed closer to the variable resistance layer 149 and/or the second electrode layer 145 . According to another embodiment, in the selection element layer 143 , the concentration of the fourth element is greater at a position adjacent to the second electrode layer 145 than the first electrode layer 141 , or a predetermined value inside the selection element layer 143 . The fourth element may have a maximum concentration at the thickness location. In addition, in the selection element layer 143 , the concentration of the fifth element is smaller at a position adjacent to the second electrode layer 145 than the first electrode layer 141 , or at a predetermined thickness inside the selection element layer 143 . Five elements can have a minimum concentration.

Also, the semiconductor device MC may not include an insulating material between the first electrode layer 141 and the selection device layer 143 and/or between the second electrode layer 145 and the selection device layer 143 . The insulating material may be a metal oxide and/or a metal nitride, and may be silicon oxide, silicon nitride, silicon nitride, or the like.

The variable resistance layer 149 may include a material having a resistance change characteristic according to an applied condition.

According to an embodiment, the variable resistance layer 149 may include a material whose phase can be reversibly changed according to temperature. In other words, the variable resistance layer 149 may include a material capable of reversibly changing a phase between crystalline and amorphous according to a heating time (amount of applied heat). Specifically, the variable resistance layer 149 may be reversibly changed into an amorphous state and a crystalline state by Joule heating generated when an electric pulse is applied from the outside. It may include a material whose resistance can be changed by change. For example, the phase change material may be in a high resistance state in an amorphous phase and a low resistance state in a crystalline phase. By defining the high resistance state as '0' and the low resistance state as '1', data may be stored in the variable resistance layer 149 .

Phase change materials include selenium (Se) and/or tellurium (Te), Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O and C It may include one or two or more elements selected from among them. The phase change material may include Ge-Sb-Te (GST). For example, Ge-Sb-Te (GST) is a compound comprising Ge, Sb, and Te, Ge ₂ Sb ₂ Te ₅ , Ge ₂ Sb ₂ Te ₇ , Ge ₁ Sb ₂ Te ₄ , and/or Ge ₁ Sb ₄ Te ₇ may be included.

Phase change materials are aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium One or more metal elements selected from (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po) are further added may include The metal element may increase the electrical conductivity and thermal conductivity of the variable resistance layer 149 and may increase the crystallization rate.

Each element constituting the phase change material may have various stoichiometry. According to the chemical composition ratio of each element, the crystallization temperature, melting point, phase change rate according to the crystallization energy, and information retention of the phase change material may be controlled. For example, the chemical composition ratio may be adjusted so that the melting point of the phase change material is 500° C. to about 800° C.

The variable resistance layer 149 may have a multilayer structure in which a plurality of layers including different materials are alternately stacked. For example, the variable resistance layer 149 may include a structure in which a layer made of Ge-Te and a layer made of Sb-Te are alternately stacked. Such a stacked structure may be a super-lattice structure. In addition, a barrier layer may be further included between the plurality of layers. The barrier layer may serve to prevent material diffusion between the plurality of layers.

The semiconductor device MC may further include a heating electrode layer 147 capable of heating the variable resistance layer 149 . The heating electrode layer 147 may be disposed between the second electrode layer 145 and the variable resistance layer 149 to be in contact with the variable resistance layer 149 . The heating electrode layer 147 may include a conductive material capable of generating sufficient heat to change the phase of the variable resistance layer 149 without reacting with the variable resistance layer 149 . The heating electrode layer 147 may include a carbon-based conductive material. For example, the heating electrode layer 147 may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), carbon nitride (CN), titanium carbon nitride (TiCN), tantalum carbon nitride (TaCN), or a combination thereof may include

The second electrode layer 145 may be formed to a thickness such that heat generated by the heating electrode layer 147 does not substantially affect the selection element layer 143 . The second electrode layer 145 may be formed to be thicker than the first electrode layer 141 or the third electrode layer 148 , and may have a thickness of about 10 nm to about 100 nm. In addition, the second electrode layer 145 may further include a thermal barrier layer, and may have a structure in which a thermal barrier layer and an electrode material layer are alternately stacked. The heating electrode layer 147 is for heating the variable resistance layer 149, which is a phase change material by heat, and in the following embodiments in which the material of the variable resistance layer 149 is a different material, the heating electrode layer 147 is omitted. can be

According to another embodiment, the variable resistance layer 149 may include a material whose electrical resistance can be reversibly changed while defects in the compound move according to an externally applied voltage. For example, the variable resistance layer 149 may include a transition metal oxide. In the transition metal oxide, as oxygen vacancy moves according to an externally applied voltage, an electrical path is created/disappears, and the transition metal oxide may reversibly change into a low-resistance state and a high-resistance state. The transition metal oxide may include one or two or more selected from among Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr. For example, transition metal oxides are Ta ₂ O _5-x , ZrO _2-x , TiO _2-x , HfO _2-x , MnO _2-x , Y ₂ O _3-x , NiO _1-y , Nb ₂ O _5-x , CuO _1-y , and Fe ₂ O _3-x may include one or two or more. (It may be 0≤x≤1.5, 0≤y≤0.5.)

According to another embodiment, the variable resistance layer 149 may be a material whose electrical resistance can be reversibly changed while the polarization state is changed according to an externally applied voltage. For example, the variable resistance layer 149 may include a perovskite compound. The variable resistance layer 149 is formed of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO((Pr,Ca)MnO3 ), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, And it may include one or two or more of barium-strontium-zirconium oxide (barium-strontium-zirconium oxide).

According to another embodiment, the variable resistance layer 149 may be a material whose electrical resistance can be reversibly changed while a magnetization state is changed according to an externally applied voltage. The variable resistance layer 149 may have a magnetic tunnel junction (MTJ) structure. Specifically, the variable resistance layer 149 may include two electrodes made of a magnetic material and a dielectric interposed between the two magnetic electrodes. The two electrodes made of a magnetic material may be a magnetization pinned layer and a magnetization free layer, respectively, and a dielectric interposed therebetween may be a tunnel barrier layer. The magnetization pinned layer has a magnetization direction fixed in one direction, and the magnetization free layer may have a magnetization direction changed by a spin torque of internal electrons. Specifically, the magnetization direction of the magnetization free layer may be reversibly changed to be parallel or antiparallel to the magnetization direction of the magnetization pinned layer, and the variable resistance layer 149 is converted into a high resistance state and a low resistance state according to the magnetization direction of the magnetization free layer. can be reversibly changed. The magnetization pinned layer and the magnetization free layer may include a ferromagnetic material, and the magnetization pinned layer may further include an antiferromagnetic material for fixing a magnetization direction of the internal ferromagnetic material. In addition, the tunnel barrier layer may include one or two or more oxides selected from Mg, Ti, Al, MgZn, and MgB.

The semiconductor device MC may have a pillar shape. For example, the semiconductor device MC may have a quadrangular prism shape as shown in FIGS. 4A and 4B , and may have various prism shapes such as a cylinder, an elliptical prism, and a polygonal prism.

Also, the side of the semiconductor device MC may be perpendicular to the substrate 101 as shown in FIGS. 4A and 4B . In other words, the semiconductor device MC may have a constant cross-sectional area perpendicular to the stacking direction (Z direction), but this is exemplary and may have a structure in which the lower part is wider than the upper part or the upper part is wider than the lower part. . In addition, the first electrode layer 141 , the second electrode layer 145 , the heating electrode layer 147 , the third electrode layer 148 , the selection element layer 143 , and the variable resistance layer 149 are respectively independently upper and lower portions. may have the same or different widths. Such a shape may vary depending on a method of forming each component. For example, the first electrode layer 141 and the selection element layer 143 may be formed through a damascene process so that the upper portion is wider than the lower portion, and the second electrode layer 145 and the heating electrode layer 147 are formed through a damascene process. ), the third electrode layer 148 , and the variable resistance layer 149 may be formed through an embossed etching process to have a structure with side surfaces perpendicular to the substrate 101 .

An insulating layer may be further disposed between the first electrode lines 110 , between the second electrode lines 120 , and/or between the semiconductor devices MC. Specifically, a first insulating layer 160a is formed between the first electrode lines 110 , a second insulating layer 160b is formed between the spaced apart semiconductor devices MC of the semiconductor device layer MCL, and a second electrode is formed. A third insulating layer 160c may be disposed between the lines 120 . The first insulating layer 160a, the second insulating layer 160b, and/or the third insulating layer 160c may include a dielectric material including oxide and/or nitride, and may be formed of the same material or different materials. can be done Also, the first insulating layer 160a, the second insulating layer 160b, and/or the third insulating layer 160c may be an air gap. In this case, an insulating liner (not shown) may be formed between the first electrode lines 110 , the second electrode lines 120 , or the semiconductor device MC and the air gap.

The substrate 101 may be, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or the like. It may include the same semiconductor material, and may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The semiconductor device 100 may further include an interlayer insulating layer 105 on the substrate 101 . The interlayer insulating layer 105 may be disposed between the substrate 101 and the first electrode line layer 110L to electrically separate them. The interlayer insulating layer 105 may include an oxide such as silicon oxide and/or a nitride such as silicon nitride.

The semiconductor device may include two or more semiconductor device layers MCL. Referring to FIG. 4C , the semiconductor device 400 includes a first electrode line layer 110L, a second electrode line layer 120L, a third electrode line layer 130L, and a first semiconductor device layer on a substrate 101 . MCL1 and a second semiconductor device layer MCL2 may be included. The first semiconductor device layer MCL1 may include a plurality of first semiconductor devices MC-1, and the second semiconductor device layer MCL2 may include a plurality of second semiconductor devices MC-2. there is. The first semiconductor device MC-1 includes a first electrode layer 141-1, a selection device layer 143-1, a second electrode layer 145-1, a heating electrode layer 147-1, and a variable resistance layer 149. -1) and a third electrode layer 148-1, and the second semiconductor device MC-2 includes a first electrode layer 141-2, a selection device layer 143-2, and a second electrode layer 145- 2), a heating electrode layer 147 - 2 , a variable resistance layer 149 - 2 and a third electrode layer 148 - 2 may be included. These materials may be substantially the same as those of the first electrode layer 141, the selection element layer 143, the second electrode layer 145, the heating electrode layer 147, the variable resistance layer 149, and the third electrode layer 148 described above. can The first semiconductor device layer MCL1 is disposed between the first electrode line layer 110L and the second electrode line layer 120L, and the second semiconductor device layer MCL2 includes the second electrode line layer 120L and the second electrode line layer 120L. It may be disposed between the three electrode line layers 130L. A fourth insulating layer 160d may be disposed between the second semiconductor device MC-2 and a fifth insulating layer 160e may be disposed between the third electrode lines 130 .

Specifically, the first electrode line layer 110L and the third electrode line layer 130L may extend in the same direction (first direction, X direction) and may be disposed to be spaced apart from each other in the third direction (Z direction). . In addition, the second electrode line layer 120L extends in the second direction (Y direction), and between the first electrode line layer 110L and the third electrode line layer 130L, in the third direction (Z direction). They may be spaced apart from each other. The first semiconductor element layer MCL1 is formed in a portion where they intersect between the first electrode line layer 110L and the second electrode line layer 120L, and the second semiconductor element layer MCL2 is the second electrode line layer 120L. ) and the third electrode line layer 130L may be disposed at an intersection between them. In terms of driving the semiconductor device 400 , the first electrode line layer 110L and the third electrode line layer 130L are word lines (or bit lines), and the second electrode line layer 120L is a common bit line (or common bit line). word line).

Although FIG. 4C illustrates the semiconductor device 400 having two semiconductor device layers MCL1 and MCL2, the number of semiconductor device layers and the number of electrode line layers may be appropriately adjusted according to a desired performance level.

The semiconductor device may further include a driving circuit region on the substrate. Referring to FIG. 4C , the driving circuit region 410 may include circuit parts such as peripheral circuits, driving circuits, and core circuits that drive the semiconductor devices MC-1 and MC-2 or perform arithmetic processing. Such circuits include, for example, a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, and a data in/out circuit. /out circuit) or a row decoder. Also, these circuits may be disposed between the substrate and the semiconductor device layer MCL. In other words, the driving circuit region 410 and the semiconductor device layers MCL1 and MCL2 may be sequentially disposed on the substrate 101 , and such an arrangement structure may be a COP (Cell On Peri) structure.

The driving circuit region 410 may include one or more transistors TR and a wiring structure 414 electrically connected to the transistors TR.

The transistor TR may be disposed on the active region AC of the substrate 101 defined by the device isolation layer 104 . The transistor TR may include a gate G, a gate insulating layer GD, and a source/drain SD. In addition, insulating spacers 106 may be disposed on both sidewalls of the gate G, and an etch stop layer 108 may be disposed on the gate G and/or the insulating spacers 106 . The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

The wiring structures 414 may be disposed in an appropriate number and positions according to the layout of the driving circuit region 410 , the type and arrangement of the gates G, and the like. The wiring structure 414 may have a multi-layer structure of two or more layers. Specifically, the wiring structure 414 includes a first contact 416A, a first wiring layer 418A, a second contact 416B, and a second wiring layer 418B that are electrically connected to each other as shown in FIG. 4C . and may be sequentially stacked on the substrate 101 . The first contact 416A, the first wiring layer 418A, the second contact 416B, and the second wiring layer 418B may each independently be made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof, and a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, or the like.

The wiring structure 414 may include interlayer insulating layers 412A, 412B, and 412C that electrically separate each component. Referring to FIG. 4C , the interlayer insulating layers 412A, 412B, and 412C may be disposed between the plurality of transistors TR, between the plurality of wiring layers 418A and 418B, and/or between the plurality of contacts 416A and 416B. there is. The interlayer insulating layers 412A, 412B, and 412C may include silicon oxide, silicon oxynitride, silicon oxynitride, or the like.

The semiconductor device 400 may further include a wiring structure (not shown) electrically connecting the semiconductor elements MC-1 and MC-2 and the driving circuit region 410, and such a wiring structure (not shown) may be disposed through the interlayer iron layer 105 .

The above-described selection element layer may constitute a switching element together with two electrodes disposed on both sides as shown in FIGS. 3A to 3C . Specifically, the switching element may be used in various technical fields for the purpose of controlling a current flow according to a change in current and/or voltage. for example. The switching element may be used in place of a P-N diode in a technical field where a P-N diode is used. For the two electrodes and the selection element layer of the switching element, the contents of the first electrode layer 141 , the second electrode layer 145 , and the selection element layer 143 of FIG. 4A may be referred to.

In the switching device, the semiconductor device, and/or the semiconductor device according to the embodiments, the threshold voltage V _th is 2.5V or more, 2.6V or more, 2.7V or more, 2.8V or more, 2.9V or more, 3.0V or more, 5.0V or more. or less, 4.9V or less, 4.7V or less, 4.6V or less, or 4.5V or less.

The switching device, the semiconductor device, and/or the semiconductor device according to the embodiments may have excellent durability. For example, the switching element, the semiconductor element, and/or the semiconductor device may have an endurance of 5.0 x 10 ⁷ times or more, 1.0x 10 ⁸ times or more, 5.0x 10 ⁸ times or more, 1.0x 10 ⁹ times or more, or 5.0x10 ⁸ times or more. This endurance characteristic (Endurance) is the threshold voltage (V _th ) of the initial threshold voltage (average threshold voltage for 1000 on-off cycles) using a pulse with a voltage rise and fall time of 10 ns and a width of 100 ns It can be defined as the number of on-off operation possible within ±15%. In addition, the switching element, the semiconductor element, and/or the semiconductor device may have a threshold voltage variation rate (V _th _drift value) of 60 mV/dec or 55 mV/dec or less.

The switching element, the semiconductor element, and/or the semiconductor device may be manufactured according to a conventional method known in the art. 5A to 5C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an exemplary embodiment.

Referring to FIG. 5A , an interlayer insulating layer 105 is formed on a substrate 101 . A first electrode line layer 110L extending in a first direction (X direction) and including a plurality of first electrode lines 110 spaced apart from each other is formed on the interlayer insulating layer 105 . The first electrode line layer 110L may be formed by forming a conductive layer for the first electrode line and patterning it through etching. A first insulating layer 160a may be filled between the first electrode lines 110 . The first insulating layer 160a may be formed by filling a space between the first electrode lines 110 with an insulating material and planarizing the top surfaces of the first electrode lines 110 through a CMP process or the like to the extent that they are exposed. On the first electrode line layer 110L and the first insulating layer 160a, the material layer 141k for the first electrode, the material layer 143k for the selection element, the material layer 145k for the second electrode, and the heating electrode A stacked structure 140k is formed by sequentially stacking the material layer 147k, the variable resistance material layer 149k, and the third electrode material layer 148k.

Referring to FIG. 5B , a mask pattern (not shown) spaced apart from each other in a first direction (X direction) and a second direction (Y direction) is formed on the stacked structure 140k, and the first insulating layer ( 160a) and the upper surfaces of the first electrode lines 110 are etched to expose a portion of the stacked structure 140k. A plurality of semiconductor devices MC spaced apart from each other in the first direction and the second direction may be manufactured according to the structure of the mask pattern. The plurality of semiconductor devices MC include a first electrode layer 141 , a selection device layer 143 , a second electrode layer 145 , a heating electrode layer 147 , a variable resistance layer 149 , and a third electrode layer 148 , respectively. and may be electrically connected to the first electrode lines 110 . Also, the remaining mask pattern may be removed through an ashing and a strip process.

Referring to FIG. 5C , a second insulating layer 160b may be filled between the plurality of semiconductor devices MC. A second electrode line layer 120L extending in the second direction (X direction) and including a plurality of second electrode lines 120 spaced apart from each other is formed on the semiconductor device MC and the second insulating layer 160b. to form A third insulating layer 160c may be filled between the second electrode lines 120 .

First, second electrode lines 110, 120, first, second, and third electrode layers 141, 145, 148, heating electrode layer 147, insulating layers 105, 160a, 160b, 160c, selection element layer 143, Each component such as the variable resistance layer 149 may be formed through a method known in the art. Each of these components may be independently formed to have a desired composition and thickness through deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. For example, the material layer 143k for the selection device may be formed on the first electrode layer 141 through a physical vapor deposition (PVD) or sputtering process to form a first element, a second element, a third element, and a fifth element. It may be formed by sequentially using a source or target including a source or target and a source or target including the first element, the second element, the third element, and the fourth element.

In addition, each of these components may be independently patterned through methods known in the art. Specifically, in addition to the patterning method described above, a damascene method may be used. For example, when the second electrode lines 120 are formed by a damascene process, an insulating material layer is thickly formed between and on the plurality of semiconductor devices MC, and then the trench is formed by etching the insulating material layer. to form The trench may be formed to extend in the second direction and expose a top surface of the variable resistance layer 149 . The second electrode lines 120 may be formed by filling and planarizing the trench with a conductive material. The second insulating layer 160b and the third insulating layer 160c may be formed in a one-body type.

Hereinafter, the technical contents of the semiconductor device will be described in more detail through the implemented embodiments. However, the following examples are for illustrative purposes only and do not limit the scope of rights.

Example 1

The first electrode layer was formed by DC sputtering or ALD method.

A selection element layer was formed on the first electrode layer by sputtering. Specifically, a first chalcogen compound layer is formed on the first electrode layer using a target including germanium (Ge), arsenic (As), and selenium (Se), and indium (In), germanium (Ge) A second chalcogen compound layer was formed using a target including , arsenic (As), and selenium (Se). As a result, indium (In) in the selection element layer may have a higher concentration at a position adjacent to the second electrode layer than at a position adjacent to the first electrode layer.

A second electrode layer was formed on the selection element layer by DC sputtering or ALD method.

Example 2

A semiconductor device was manufactured in the same manner as in Example 1, except that the order of introduction of the target was changed when the selection device layer was formed. Specifically, a first chalcogen compound layer is formed on the first electrode layer using a target including indium (In), germanium (Ge), arsenic (As), and selenium (Se), and germanium (Ge) A second chalcogen compound layer was formed using a target including , arsenic (As), and selenium (Se). As a result, indium (In) in the selection element layer may have a higher concentration at a position adjacent to the first electrode layer than at a position adjacent to the second electrode layer.

Comparative Example 1

The same method as in Example 1, except that the selection device layer was formed using only a target including germanium (Ge), arsenic (As), and selenium (Se) without changing the composition of the target during the manufacturing process. to fabricate a semiconductor device.

Comparative Example 2

Without changing the composition of the target during the manufacturing process, except that the selection device layer was formed using only a target including indium (In), germanium (Ge), arsenic (As), and selenium (Se), A semiconductor device was manufactured in the same manner as in Example 1.

Electrical Characteristics Evaluation 1

For the semiconductor devices of Examples 1, 2, Comparative Example 1, and Comparative Example 2, threshold voltage (V _th ), off current (I _off ), threshold voltage change rate (V _th _drift), and durability (Endurance) ) properties were measured and described in Table 1.

Referring to Table 1, the semiconductor devices of Examples 1 and 2 had a high threshold voltage (V _th ) at a level similar to that of Comparative Examples 1 and/or 2 and durability characteristics ( Endurance) was shown. In addition, the semiconductor devices of Examples 1 and 2 have an excellent threshold voltage change rate (V _th _drift) compared to Comparative Example 1, and the semiconductor device of Example 1 has a lower off-current value (I _off ) compared to Example 2 ) was shown.

Threshold voltage (V _th )
(V) off current (I _off )
(A) Rate of change of threshold voltage (V _th _drift) Endurance Example 1 3.28 7.15E-10 53.83 1.00E+9 Example 2 3.23 1.30E-9 56.84 5.28E+8 Comparative Example 1 3.5 5.87E-10 127.10 3.00E+8 Comparative Example 2 3.25 1.25E-0.9 48.65 1.00E+8

Although the embodiments have been described in detail above, the scope of the rights is not limited thereto, and various modifications and improved forms of those skilled in the art using the basic concepts defined in the following claims also belong to the scope of the rights.

100, 400: semiconductor device, MC, MC-1, MC- 2: semiconductor device
141: a first electrode layer, 145: a second electrode layer;
148: a third electrode layer, 147: a heating electrode layer;
143, SW: selection element layer, 149, ME: variable resistance layer
143a, 143b, 143c, SW1, SW2: chalcogen compound layer
110: first electrode line, 120: second electrode line

Claims (34)

a first electrode;
a second electrode spaced apart from the first electrode, and
Comprising a first chalcogen compound layer and a second chalcogen compound layer disposed between the first electrode and the second electrode,
The first chalcogen compound layer and the second chalcogen compound layer are each independently selected from the group consisting of germanium (Ge) and tin (Sn) and at least one first element selected from the group consisting of sulfur (S), selenium (Se) and tellurium ( Te) comprising at least one second element selected from the group consisting of,
The first chalcogen compound layer and the second chalcogen compound layer is a semiconductor device having a different composition. The method of claim 1,
A semiconductor device exhibiting ovonic threshold switching characteristics. The method of claim 1,
The first chalcogen compound layer is a semiconductor device having a larger energy band gap than the second chalcogen compound layer. The method of claim 1,
The first chalcogenide compound layer has an energy bandgap of 0.1eV or more and 1.0eV or less larger than that of the second chalcogenide compound layer. The method of claim 1,
Any one or more of the first chalcogen compound layer and the second chalcogen compound layer are each independently selected from the group consisting of arsenic (As), antimony (Sb), silicon (Si) and bismuth (Bi). A semiconductor device further comprising three elements. The method of claim 1,
The second chalcogen compound layer contains at least one fourth element selected from the group consisting of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In). Further comprising a semiconductor device. The method of claim 1,
The first chalcogen compound layer is a semiconductor device further comprising at least one fifth element selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S). The method of claim 1,
The second chalcogen compound layer is a semiconductor device comprising a compound of Formula 1 or Formula 2.
[Formula 1]
A _a B _b C _c
[Formula 2]
A _a B _b C _c D _d
In Formula 1 or Formula 2, A is a first element, B is a second element, C is a third element, and D is a fourth element, a+b+c=1 in Formula 1, a+b+ in Formula 2 c + d = 1. The method of claim 1,
The first chalcogen compound layer is a semiconductor device comprising one of the compounds of Formula 1, Formula 3, and Formula 4.
[Formula 1]
A _a B _b C _c
[Formula 3]
A _a B _b
[Formula 4]
A _a B _b C _c E _e
In Formula 1, Formula 3, or Formula 4, A is a first element, B is a second element, C is a third element, and E is a fifth element, in Formula 1, a+b+c=1, in Formula 3 a+b=1, in Formula 4, a+b+c+e=1. The method of claim 1,
The second chalcogen compound layer is a semiconductor device having a volume ratio of 0.1 times or more and 1.5 times or less compared to the first chalcogen compound layer. The method of claim 1,
A semiconductor device further comprising a third chalcogen compound layer disposed adjacent to the second chalcogen compound layer and spaced apart from the first chalcogen compound layer. 12. The method of claim 11,
The third chalcogen compound layer is a semiconductor device comprising at least one of the following Chemical Formula 1, Chemical Formula 3, and Chemical Formula 4.
[Formula 1]
A _a B _b C _c
[Formula 3]
A _a B _b
[Formula 4]
A _a B _b C _c E _e
In Formula 1, Formula 3, or Formula 4, A is a first element, B is a second element, C is a third element, and E is a fifth element, in Formula 1, a+b+c=1, in Formula 3 a+b=1, in Formula 4, a+b+c+e=1. 12. The method of claim 11,
The third chalcogen compound layer is a semiconductor device having a larger energy band gap than the second chalcogen compound layer. a first electrode;
a second electrode spaced apart from the first electrode, and
and a chalcogen compound layer disposed between the first electrode and the second electrode,
The chalcogen compound layer is
At least one first element selected from the group consisting of germanium (Ge) and tin (Sn), and at least one second element selected from the group consisting of sulfur (S), selenium (Se) and tellurium (Te), arsenic (As), antimony (Sb), silicon (Si), and at least one third element selected from the group consisting of bismuth (Bi), and boron (B), aluminum (Al), scandium (Sc), manganese ( A semiconductor device comprising at least one fourth element selected from the group consisting of Mn), strontium (Sr), and indium (In), wherein the fourth element has a concentration gradient in the thickness direction of the chalcogen compound layer. 15. The method of claim 14,
The calogen compound layer further includes at least one fifth element selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur (S), the fifth element is a semiconductor device having a concentration gradient in the thickness direction of the chalcogen compound layer. 16. The method of claim 15,
The concentration gradient of the fifth element is in a direction opposite to the concentration gradient of the fourth element. The method of claim 1,
a variable resistance layer and a selection element layer disposed to be electrically connected to the variable resistance layer;
The selection device layer is a semiconductor device comprising the first chalcogen compound layer and the second chalcogen compound layer. 18. The method of claim 17,
The second chalcogenide compound layer is a semiconductor device disposed adjacent to the variable resistance layer compared to the first chalcogenide compound layer. 18. The method of claim 17,
Further comprising a third electrode,
A semiconductor device in which the selection element layer is disposed between the first electrode and the second electrode, and the variable resistance layer is disposed between the second electrode and the third electrode. 20. The method of claim 19,
The first chalcogen compound layer is a semiconductor device disposed adjacent to the first electrode compared to the second chalcogen compound layer. 20. The method of claim 19,
The first electrode, the second electrode and the third electrode are each independently carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride A semiconductor device comprising at least one from the group consisting of lithium (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN). 18. The method of claim 17,
The variable resistance layer includes a material capable of reversibly changing a phase between crystalline and amorphous according to temperature change. 23. The method of claim 22,
The variable resistance layer includes at least one of Te and Se, and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, B, O and C. A semiconductor device comprising this combined compound. 24. The method of claim 23,
The variable resistance layer includes aluminum (Al), zinc (Zn), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), Palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), and polonium (Po) comprising one or more from the group consisting of semiconductor device. 23. The method of claim 22,
The semiconductor device further comprising a heating electrode layer disposed in contact with the variable resistance layer. 18. The method of claim 17,
The variable resistance layer may include a material whose electrical resistance can be reversibly changed according to an externally applied voltage. 27. The method of claim 26,
The variable resistance layer includes an oxide of at least one metal selected from the group consisting of Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr. 18. The method of claim 17,
The variable resistance layer includes a material whose polarization state can be reversibly changed according to an externally applied voltage. 29. The method of claim 28,
The variable resistance layer includes niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO((Pr,Ca)MnO3), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, and barium - A semiconductor device comprising at least one perovskite compound selected from the group consisting of -strontium-zirconium oxide (barium-strontium-zirconium oxide). 18. The method of claim 17,
The variable resistance layer includes a material whose magnetization state can be reversibly changed according to an externally applied voltage. 31. The method of claim 30,
The variable resistance layer includes two electrodes made of a magnetic material, and a dielectric interposed between the two electrodes. a plurality of first electrode lines formed on the substrate, parallel to the upper surface of the substrate and extending in a first direction;
a plurality of second electrode lines formed on the plurality of first electrode lines and extending in a second direction parallel to the upper surface of the substrate and different from the first direction; and
A semiconductor device comprising a; a first semiconductor element disposed between the plurality of first electrode lines and the plurality of second electrode lines at their crossing points, the first semiconductor element comprising the semiconductor element of claim 1 . 33. The method of claim 32,
a plurality of third electrode lines formed on the plurality of first and second electrode lines and extending in the first direction; and
A semiconductor device further comprising a; a second semiconductor device disposed between the plurality of second electrode lines and the plurality of third electrode lines at intersections thereof, the second semiconductor device including the semiconductor device of claim 1 . 33. The method of claim 32,
The semiconductor device further comprising a circuit unit for driving the semiconductor element or performing an arithmetic process.

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