KR20220050580A - Semiconductor devices - Google Patents

Abstract

A semiconductor device includes: an active pattern formed on a substrate; a gate structure buried over the active pattern; a bit line structure formed on the active pattern and stacked with an insulating capping pattern including a conductive structure and a nitride; a spacer structure formed on a sidewall of the bit line structure; a contact plug structure formed on the active pattern and contacting the spacer structure; and a capacitor formed on the contact plug structure. The spacer structure includes an air spacer containing air. The uppermost end of the air spacer may be higher than a top surface of the bit line structure. According to the present invention, the cell sensing margin may be increased through CBL reduction, and thus the characteristics of a DRAM device may be improved.

Description

semiconductor device

The present invention relates to a semiconductor device. More particularly, the present invention relates to a DRAM device.

Due to the recent miniaturization of DRAM devices, a problem of increasing bit line loading capacity (CBL) may occur as an interval between bit lines is narrowed. Accordingly, the DRAM device may include an air spacer containing air to reduce CBL, and a method of forming the air spacer to have a sufficient size is required.

An object of the present invention is to provide a semiconductor device having improved characteristics.

According to exemplary embodiments of the present invention, a semiconductor device includes an active pattern formed on a substrate, a gate structure buried over the active pattern, and a conductive structure and a nitride formed on the active pattern. a bit line structure having an insulating capping pattern stacked thereon, a spacer structure formed on sidewalls of the bit line structure, a contact plug structure formed on the active pattern to contact the spacer structure, and a capacitor formed on the contact plug structure, , the spacer structure may include an air spacer containing air, and an uppermost end of the air spacer may be higher than a top surface of the bit line structure.

A semiconductor device according to other exemplary embodiments for achieving the object of the present invention includes an active pattern formed on a substrate, a gate structure buried over the active pattern, and a conductive structure and a nitride formed on the active pattern. a bit line structure having an insulating capping pattern stacked thereon; a spacer structure formed on sidewalls of the bit line structure; a contact plug structure formed on the active pattern to contact the spacer structure; and a capacitor formed on the contact plug structure. and an interlayer insulating structure partially penetrating an upper portion of the contact plug structure, an upper portion of the spacer structure, and an upper portion of the bit line structure, wherein the spacer structure includes an air spacer containing air, and the bit line The air spacer, the interlayer insulating structure, the air spacer, and the contact plug structure may be sequentially disposed from the insulating capping pattern of the structure in a horizontal direction parallel to the upper surface of the substrate.

In the semiconductor device according to the exemplary embodiments, since the air spacer formed on the sidewall of the bit line structure has a top higher than the top surface of the bit line structure, a vertical cross-sectional area facing the sidewall of the bit line structure may be sufficiently large. there is. Accordingly, CBL due to the bit line structure can be effectively reduced.

Furthermore, it is possible to increase a cell sensing margin through the reduction of the CBL, and consequently, the characteristics of the DRAM device may be improved.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 and 2 are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments.
3 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
4 to 19 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.
20 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to example embodiments.

Hereinafter, a semiconductor device and a method of manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. When a material, layer (film), region, pad, electrode, pattern, structure or process is referred to herein as “first,” “second,” and/or “third,” it is not intended to define such members. Rather, it is merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Thus, “first,” “second,” and/or “third” may be used selectively or interchangeably, respectively, for each material, layer (film), region, electrode, pad, pattern, structure, and process, respectively. .

[Example]

1 and 2 are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments. In this case, FIG. 2 includes cross-sections taken along lines A-A' and B-B' of FIG. 1 .

In the following detailed description of the invention, two directions parallel to the upper surface of the substrate and perpendicular to each other are defined as first and second directions, respectively, and an acute angle parallel to the upper surface of the substrate and each of the first and second directions is defined as an acute angle. A direction formed is defined as a third direction, and a direction parallel to the upper surface of the substrate and perpendicular to the third direction is defined as a fourth direction.

1 and 2 , the semiconductor device may include a gate structure 160 , a bit line structure 325 , a spacer structure, a contact plug structure, and a capacitor 540 formed on a substrate 100 . In addition, the semiconductor device may further include a second capping pattern 410 , an insulating structure, an etch stop layer 500 , an interlayer insulating structure, and a third interlayer insulating layer 550 .

The substrate 100 may include silicon, germanium, silicon-germanium, or a group III-V compound such as GaP, GaAs, or GaSb. According to some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

A device isolation pattern 110 may be formed on the substrate 100 , and an active pattern 105 having a sidewall surrounded by the device isolation pattern 110 may be defined on the substrate 100 . The device isolation pattern 110 may include, for example, an oxide such as silicon oxide.

In example embodiments, a plurality of active patterns 105 may be formed to be spaced apart from each other in each of the first and second directions, and each of the active patterns 105 may have a predetermined length in the third direction. can be extended

The gate structure 160 may extend in the first direction through upper portions of the active pattern 105 and the device isolation pattern 110 formed on the substrate 100 and may be spaced apart from each other in the second direction. It may be formed in plurality as possible. That is, the gate structure 160 may be buried in the upper portions of the active pattern 105 and the device isolation pattern 110 . The gate structure 160 may include a gate insulating layer 130 , a gate electrode 140 , and a gate mask 150 sequentially stacked in a vertical direction perpendicular to the top surface of the substrate 100 .

The gate insulating layer 130 may be formed on the surface of the active pattern 105 , and the gate electrode 140 may extend on the gate insulating layer 130 and the device isolation pattern 110 in the first direction. , the gate mask 150 may cover the upper surface of the gate electrode 140 .

The gate insulating layer 130 may include, for example, an oxide such as silicon oxide, and the gate electrode 140 is, for example, a metal such as tungsten (W), titanium (Ti), or tantalum (Ta), Alternatively, it may include a metal nitride such as tungsten nitride, titanium nitride, or tantalum nitride, and the gate mask 150 may include, for example, a nitride such as silicon nitride.

In example embodiments, the bit line structure 325 may extend along the second direction on the active pattern 105 , the device isolation pattern 110 , and the gate structure 160 , in the first direction. It may be formed in plurality so as to be spaced apart from each other. In this case, each of the bit line structures 325 may contact the upper surface of the middle portion of the active pattern 105 in the third direction.

The bit line structure 325 may extend in the vertical direction, and a conductive structure 265 , a diffusion barrier 295 , a fourth conductive pattern 305 , and a first capping pattern are sequentially stacked in the vertical direction. (315).

The conductive structure 265 may include sequentially stacked second and third conductive patterns 245 and 255 (refer to FIGS. 9 and 10 ) or sequentially stacked first and third conductive patterns 215 and 255 ( FIGS. 9 and 10 ). 10) may be included. In this case, a plurality of second conductive patterns 245 may be formed to be spaced apart from each other in each of the first and second directions. That is, each of the second conductive patterns 245 may be formed in the second recess 230 formed on the upper surface of the active pattern 105 , the device isolation pattern 110 adjacent thereto, and the upper surface of the gate mask 150 . In addition, the first conductive pattern 215 may be formed outside the second recess 230 .

The third conductive pattern 255 may extend in the second direction on the first and second conductive patterns 215 and 245 disposed in the second direction. In example embodiments, each of the first to third conductive patterns 215 , 245 , and 255 may include, for example, polysilicon doped with n-type impurities, and thus merge with each other to form a conductive structure (265) may be formed.

Each of the diffusion barrier 295 , the fourth conductive pattern 305 , and the first capping pattern 315 may extend on the third conductive pattern 255 in the second direction. The diffusion barrier 295 may include, for example, a metal silicon nitride such as titanium silicon oxide (TiSiN), and the fourth conductive pattern 305 may include, for example, tungsten, copper, aluminum, titanium, tantalum, or the like. It may include a metal, and the first capping pattern 315 may include, for example, a nitride such as silicon nitride.

The spacer structure may be formed on both sidewalls of the bit line structure 325 , and thus may extend in the second direction. The spacer structure includes a first spacer 335 , an air spacer 365 , a third spacer 385 , and a fourth spacer sequentially stacked in the first direction from both sidewalls of the bit line structure 325 . (425).

The first spacer 335 may contact a sidewall of the bit line structure 325 in the first direction, and the air spacer 365 may contact a partial outer wall of the first spacer 335 , and the third The spacer 385 may contact the outer wall of the air spacer 365 , and the fourth spacer 425 is formed on the upper surface of the first capping pattern 315 , the upper surface of the first spacer 335 and the upper surface of the outer wall, and the air spacer ( 365 , a portion of the top surface of the third spacer 385 , and an upper portion of the outer wall may be in contact. However, in a partial region, that is, in a region where the sidewall of the bit line structure 325 in the first direction is surrounded by the second capping pattern 410 , the air spacer 365 and the third spacer 385 may They may be sequentially stacked on the outer wall of the spacer 335 in the first direction, and the fourth spacer 425 may not be formed.

In addition, the air spacer 365 may contact the sidewall of the first interlayer insulating layer 480 and the contact plug structure, and partially penetrate the upper portion of the first spacer 335 and the upper portion of the first capping pattern 315 . can do.

In example embodiments, the top of the air spacer 365 may be higher than the top surface of the bit line structure 325 and the top surface of the first, third, and fourth spacers 335 , 385 , and 425 , and the first The top surface of the spacer 335 may be higher than the top surface of the third spacer 385 .

Each of the first, third, and fourth spacers 335 , 385 , and 425 may include, for example, a nitride such as silicon nitride, and the air spacer 365 may include air.

A sidewall of a portion of the bit line structure 325 formed in the second recess 230 and a bottom surface of the second recess 230 may be covered by the first spacer 335 . In this case, a fourth insulating pattern 340 may be formed on the portion of the first spacer 335 in the second recess 230 , and the remaining portion of the second recess 230 may be formed on the fourth insulating pattern 340 . A filling fifth insulating pattern 350 may be formed. In example embodiments, the air spacer 365 may contact the upper surfaces of the fourth and fifth insulating patterns 340 and 350 , and the third spacer 385 may be disposed on the fifth insulating pattern 350 . may be in contact with the upper surface.

Meanwhile, between the portion of the active pattern 105 and the portion of the device isolation pattern 110 in which the second recess 230 is not formed, and the bit line structure 325 , the first to second sequentially stacked portions in the vertical direction are formed. An insulating pattern structure including three insulating patterns 175 , 185 , and 195 structures may be formed. In this case, the second insulating pattern 185 may contact the bottom of the first spacer 335 having an “L”-shaped cross-section, and the third insulating pattern 195 may be disposed on the bottom of the bit line structure 325 . can be contacted

Each of the first, third, and fifth insulating patterns 175 , 195 , and 350 may include, for example, a nitride such as silicon nitride, and the second and fourth insulating patterns 185 and 340 , respectively For example, it may include an oxide such as silicon oxide.

The second capping pattern 410 may extend in the first direction to overlap the gate structure 160 in the vertical direction, and may be formed on a sidewall of the bit line structure 325 in the first direction. The outer wall may be partially covered. In example embodiments, a plurality of second capping patterns 410 may be formed to be spaced apart from each other at regular intervals along the second direction. The second capping pattern 410 may include, for example, a nitride such as silicon nitride.

The contact plug structure may include a lower contact plug 405 , an ohmic contact pattern 435 , a barrier layer 450 , and an upper contact plug 465 sequentially stacked in the vertical direction.

The lower contact plug 405 includes the active pattern 105 and the device between the bit line structures 325 adjacent to each other in the first direction and the second capping patterns 410 adjacent to each other in the second direction. It may be formed on the third recess 390 formed on the separation pattern 110 , and may contact the outer wall of the third spacer 385 of the spacer structure and the sidewall of each of the second capping patterns 410 . there is. Accordingly, a plurality of lower contact plugs 405 may be formed to be spaced apart from each other in each of the first and second directions. In an embodiment, the uppermost surface of the lower contact plug 405 may be lower than the uppermost surface of the third spacer 385 .

The lower contact plug 405 may include, for example, polysilicon doped with impurities. Meanwhile, an air gap (not shown) may be formed inside the lower contact plug 405 .

The ohmic contact pattern 435 may be formed on the lower contact plug 405 . The ohmic contact pattern 435 may include, for example, cobalt silicide or nickel silicide.

The barrier layer 450 may be formed on the top surface of the ohmic contact pattern 435 and sidewalls and top surfaces of the fourth spacer 425 . The barrier layer 450 may include, for example, a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride.

The upper contact plug 465 may be formed on the barrier layer 450 . A top surface of the upper contact plug 465 may be higher than a top surface of the bit line structure 325 and the second capping pattern 410 .

In example embodiments, the upper contact plug 465 may be arranged in a honeycomb shape when viewed from above. Each of the upper contact plugs 465 may have a circular, oval, or polygonal shape when viewed from above. The upper contact plug 465 may include, for example, a low-resistance metal such as tungsten (W), aluminum (Al), or copper.

The interlayer insulating structure may partially penetrate the contact plug structure and the spacer structure, and accordingly, a plurality of upper contact plugs 465 may be formed to be spaced apart from each other in each of the first and second directions. The interlayer insulating structure is formed on a first interlayer insulating layer 480 surrounding one sidewall of an upper portion of the air spacer 365 and a second interlayer insulating layer 490 formed on the first interlayer insulating layer 480 and surrounding an uppermost end of the air spacer 365 . ) may be included.

In example embodiments, the uppermost surface of the first interlayer insulating film 480 may be higher than the lowermost surface of the second interlayer insulating film 490 , and accordingly, air from the first capping pattern 315 along the first direction A spacer 365 , a first interlayer insulating layer 480 , an air spacer 365 , and an upper contact plug 465 may be sequentially disposed.

In example embodiments, a lower portion of the first interlayer insulating layer 480 may include an upper portion of the third spacer 385 , an upper portion of the fourth spacer 425 , the barrier film 450 , and/or the upper contact plug 465 . can be contacted with

In example embodiments, the first interlayer insulating layer 480 may include silicon nitride, and the second interlayer insulating layer 490 may include, for example, silicon carbonitride having a low gap-fill characteristic. It may include an insulating material.

The capacitor 540 may include a lower electrode 510 , a dielectric layer 520 , and an upper electrode 530 sequentially stacked on the upper contact plug 465 . The lower electrode 510 and the upper electrode 530 may include substantially the same material as each other, for example, doped polysilicon and/or metal. The dielectric layer 520 may include an oxide such as silicon oxide or metal oxide and/or a nitride such as silicon nitride or metal nitride, wherein the metal is aluminum (Al), zirconium (Zr), titanium (Ti), It may include hafnium (Hf) and the like.

The etch stop layer 500 may be formed between the first and second interlayer insulating layers 480 and 490 and the dielectric layer 520 , and may include, for example, a nitride such as silicon nitride.

The third interlayer insulating layer 550 may be formed on the first and second interlayer insulating layers 480 and 490 to cover the capacitor 540 , and may include, for example, an oxide such as silicon oxide.

In the semiconductor device, the air spacer 365 may be formed to face most of the sidewalls of the bit line structure 325 , and in particular, the uppermost end thereof may be higher than the top surface of the bit line structure 325 . Accordingly, since the vertical cross-sectional area of the air spacer 365 facing the sidewall of the bit line structure 325 may have a sufficient size, bit line loading capacity (CBL) may be effectively reduced.

Furthermore, it is possible to increase a cell sensing margin by reducing the CBL, and consequently, the characteristics of the semiconductor device may be improved.

3 is a cross-sectional view illustrating a semiconductor device according to example embodiments. The semiconductor device is substantially the same as or similar to the semiconductor device described with reference to FIGS. 1 and 2 except for the air spacer and the first interlayer insulating layer.

Referring to FIG. 3 , the air spacer 365 may be formed to surround the lowermost surface of the first interlayer insulating layer 480 , so that a lower portion of the first interlayer insulating layer 480 is an upper portion of the third spacer 385 . , may not contact the upper portion of the fourth spacer 425 , the barrier layer 450 , and/or the upper contact plug 465 .

4 to 19 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. Specifically, FIGS. 4, 6, 9 and 13 are plan views, and FIGS. 5, 7, 10-12 and 14-19 are cross-sections taken along lines A-A' and B-B' of the corresponding respective plan views. include

4 and 5 , active patterns 105 may be formed on the substrate 100 , and device isolation patterns 110 covering sidewalls of the active patterns 105 may be formed.

Thereafter, an impurity region (not shown) is formed on the substrate 100 by, for example, performing an ion implantation process, and then the active pattern 105 and the device isolation pattern 110 are partially etched in the first direction. A first recess extending to .

Thereafter, a gate structure 160 may be formed in the first recess. The gate structure 160 is formed on the gate insulating layer 130 formed on the surface of the active pattern 105 exposed by the first recess and the gate insulating layer 130 and filling the lower portion of the first recess. It may include an electrode 140 and a gate mask 150 formed on the gate electrode 140 and filling an upper portion of the first recess. In this case, the gate structures 160 may extend along the first direction and may be formed in plurality to be spaced apart from each other along the second direction.

The gate insulating layer 130 may be formed through a thermal oxidation process on the surface of the active pattern 105 exposed by the first recess.

6 and 7 , an insulating film structure 200 , a first conductive film 210 , and a first mask 220 are sequentially formed on a substrate 100 , and the first mask 220 is used as an etch mask. The first hole 230 exposing the active pattern 105 may be formed by etching the lower first conductive layer 210 and the insulating layer structure 200 by performing the used etching process.

In example embodiments, the insulating film structure 200 may include sequentially stacked first to third insulating films 170 , 180 , and 190 .

The first conductive layer 210 may include, for example, polysilicon doped with n-type impurities.

During the etching process, the active pattern 105 exposed by the first hole 230 and the upper portion of the device isolation pattern 110 adjacent thereto, and the upper portion of the gate mask 150 are also etched to form a second second surface on these upper surfaces. A recess may be formed. That is, the bottom surface of the first hole 230 may also be referred to as a second recess.

In example embodiments, the first hole 230 may expose an upper surface of a central portion of each of the active patterns 105 extending in the third direction, and thus the first and second directions are formed in each of the first and second directions. Accordingly, it may be formed in plurality.

Thereafter, a second conductive layer 240 filling the first hole 230 may be formed.

In example embodiments, the second conductive layer 240 is formed on the active pattern 105 , the device isolation pattern 110 , the gate mask 150 , and the first hole 230 on the first mask 220 . It may be formed by forming the second preliminary conductive layer filling the ?, and then removing the upper portion of the preliminary second conductive layer through a CMP process and/or an etch-back process. Accordingly, the second conductive layer 240 may be formed to have a top surface positioned at substantially the same height as the top surface of the first conductive layer 210 .

In example embodiments, a plurality of second conductive layers 240 may be formed along each of the first and second directions. The second conductive layer 240 may include, for example, polysilicon doped with n-type impurities, and may be combined with the first conductive layer 210 .

Referring to FIG. 8 , after the first mask 220 is removed, the third conductive layer 250 , the diffusion barrier layer 290 , and the fourth conductive layer are formed on the first and second conductive layers 210 and 240 . 300 and the first capping layer 310 may be sequentially formed.

The third conductive layer 250 may include, for example, polysilicon doped with n-type impurities, and may be combined with the first and second conductive layers 210 and 240 .

9 and 10 , a first capping pattern 315 may be formed by patterning the first capping layer 310 , and the fourth conductive layer 300 and the diffusion barrier layer 290 may be used as an etch mask. ), the third conductive layer 250 , the first and second conductive layers 210 and 240 , and the third insulating layer 190 may be sequentially etched.

In example embodiments, a plurality of first capping patterns 315 may be formed on the substrate 100 to extend in the second direction and to be spaced apart from each other in the first direction.

As the etching process is performed, the second conductive pattern 245 and the third conductive pattern are sequentially stacked on the active pattern 105 , the device isolation pattern 110 , and the gate mask 150 in the first hole 230 . A pattern 255 , a diffusion barrier 295 , a fourth conductive pattern 305 , and a first capping pattern 315 may be formed, and the second insulating layer ( 180), a third insulating pattern 195, a first conductive pattern 215, a third conductive pattern 255, a diffusion barrier 295, a fourth conductive pattern 305, and a first capping pattern ( 315) may be formed.

As described above, the first to third conductive layers 210 , 240 , and 250 may be merged with each other, and accordingly, the second and third conductive patterns 245 and 255 , and the first and third conductive patterns 245 and 255 sequentially stacked Each of the third conductive patterns 215 and 255 may form one conductive structure 265 . Hereinafter, the sequentially stacked conductive structure 265 , the diffusion barrier 295 , the fourth conductive pattern 305 , and the first capping pattern 315 will be referred to as a bit line structure 325 .

In example embodiments, the bit line structure 325 may extend in the second direction on the substrate 100 and may be formed in plurality to be spaced apart from each other along the first direction. In this case, each of the bit line structures 325 may contact and be electrically connected to a middle portion of each of the corresponding active patterns 105 in the third direction through the first hole 230 .

Referring to FIG. 11 , the upper surface of the active pattern 105 , the isolation pattern 110 , and the gate mask 150 exposed by the first hole 230 in the first spacer layer covering the bit line structure 325 ; After forming on the sidewall of the first hole 230 and the second insulating layer 180 , fourth and fifth insulating layers may be sequentially formed on the first spacer layer.

The first spacer layer may also cover a sidewall of the third insulating pattern 195 under the bit line structure 325 formed on the second insulating layer 180 , and the fifth insulating layer may cover the first hole 230 . It can be formed to fill all.

Thereafter, an etching process may be performed to etch the fourth and fifth insulating layers. In example embodiments, the etching process may be performed by a wet etching process, and all portions of the fourth and fifth insulating layers other than a portion in the first hole 230 may be removed. Accordingly, most of the surface of the first spacer layer, that is, all portions of the second spacer layer other than the portion formed in the first hole 230 may be exposed, and the fourth and fourth remaining in the first hole 230 may be exposed. The portions of the five insulating layers may form fourth and fifth insulating patterns 340 and 350 , respectively.

Thereafter, a second spacer layer is formed on the exposed surface of the first spacer layer and the fourth and fifth insulating patterns 340 and 350 formed in the first hole 230 , and then anisotropically etched to form a bit line structure ( A second spacer 360 covering the sidewall of the 325 may be formed on the surface of the first spacer layer and on the fourth and fifth insulating patterns 340 and 350 .

The second spacer layer may include, for example, an oxide such as silicon oxide.

Thereafter, a dry etching process using the first capping pattern 315 and the second spacer 360 as an etching mask may be performed to form the first opening 370 exposing the upper surface of the active pattern 105 , A top surface of the device isolation pattern 110 and a top surface of the gate mask 150 may also be exposed through the first opening 370 .

By the dry etching process, the portion of the first spacer layer formed on the top surface of the first capping pattern 315 and the top surface of the second insulating layer 180 may be removed, and accordingly, the sidewall of the bit line structure 325 is covered. A first spacer 335 may be formed. In addition, in the dry etching process, the first and second insulating layers 170 and 180 are also partially removed to remain as first and second insulating patterns 175 and 185 under the bit line structure 325 , respectively. can The first to third insulating patterns 175 , 185 , and 195 sequentially stacked under the bit line structure 325 may form an insulating pattern structure.

12 , the upper surface of the first capping pattern 315 , the outer wall of the second spacer 360 , a portion of the upper surface of the fourth and fifth insulating patterns 340 and 350 , and the first opening 370 are exposed. A third spacer layer is formed on the upper surfaces of the active pattern 105 , the device isolation pattern 110 , and the gate mask 150 , and the third spacer 385 is anisotropically etched to cover the sidewall of the bit line structure 325 . can form.

The first to third spacers 335 , 360 , and 385 sequentially stacked on the sidewall of the bit line structure 325 on the substrate 100 in a horizontal direction parallel to the top surface of the substrate 100 together form a preliminary spacer structure. may be referred to.

Thereafter, by performing an etching process to etch the upper portion of the active pattern 105 , the third recess 390 communicating with the first opening 370 may be formed.

Thereafter, after forming the lower contact plug layer 400 filling the first opening 370 and the third recess 390 formed on the substrate 100 to a sufficient height, the upper surface of the first capping pattern 315 is The top can be planarized until exposed.

In example embodiments, the lower contact plug layer 400 may extend in the second direction, and a plurality of lower contact plug layers 400 may be formed to be spaced apart from each other by the bit line structures 325 in the first direction. .

13 and 14 , a second mask (not shown) each extending in the first direction and having a plurality of second openings spaced apart from each other in the second direction is formed by a first capping pattern 315 and a lower portion thereof. The lower contact plug layer 400 may be etched by performing an etching process formed on the contact plug layer 400 and using it as an etch mask.

In example embodiments, each of the second openings may overlap the gate structure 160 in a direction perpendicular to the top surface of the substrate 100 . As the etching process is performed, a third opening exposing the top surface of the gate mask 150 of the gate structure 160 may be formed between the bit line structures 325 on the substrate 100 .

After removing the second mask, a second capping pattern 410 filling the third opening may be formed on the substrate 100 . In example embodiments, the second capping pattern 410 may extend between the bit line structures 325 in the first direction, and may be formed in plurality along the second direction.

Accordingly, the lower contact plug layer 400 extending in the second direction between the bit line structures 325 is a plurality of lower contacts spaced apart from each other in the second direction by the second capping patterns 410 . may be converted into plugs 405 . In this case, each of the lower contact plugs 405 may contact both ends of the corresponding respective active patterns 105 in the third direction to be electrically connected thereto.

15 , after the upper portion of the lower contact plug 405 is removed to expose the upper portion of the preliminary spacer structure formed on the sidewall of the bit line structure 325 , the second and third portions of the exposed preliminary spacer structure are exposed. The upper portions of the spacers 360 and 385 may be removed.

Thereafter, the upper portion of the lower contact plug 405 may be additionally removed. Accordingly, the upper surface of the lower contact plug 405 may be lower than the upper surface of the second and third spacers 360 and 385 .

Thereafter, a fourth spacer layer is formed on the bit line structure 325 , the preliminary spacer structure, the second capping pattern 410 , and the lower contact plug 405 and anisotropically etched, thereby forming the bit line structure 325 . A fourth spacer 425 may be formed to cover the first to third spacers 335 , 360 , and 385 formed on both sidewalls in the first direction, and thus the upper surface of the lower contact plug 405 may be may be exposed.

Thereafter, an ohmic contact pattern 435 may be formed on the exposed upper surface of the lower contact plug 405 . In example embodiments, the ohmic contact pattern 435 is formed by heat-treating a metal film on the lower contact plug 405 , the fourth spacer 425 , and the first and second capping patterns 315 and 410 . Thereafter, it may be formed by removing an unreacted portion of the metal film.

Referring to FIG. 16 , a barrier layer 450 is formed on the fourth spacer 425 , the ohmic contact pattern 435 , and the first and second capping patterns 315 and 410 , and the barrier layer 450 is formed. After forming the upper contact plug layer 460 sufficiently filling the space between the bit line structures 325 , the upper portion thereof may be planarized.

In example embodiments, a top surface of the upper contact plug layer 460 may be higher than a top surface of the first and second capping patterns 315 and 410 .

Referring to FIG. 17 , the upper contact plug layer 460 , a portion of the barrier layer 450 , the first capping pattern 315 , and the first to fourth spacers 335 , 360 , 385 and 425 are formed. It may be removed to form a second hole 470 .

As the second hole 470 is formed, the upper contact plug layer 460 may be converted into an upper contact plug 465 . In example embodiments, a plurality of upper contact plugs 465 may be formed to be spaced apart from each other in each of the first and second directions, and may be arranged in a honeycomb shape when viewed from above. Each of the upper contact plugs 465 may have a circular, oval, or polygonal shape when viewed from the top.

The lower contact plug 405 , the ohmic contact pattern 435 , the barrier layer 450 , and the upper contact plug 465 sequentially stacked on the substrate 100 may together form a contact plug structure.

Thereafter, after forming a sacrificial layer on the upper contact plug 465 and the second hole 470 , an etching process is performed on the sacrificial layer to form an upper surface of the upper contact plug 465 and a lower portion of the second hole 470 . A sacrificial pattern 475 covering the upper surface of the second spacer 360 may be formed by exposing a portion thereof.

The sacrificial layer may include, for example, an oxide such as silicon oxide, and thus may include substantially the same material as the second spacer 360 .

In example embodiments, a top surface of the sacrificial pattern 475 may be formed to be higher than a top surface of the bit line structure 325 .

Referring to FIG. 18 , after a preliminary first interlayer insulating layer filling the second hole 470 is formed on the sacrificial pattern 475 and the upper contact plug 465 , an upper portion of the preliminary first interlayer insulating layer is removed. An interlayer insulating layer 480 may be formed, and in this case, an upper portion of the sacrificial pattern 475 may also be partially removed. The first interlayer insulating layer 480 may also be formed on the second capping pattern 410 .

In example embodiments, an upper portion of the preliminary first interlayer insulating layer may be removed by a CMP process and/or an etch-back process.

In example embodiments, a lower surface of the first interlayer insulating layer 480 may be convex downward, and an upper surface thereof may be concave upward. Also, the first interlayer insulating layer 480 may be formed to surround one sidewall of the sacrificial pattern 475 but not to cover the top surface of the sacrificial pattern 475 , so that the top surface of the sacrificial pattern 475 is exposed. can

Referring to FIG. 19 , the exposed sacrificial pattern 475 and the second spacer 360 may be removed to form an air gap 365 communicating with the second hole 470 . The sacrificial pattern 475 and the second spacer 360 may be removed together by, for example, a wet etching process.

In the drawings, it is shown that the top end of the air gap 365 has a sharp shape, but the concept of the present invention is not necessarily limited thereto.

Thereafter, after forming a second preliminary interlayer insulating layer filling the second hole 470 on the first interlayer insulating layer 480 and the air gap 365 , the upper portion of the preliminary second interlayer insulating layer is removed to form the air gap 365 . ), a second interlayer insulating film 490 surrounding the uppermost end may be formed. The second interlayer insulating layer 490 may also be stacked on the first interlayer insulating layer 480 formed on the second capping pattern 410 . Accordingly, the first and second interlayer insulating layers 480 and 490 may form an interlayer insulating structure together.

In example embodiments, an upper portion of the preliminary second interlayer insulating layer may be removed by a CMP process and/or an etch-back process.

In example embodiments, the second interlayer insulating layer 490 may be formed using a material having a low gap-fill property. Accordingly, the air gap 365 may not be filled or may remain as only the upper portion is filled, and the uppermost end of the air gap 36 may still be higher than the upper surface of the bit line structure 325 .

In this case, the air gap 365 may be referred to as an air spacer 365 , and may form a spacer structure together with the first, third, and fourth spacers 335 , 385 , and 425 . That is, the air gap 365 may be a spacer including air.

Referring back to FIGS. 1 and 2 , a capacitor 540 in contact with the upper surface of the upper contact plug 465 may be formed.

That is, an etch stop layer 500 and a mold layer (not shown) are sequentially formed on the upper contact plug 465 and the second interlayer insulating layer 490 and partially etched to form the upper contact plug 465 . A third hole partially exposing the upper surface may be formed.

A lower electrode layer (not shown) is formed on the sidewall of the third hole, the exposed upper surface of the upper contact plug 465, and the mold layer, and a sacrificial layer (not shown) sufficiently filling the remaining portion of the third hole. After forming on the lower electrode layer, the lower electrode layer may be node-separated by planarizing upper portions of the lower electrode layer and the sacrificial layer until the top surface of the mold layer is exposed. The remaining sacrificial layer and the mold layer may be removed by, for example, performing a wet etching process, and thus a cylindrical lower electrode 510 is formed on the exposed upper surface of the upper contact plug 465 . can be Alternatively, a pillar-shaped lower electrode 510 may be formed to completely fill the third hole.

Thereafter, a dielectric layer 520 is formed on the surface of the lower electrode 510 and the etch stop layer 500 , and an upper electrode 530 is formed on the dielectric layer 520 , thereby forming the lower electrode 510 and the dielectric layer 520 . ) and a capacitor 540 each including an upper electrode 530 may be formed.

Thereafter, the semiconductor device may be completed by forming a third interlayer insulating layer 550 covering the capacitor 540 on the substrate 100 .

When the air spacer 365 is formed to face only a part of the sidewall of the bit line structure 325 rather than the entire sidewall of the bit line structure 325 , the vertical cross-sectional area of the air spacer 365 facing the sidewall of the bit line structure 325 is sufficient. CBL can be large because it cannot have a size. Also, even when process dispersion occurs in which some of the bit line structures 325 are formed to have a relatively low height or some of the second holes 470 are formed to have a relatively deep depth, the air spacer 365 is CBL may be large because it cannot have sufficient vertical cross-sectional area.

However, in exemplary embodiments, as the air spacer 365 has a high top surface to completely cover the upper sidewall of the bit line structure 325 , the second interlayer insulating layer 490 is formed on the air spacer 365 . Since the air spacer 365 may have a sufficient vertical cross-sectional area even if it fills an upper part of the CBL, it is possible to effectively reduce the CBL. In addition, even if the above-described process dispersion occurs, the air spacer 365 may have a sufficient vertical cross-sectional area, so that the process margin may be improved.

20 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to example embodiments. Since the manufacturing method of the semiconductor device includes processes substantially the same as or similar to those described with reference to FIGS. 3 to 19 , detailed descriptions thereof will be omitted.

Referring to FIG. 20 , after a sacrificial layer is formed on the upper contact plug 465 and the second hole 470 , an etching process is performed on the sacrificial layer to expose the top surface of the upper contact plug 465 , 2 A sacrificial pattern 475 covering the upper surface of the spacer 360 may be formed.

The semiconductor device described with reference to FIG. 3 may be completed through the above-described processes.

Although described with reference to preferred embodiments of the present invention as described above, those of ordinary skill in the art can variously modify and modify the present invention within the scope without departing from the spirit and scope of the present invention as described in the claims. You will understand that it can be changed.

100: substrate 105: active pattern
110: device isolation pattern 130: gate insulating layer
140: gate electrode 150: gate mask
160: gate structure
170, 180, 190: first to third insulating layers
175, 185, 195, 340, 350: first to fifth insulating patterns
200: insulating film structure
210, 240, 250, 300: first to fourth conductive layers
215, 245, 255, 305: first to fourth conductive patterns
220: first mask 230, 390: second and third recesses
230 and 470: first and second holes 265: conductive structure
290: diffusion barrier film 295: diffusion barrier
310: first capping layer 315, 410: first and second capping patterns
325: bit line structure
335, 360, 385, 425: first to fourth spacers
365: air spacer
370: first opening
400, 460: lower and upper contact plug membranes
405, 465: lower and upper contact plugs
435: ohmic contact pattern 450: barrier film
475: sacrifice pattern
480, 490, 550: first to third interlayer insulating layers
500: etch stop layer 510: lower electrode
520: dielectric layer 530: upper electrode
540: capacitor

Claims (10)

an active pattern formed on the substrate;
a gate structure buried over the active pattern;
a bit line structure formed on the active pattern and stacked with an insulating capping pattern including a conductive structure and a nitride;
a spacer structure formed on a sidewall of the bit line structure;
a contact plug structure formed on the active pattern and contacting the spacer structure; and
a capacitor formed on the contact plug structure;
The spacer structure includes an air spacer containing air, and an uppermost end of the air spacer is higher than a top surface of the bit line structure. 2 . The spacer structure of claim 1 , wherein the spacer structure includes first to third spacers sequentially stacked from a sidewall of the bit line structure in a horizontal direction parallel to the upper surface of the substrate, and wherein the air spacer comprises the second spacer. is,
The uppermost surface of the first spacer is lower than the uppermost end of the second spacer and higher than the uppermost surface of the third spacer. 3 . The spacer structure of claim 2 , further comprising a fourth spacer contacting the first to third spacers, covering an upper surface of the bit line structure, and contacting the contact plug structure;
The uppermost end of the second spacer is higher than the uppermost surface of the fourth spacer. The semiconductor device of claim 2 , wherein the first, third, and fourth spacers include nitride. The method of claim 1 , further comprising: an interlayer insulating structure partially penetrating the contact plug structure and the spacer structure;
The interlayer insulating structure is
a first interlayer insulating film surrounding one sidewall of an upper portion of the air spacer; and
and a second interlayer insulating layer formed on the first interlayer insulating layer and surrounding an uppermost end of the air spacer. The semiconductor device of claim 5 , wherein an uppermost surface of the first interlayer insulating film is higher than a lowermost surface of the second interlayer insulating film. The semiconductor device of claim 5 , wherein the air spacer surrounds a lowermost surface of the first interlayer insulating layer. an active pattern formed on the substrate;
a gate structure buried over the active pattern;
a bit line structure formed on the active pattern and stacked with an insulating capping pattern including a conductive structure and a nitride;
a spacer structure formed on a sidewall of the bit line structure;
a contact plug structure formed on the active pattern and contacting the spacer structure; and
a capacitor formed on the contact plug structure;
an interlayer insulating structure partially penetrating an upper portion of the contact plug structure, an upper portion of the spacer structure, and an upper portion of the bit line structure;
The spacer structure includes an air spacer containing air,
The air spacer, the interlayer insulating structure, the air spacer, and the contact plug structure are sequentially disposed from the insulating capping pattern of the bit line structure in a horizontal direction parallel to a top surface of the substrate. The method of claim 8, wherein the interlayer insulating structure
a first interlayer insulating film surrounding one sidewall of an upper portion of the air spacer; and
a second interlayer insulating film formed on the first interlayer insulating film and surrounding the uppermost end of the air spacer;
The uppermost surface of the first interlayer insulating film is higher than the lowermost surface of the second interlayer insulating film, and thus the air spacer, the first interlayer insulating film, the air spacer and the air spacer along the horizontal direction from the insulating capping pattern of the bit line structure A semiconductor device in which the contact plug structures are sequentially disposed. 9. The method of claim 8, wherein the spacer structure includes first to third spacers sequentially stacked along the horizontal direction from a sidewall of the bit line structure, and contacting the first to third spacers and contacting the bit line a fourth spacer covering an upper surface of the structure and contacting the contact plug structure, wherein the air spacer is the second spacer;
The uppermost surface of the first spacer is lower than the uppermost end of the second spacer and higher than the uppermost surface of the third spacer,
The uppermost end of the second spacer is higher than the uppermost surface of the fourth spacer.

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