KR20210112872A - Data Storage Apparatus and Operation Method Thereof - Google Patents

Abstract

According to an embodiment of the present invention, a data storage device includes: a storage configured to store data; and a controller configured to perform a normal read operation based on a default read voltage in accordance with a read request of a host device and to perform a read retry operation using at least one retry read voltage when the normal read operation fails. The controller is configured to determine a workload according to a hit ratio table which stores read success performance by retry read voltage according to the workload and a normal read operation failure, and select the retry read voltage in an order of the highest hit ratio in the determined workload. The present invention provides the data storage device capable of improving a read speed and the operating method thereof.

Description

Data Storage Apparatus and Operation Method Thereof

The present technology relates to a semiconductor integrated device, and more particularly, to a data storage device and an operating method thereof.

The data storage device is connected to the host device and performs data input/output operations according to the request of the host.

The data storage device may perform a read operation according to a read request from the host, detect and correct errors included in the read data, and provide the read data to the host device.

A program/erase cycle of a flash memory device is closely related to reliability, and a method for reducing read latency while ensuring reliability of the memory device is required.

Embodiments of the present technology may provide a data storage device capable of improving a read speed and an operating method thereof.

A data storage device according to an embodiment of the present technology includes a storage unit for storing data; and a controller that performs a normal read operation based on a default read voltage according to a read request from a host, and performs a read retry operation using at least one retry read voltage when the normal read operation fails. The controller may include: a hit ratio table configured to store a read success performance for each retry read voltage according to a workload as a hit ratio; and determining the workload according to the failure of the normal read operation, and selecting the retry read voltage in the order of the highest hit ratio from the determined workload.

A data storage device according to an embodiment of the present technology includes a storage unit for storing data; and a controller controlling the storage unit, wherein the controller includes: a read retry table configured to store a plurality of retry read voltages; a hit ratio table for storing read success rates for each of the plurality of retry read voltages according to a workload; and a read voltage determiner configured to determine a workload when a normal read operation using the default read voltage fails, and select a read voltage based on a hit ratio for each retry read voltage of the determined workload. .

An operating method of a data storage device according to an embodiment of the present technology is an operating method of a data storage device including a storage unit in which data is stored and a controller controlling the storage unit, wherein the controller controls a retry read voltage according to a workload. performing, by the controller, a normal read operation based on a default read voltage in response to a read request from a host, including a hit ratio table in which each read success record is stored as a hit ratio; and performing, by the controller, a read retry operation using at least one retry read voltage when the normal read operation fails, wherein the read retry operation is performed by the controller as the normal read operation fails. determining the workload; selecting a retry read voltage in the order of the highest hit ratio in the workload; and a retry step of reading data by providing the selected retry read voltage to the storage unit.

According to the present technology, reliability and operation speed of the data storage device may be improved by performing a read operation with a read voltage optimized for the workload of the data storage device.

1 is a block diagram of a data storage device according to an exemplary embodiment.
2 is a configuration diagram of a controller according to an embodiment.
3 is a block diagram of a read voltage determiner according to an exemplary embodiment.
4 is a block diagram of a read retry table according to an embodiment.
5 is a configuration diagram of a hit ratio table according to an embodiment.
6 is a flowchart illustrating a method of operating a data storage device according to an exemplary embodiment.
7 is a configuration diagram of a storage system according to an exemplary embodiment.
8 and 9 are block diagrams of data processing systems according to embodiments.
10 is a configuration diagram of a network system including a data storage device according to an embodiment.
11 is a block diagram of a nonvolatile memory device included in a data storage device according to an exemplary embodiment.

Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of a data storage device according to an exemplary embodiment.

Referring to FIG. 1 , a data storage device 10 according to an embodiment may include a controller 110 and a storage unit 120 .

The controller 110 may control the storage unit 120 in response to a request from the host device. For example, the controller 110 may program data in the storage unit 120 according to a program (write) request from the host device. In addition, data recorded in the storage unit 120 may be provided to the host device in response to a read request from the host device. In an embodiment, the controller 110 selects a read voltage based on a read retry table (RRT, 210 ) and a hit ratio table (HRT, 220 ) and provides it to the storage unit 120 . and a read voltage determiner 20 to

The storage unit 120 may record data or output recorded data under the control of the controller 110 . The storage unit 120 may be configured as a volatile or non-volatile memory device. In an embodiment, the storage unit 120 includes an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), and a ferroelectric (FRAM). RAM) and STT-MRAM (Spin Torque Transfer Magnetic RAM) may be implemented using a memory device selected from among various non-volatile memory devices.

The storage unit 120 may include a plurality of non-volatile memory devices (NVMs) 121 to 12n, and each of the non-volatile memory devices 121 to 12n includes a plurality of dies, or a plurality of chips, or a plurality of non-volatile memory devices (NVMs) 121 to 12n. Packages may be included. Furthermore, the storage unit 120 is a single-level cell that stores one bit of data in one memory cell, or a multi-level cell that stores multiple bits of data in one memory cell. ) can be made.

The storage unit 120 may cause read errors due to changes in retention characteristics, read disturb, and cell characteristics in the execution of repeated programs and read operations of the memory devices 121 to 12n constituting the storage unit 120 . have.

The controller 110 may detect and correct (ECC) an error of data read from the storage unit 120 according to a read command, and perform ECC operation while changing the read voltage when an error check and correction (ECC) failure occurs. A read retry operation may be performed to find the read voltage passed.

For this, the controller 110 may refer to the RRT 210 . The RRT 210 may be a table storing a plurality of retry read voltage levels. In an embodiment, the RRT 210 may manage a plurality of retry read voltages to be applied during a read retry operation according to an index, and the controller 110 may sequentially change the retry read voltages according to a set index order. . The retry read voltage may consist of one voltage value in the case of SLC, and may be a set of a plurality of read voltage values in the case of MLC.

The RRT 210 may be stored in the storage unit 120 , and may be loaded into the controller 110 when the data storage device 10 is driven. The controller 110 may determine a retry read voltage to be used in a read retry operation based on the loaded RRT 210 . The determined retry read voltage is transmitted to the storage unit 120 through, for example, a set parameter operation, and the storage unit 120 stores the transmitted retry read voltage value in a register to perform a read retry operation. Can be used.

When data read from the storage unit 120 is transferred to the controller 110 , the controller 110 may correct an error by an ECC operation. When an error is corrected from the read data by the ECC operation, the read operation is successful, and the error-corrected data may be provided from the controller 110 to the host. When the ECC operation fails, the controller 110 may change the retry read voltage with reference to the RRT 210 and transmit it to the storage unit 120 . The storage unit 120 transmits the read data using the changed retry read voltage to the controller 110 , and the controller 110 may correct an error by an ECC operation. This process may be repeated until the read operation is successful or until all retry read voltage values of the RRT 210 are applied.

The HRT 220 may be a hit ratio table for each retry read voltage according to the workload of the data storage device 10 . The HRT 220 reflecting the initial hit ratio determined through experiments, etc. may be stored in the storage unit 120 and shipped, and as the data storage device 10 operates, the HRT 220 may be updated.

The read voltage determiner 20 may provide a default read voltage to the storage unit 120 in response to a read request from the host to perform a normal read operation. In the following description, a read operation performed using a default read voltage is referred to as a normal read operation, and after the normal read operation fails, a read retry performed using a retry read voltage that is a read voltage of a different level from the default read voltage is used. to distinguish it from action.

The read voltage determiner 20 determines a supply order of the retry read voltage stored in the RRT 210 when a normal read operation or a preceding read retry operation fails, and stores the retry read voltage according to the determined order. (120) can be provided.

In an embodiment, the read voltage determiner 20 may determine the workload of the data storage device 10 during a read operation, preferably, when a normal read operation fails. The workload may mean a characteristic or amount of work to be processed by the data storage device 10 for a predetermined time. The workload may be random or sequential access, data transfer size, ratio of read/write operations, or a combination thereof.

The read voltage determiner 20 may select a retry read voltage from the HRT 220 in the order of the highest hit ratio in the workload based on the determined workload and provide it to the storage unit 120 . The read voltage determiner 20 may update the HRT 220 by calculating a hit ratio for each retry read voltage in the corresponding workload as the read retry operation is successful. The hit ratio for each retry read voltage may be a value representing a read retry success performance of each retry read voltage.

In one embodiment, the read voltage determiner 20 may further determine the wear level of the storage unit 120 in addition to the workload, calculate the hit ratio for each read voltage according to the workload and the wear level, and update the HRT 220 . can do. The degree of wear may be determined based on the number of programs/erases and/or the number of reads, but is not limited thereto.

In summary, when a normal read operation is performed using a default read voltage in response to a read request from the host, but an ECC failure occurs, a read retry may be performed. During the read retry operation, the read voltage determining unit 20 determines the current workload, and sequentially selects the retry read voltages in the order of the highest hit ratio in the workload situation determined by referring to the HRT 220 to select the storage unit ( 120) can be transferred. The hit ratio for each workload and retry read voltage managed by the HRT 220 may be updated whenever a read retry operation is performed.

The read latency of the data storage device 10 is affected by the performance level of the storage unit 120 , the overhead of the data storage device 10 including the controller 110 , and how quickly the read retry process succeeds. .

The voltage at which the read operation succeeds may vary depending on the workload of the host or the degree of deterioration of the memory cells constituting the storage unit 120. If the application order of the retry read voltage is fixed, there is a limit to improving the read latency. have.

In the present technology, the success time of the read retry may be advanced by determining the workload and changing the application order of the retry read voltage based on the determination of the workload. As the number of read retries is reduced, stress applied to the memory cell is also reduced, thereby extending the lifespan of the data storage device 10 .

2 is a configuration diagram of a controller according to an embodiment.

Referring to FIG. 2 , the controller 110 according to an embodiment includes a processor 111 , a host interface 113 , a ROM 1151 , a RAM 1153 , an ECC 117 , a memory interface 119 , and a read voltage. A decision unit 20 may be included.

The processor 111 transmits various control information necessary for reading or writing data to the storage unit 120 , the host interface 113 , the RAM 1153 , the ECC 117 , the memory interface 119 , and the read voltage determining unit. 20 . In an embodiment, the processor 111 may operate according to firmware provided for various operations of the data storage device 10 . In an embodiment, the processor 111 may perform functions of a flash translation layer (FTL) for performing garbage collection, address mapping, wear leveling, and the like for managing the storage unit 120 .

When the processor 111 receives a write command and a logical address from the host, the processor 111 allocates a physical address corresponding to the logical address, and writes data to the storage area of the storage unit 120 corresponding to the physical address. can be controlled.

When a read command and logical address are received from the host, a read operation of searching for a physical address corresponding to the logical address and reading data from the storage area of the storage unit 120 corresponding to the physical address can be controlled. have.

The host interface 113 may provide a communication channel for receiving a command and a clock signal from the host device and controlling input/output of data under the control of the processor 111 . In particular, the host interface 113 may provide a physical connection between the host device and the data storage device 10 . In addition, interfacing with the data storage device 10 may be provided corresponding to the bus format of the host device. The bus format of the host device is secure digital, universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), and parallel advanced technology attachment (PATA). ), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), universal flash storage (UFS) It may include at least any one of the protocols.

The ROM 1151 may store program codes necessary for the operation of the controller 110 , for example, firmware or software, and may store code data used by the program codes.

The RAM 1153 may store data necessary for the operation of the controller 110 or data generated by the controller 110 .

The ECC 117 may detect and correct an error in data read from the storage 120 .

The memory interface 119 may provide a communication channel for signal transmission/reception between the controller 110 and the storage unit 120 . The memory interface 119 may write data temporarily stored in the buffer memory 130 to the storage unit 120 under the control of the processor 111 . In addition, data read from the storage unit 120 may be temporarily stored in the buffer memory 130 .

The read voltage determiner 20 may determine the workload of the data storage device 10 when the normal read operation performed by the default read voltage in response to the host's read request fails. Then, in the workload situation determined by referring to the RRT 210 and the HRT 220 , the retrie read voltage selected in the order of the highest read retrie success rate is provided to the storage unit 120 to perform a retrie read operation. can do. As the read retry operation is performed, the read voltage determiner 20 may update information of the HRT 220 , that is, a hit ratio for each retry read voltage according to a workload.

3 is a block diagram of a read voltage determiner according to an exemplary embodiment.

Referring to FIG. 3 , the read voltage determiner 20 may include a workload determiner 230 , a read voltage selector 240 , and an HRT updater 250 .

The workload determining unit 230 may determine the workload of the data storage device 10 when the normal read operation fails. The workload may be divided into sequential reads (SEQ), random reads (RND), small reads (SML), and the like. The sequential read (SEQ) may refer to a read operation using a logical address immediately after the last logical address of a preceding read operation as a starting point. The random read (RND) may refer to a read operation other than a sequential read (SEQ). Small read (SML) is when the size of the data to be read is smaller than the set size. For example, it may refer to a read operation having a size smaller than the page buffer size of the flash memory device.

The read voltage selector 240 may be configured to select a retry read voltage with reference to the RRT 210 and the HRT 220 in order to perform a read retry operation because the normal read operation fails.

In an embodiment, the HRT 220 may store the hit ratio for each retry read voltage according to the workload, and the read voltage selector 240 selects the HRT 220 according to the determination result of the workload determiner 230 . In the workload determined by reference, the retry read voltage may be selected from the RRT 210 in the order of the highest hit ratio according to the hit ratio for each retry read voltage.

The HRT updater 250 may update the hit ratio of the HRT 220 according to a result of the read retry operation.

4 is a block diagram of a read retry table according to an embodiment.

Referring to FIG. 4 , the RRT 210 may store a plurality of retry read voltages RV to be applied during a read retry operation according to an index ID.

The read voltage determiner 20 may sequentially change the retry read voltage according to the set index order, for example, in the ascending order of the index (ID1→ID2→ID3→...→IDk). When the storage unit 120 operates as an SLC, the retry read voltage may consist of a single voltage value, and when the storage unit 120 operates as an MLC, the retry read voltage may be a set of a plurality of read voltage values.

5 is a configuration diagram of a hit ratio table according to an embodiment.

The HRT 220 may be a hit ratio table for each retry read voltage according to the workload of the data storage device 10 . In one embodiment, the HRT 220 may store the hit ratios (HR11 to HR1k, HR21 to HR2k, HR31 to HR3k) for each index (ID1 to IDk) of the retry read voltage according to the workload (SEQ, RND, SML). have.

When the storage unit 120 is shipped, the HRT 220 reflecting the initial hit ratio may be stored in the storage unit 120 . As the data storage device 10 operates, the HRT 220 may be updated by the HRT updater 250 .

6 is a flowchart illustrating a method of operating a data storage device according to an exemplary embodiment.

Referring to FIG. 6 , the controller 110 may provide a default read voltage to the storage unit 120 in response to a read request from the host ( S101 ) to control the normal read operation to be performed ( S103 ).

The controller 110 may receive the data read from the storage 120 and perform ECC decoding to determine whether the read operation is successful ( S105 ).

When the read operation passes (S105:Y), the controller 110 may provide error-corrected read data to the host (S107).

When the read operation fails (S105:N), the controller 110 may determine the workload of the data storage device 10 (S109). Then, based on the determined workload, the retry read voltage may be selected from the HRT 220 in the order of the highest hit ratio in the corresponding workload and transferred to the storage unit 120 ( S111 ). As the read retry operation is performed in the storage unit 120 ( S113 ), the controller 110 receives the data read by the read retry operation and performs ECC decoding to check whether the read retry operation is successful. There is (S115).

When the read retry operation is successful ( S115 : Y ), the controller 110 may provide error-corrected read data to the host ( S117 ). In addition, the HRT 220 may be updated by calculating the hit ratio for each retry read voltage in the corresponding workload (S119).

When the read retry operation fails (S115:N), when the read retry operation succeeds (S115:Y), when all the retry read voltage values of the RRT 210 are applied The read retry operation ( S111 to S115 ) reflecting the workload can be repeated until the

The number of read retries can be minimized by determining the order of providing the retrie read voltages based on the hit ratio according to the workload.

7 is a configuration diagram of a storage system according to an exemplary embodiment.

Referring to FIG. 7 , the storage system 1000 may include a host device 1100 and a data storage device 1200 . In one embodiment, the data storage device 1200 may be configured as a solid state drive (SSD).

The data storage device 1200 includes a controller 1210 , nonvolatile memory devices 1220-0 to 1220-n, a buffer memory device 1230 , a power supply 1240 , a signal connector 1101 , and a power connector 1103 . ) may be included.

The controller 1210 may control overall operations of the data storage device 1200 . The controller 1210 may include a host interface unit, a control unit, a random access memory as an operation memory, an error correction code (ECC) unit, and a memory interface unit. For example, the controller 1210 may include the controller 110 illustrated in FIGS. 1 to 6 .

The host device 1100 and the data storage device 1200 may transmit/receive signals through the signal connector 1101 . Here, the signal may include a command, an address, and data.

The controller 1210 may analyze and process a signal input from the host device 1100 . The controller 1210 may control the operation of the background function blocks according to firmware or software for driving the data storage device 1200 .

The buffer memory device 1230 may temporarily store data to be stored in the nonvolatile memory devices 1220-0 to 1220-n. Also, the buffer memory device 1230 may temporarily store data read from the nonvolatile memory devices 1220-0 to 1220-n. Data temporarily stored in the buffer memory device 1230 may be transmitted to the host device 1100 or the nonvolatile memory devices 1220-0 to 1220-n under the control of the controller 1210 .

The nonvolatile memory devices 1220 - 0 to 1220 - n may be used as storage media of the data storage device 1200 . Each of the nonvolatile memory devices 1220-0 to 1220-n may be connected to the controller 1210 through a plurality of channels CH0 to CHn. One or more nonvolatile memory devices may be connected to one channel. Nonvolatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 1240 supplies power input through the power connector 1103 to the controller 1210 of the data storage device 1200 , the nonvolatile memory devices 1220-0 to 1220-n, and the buffer memory 1230 . can provide The power supply 1240 may include an auxiliary power supply 1241 . The auxiliary power supply 1241 may supply power so that the data storage device 1200 can be normally terminated when a sudden power off occurs. The auxiliary power supply 1241 may include, but is not limited to, large capacity capacitors.

It is obvious that the signal connector 1101 may be configured in various types of connectors according to an interface method between the host device 1100 and the data storage device 1200 .

Of course, the power connector 1103 may be configured in various types of connectors according to the power supply method of the host device 1100 .

8 and 9 are block diagrams of data processing systems according to embodiments.

Referring to FIG. 8 , the data processing system 3000 may include a host device 3100 and a memory system 3200 .

The host device 3100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 3100 may include background function blocks for performing a function of the host device.

The host device 3100 may include a connection terminal 3110 such as a socket, a slot, or a connector. The memory system 3200 may be mounted on the access terminal 3110 .

The memory system 3200 may be configured in the form of a substrate such as a printed circuit board. The memory system 3200 may be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210 , a buffer memory device 3220 , nonvolatile memory devices 3231 to 3232 , a power management integrated circuit (PMIC) 3240 , and a connection terminal 3250 .

The controller 3210 may control overall operations of the memory system 3200 .

The controller 3210 may be configured substantially the same as the controller 110 illustrated in FIGS. 1 to 6 .

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 to 3232 . Also, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3231 to 3232 . Data temporarily stored in the buffer memory device 3220 may be transmitted to the host device 3100 or the nonvolatile memory devices 3231 to 3232 under the control of the controller 3210 .

The nonvolatile memory devices 3231 to 3232 may be used as storage media of the memory system 3200 .

The PMIC 3240 may provide power input through the access terminal 3250 to the background of the memory system 3200 . The PMIC 3240 may manage power of the memory system 3200 under the control of the controller 3210 .

The access terminal 3250 may be connected to the access terminal 3110 of the host device. Signals such as commands, addresses, data, etc. and power may be transmitted between the host device 3100 and the memory system 3200 through the connection terminal 3250 . The access terminal 3250 may be configured in various forms according to an interface method between the host device 3100 and the memory system 3200 . The connection terminal 3250 may be disposed on one side of the memory system 3200 .

9 is a diagram exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 9 , the data processing system 4000 may include a host device 4100 and a memory system 4200 .

The host device 4100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 4100 may include background function blocks for performing a function of the host device.

The memory system 4200 may be configured in the form of a surface mount type package. The memory system 4200 may be mounted on the host device 4100 through a solder ball 4250 . The memory system 4200 may include a controller 4210 , a buffer memory device 4220 , and a nonvolatile memory device 4230 .

The controller 4210 may control overall operations of the memory system 4200 . The controller 4210 may be configured substantially the same as the controller 110 illustrated in FIGS. 1 to 6 .

The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230 . Also, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory devices 4230 . Data temporarily stored in the buffer memory device 4220 may be transmitted to the host device 4100 or the nonvolatile memory device 4230 under the control of the controller 4210 .

The nonvolatile memory device 4230 may be used as a storage medium of the memory system 4200 .

10 is a configuration diagram of a network system including a data storage device according to an embodiment.

Referring to FIG. 10 , a network system 5000 may include a server system 5300 and a plurality of client systems 5410 to 5430 connected through a network 5500 .

The server system 5300 may service data in response to requests from a plurality of client systems 5410 to 5430 . For example, the server system 5300 may store data provided from a plurality of client systems 5410 to 5430 . As another example, the server system 5300 may provide data to a plurality of client systems 5410 to 5430 .

The server system 5300 may include a host device 5100 and a memory system 5200 . The memory system 5200 may include the data storage device 10 of FIG. 1 , the data storage device 1200 of FIG. 7 , the memory system 3200 of FIG. 8 , and the memory system 4200 of FIG. 9 .

11 is a block diagram of a nonvolatile memory device included in a data storage device according to an exemplary embodiment.

Referring to FIG. 11 , the nonvolatile memory device 300 includes a memory cell array 310 , a row decoder 320 , a data read/write block 330 , a column decoder 340 , a voltage generator 350 , and control logic. (360).

The memory cell array 310 may include memory cells MC arranged in a region where the word lines WL1 to WLm and the bit lines BL1 to BLn cross each other.

The memory cell array 310 may include a three-dimensional memory array. The 3D memory array has a direction perpendicular to the flat surface of the semiconductor substrate, and refers to a structure including a NAND string in which at least one memory cell is positioned vertically above the other memory cell. However, the structure of the three-dimensional memory array is not limited thereto, and it is obvious that a memory array structure formed at high density with horizontal as well as vertical directionality can be selectively applied.

The row decoder 320 may be connected to the memory cell array 310 through word lines WL1 to WLm. The row decoder 320 may operate under the control of the control logic 360 . The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 may select and drive the word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 may provide the word line voltage provided from the voltage generator 350 to the word lines WL1 to WLm.

The data read/write block 330 may be connected to the memory cell array 310 through bit lines BL1 to BLn. The data read/write block 330 may include read/write circuits RW1 to RWn corresponding to each of the bit lines BL1 to BLn. The data read/write block 330 may operate under the control of the control logic 360 . The data read/write block 330 may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block 330 may operate as a write driver that stores data provided from an external device in the memory cell array 310 during a write operation. As another example, the data read/write block 330 may operate as a sense amplifier that reads data from the memory cell array 310 during a read operation.

The column decoder 340 may operate under the control of the control logic 360 . The column decoder 340 may decode an address provided from an external device. The column decoder 340 includes the read/write circuits RW1 to RWn of the data read/write block 330 corresponding to each of the bit lines BL1 to BLn and the data input/output line (or data input/output) based on the decoding result. buffer) can be connected.

The voltage generator 350 may generate a voltage used for a background operation of the nonvolatile memory device 300 . Voltages generated by the voltage generator 350 may be applied to memory cells of the memory cell array 310 . For example, a program voltage generated during a program operation may be applied to word lines of memory cells on which a program operation is to be performed. As another example, an erase voltage generated during an erase operation may be applied to a well region of memory cells to be erased. As another example, a read voltage generated during a read operation may be applied to word lines of memory cells to be read.

The control logic 360 may control general operations of the nonvolatile memory device 300 based on a control signal provided from an external device. For example, the control logic 360 may control read, write, and erase operations of the nonvolatile memory device 300 .

As such, those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

10: data storage device
110: controller
120: storage
20: read voltage determining unit

Claims (11)

a storage unit for storing data; and
a controller that performs a normal read operation based on a default read voltage according to a read request from a host, and performs a read retry operation using at least one retry read voltage when the normal read operation fails
The controller may include: a hit ratio table configured to store a read success performance for each retry read voltage according to a workload as a hit ratio; and
a read voltage determiner configured to determine a workload according to the failure of the normal read operation, and select a retry read voltage in the order of the highest hit ratio from the determined workload;
A data storage device comprising a. The method of claim 1,
The read voltage determiner is configured to update the hit ratio table according to a result of the read retry operation. The method of claim 1,
The workload is determined based on an aspect of accessing the storage unit for a read operation and a size of read data. 4. The method of claim 3,
The workload includes a sequential read operation that is a read operation using a logical address immediately after the last logical address of a preceding read operation as a starting point, a random read operation that is a read operation that is not the sequential read, and a size of read data is less than or equal to a set size. A data storage device that includes small read operation. a storage unit for storing data; and
Including; a controller for controlling the storage unit;
The controller may include: a read retry table configured to store a plurality of retry read voltages;
a hit ratio table for storing read success rates for each of the plurality of retry read voltages according to a workload; and
a read voltage determiner configured to determine a workload when a normal read operation using a default read voltage fails and select a read voltage based on a hit ratio for each retry read voltage of the determined workload;
A data storage device comprising a. 6. The method of claim 5,
The read voltage determiner updates the hit ratio table according to a result of the read retry. 6. The method of claim 5,
The workload is determined based on an aspect of accessing the storage unit for a read operation and a size of read data. A method of operating a data storage device comprising a storage unit for storing data and a controller for controlling the storage unit, the method comprising:
The controller includes a hit ratio table that stores the read success performance for each retry read voltage according to the workload as the hit ratio,
performing, by the controller, a normal read operation based on a default read voltage in response to a read request from a host;
performing, by the controller, a read retry operation using at least one retry read voltage when the normal read operation fails;
The read retry operation is
determining, by the controller, the workload according to the failure of the normal read operation;
selecting a retry read voltage in the order of the highest hit ratio in the workload; and
a retry step of reading data by providing the selected retry read voltage to the storage unit;
A method of operating a data storage device comprising a. 9. The method of claim 8,
and updating, by the controller, the hit ratio table according to a result of the read retry operation. 9. The method of claim 8,
The determining of the workload includes determining the workload based on an aspect of accessing the storage unit for a read operation and a size of read data. 11. The method of claim 10,
The workload includes a sequential read operation that is a read operation using a logical address immediately after the last logical address of a preceding read operation as a starting point, a random read operation that is a read operation that is not the sequential read, and a size of read data is less than or equal to a set size. A method of operating a data storage device including a small read operation.

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