KR20210036699A - Bit-serial hight operation apparatus and its method, computer-readable recording medium and computer program having program language for the same - Google Patents

Abstract

The present invention relates to a device, method, computer-readable recording medium including instructions for allowing processor to perform method, and computer program for calculating a bit serial HIGHT, comprising: a key scheduling module unit for selecting and providing a whitening key for initial conversion and final conversion and a sub-key for round calculation by using an inputted master key, wherein the key scheduling module unit provides the whitening key or the sub-key by calculating the master key through a key shift register; and a round function module unit for outputting an inputted plain text by performing the initial conversion, the round calculation, and the final conversion by using the whitening key or the sub-key, wherein the plain text is inputted and is calculated by using shift data stored in the first text shift register and the whitening key or the sub-key, and thus a multiplexer (MUX) required for data control can be minimized, and a 1-bit operation can be performed every cycle without delay.

Description

BIT-SERIAL HIGHT OPERATION APPARATUS AND ITS METHOD, COMPUTER-READABLE RECORDING MEDIUM AND COMPUTER PROGRAM HAVING PROGRAM LANGUAGE FOR THE SAME}

In the present invention, by implementing text registers and key registers as shift registers, the multiplexer (MUX) required for data control can be minimized, and an auxiliary function in units of bytes is implemented in units of 1 bit through an additional shift register. By adjusting the position of the data to be calculated, a bit serial HIGHT computing device and method capable of performing an operation in units of one bit every cycle without delay, and a computer-readable method including instructions for causing the processor to perform the method. It relates to a recording medium and a computer program.

As is well known, encryption is a process of encoding so that its meaning is not clear, and decryption refers to the process of converting an encrypted message into its original form. The original form of the message is called plain text, and The form is called Cipher text.

On the other hand, the symmetric encryption system is a system in which the sender's key used for encryption and the receiver's key for decryption are the same. ) As a block encryption technology, a HIGHT (High Encryption Standard) encryption algorithm has been developed, and various research and development have been conducted to implement it.

As shown in FIGS. 1 to 3, the HIGHT has a 64-bit plaintext (P) and a 128-bit key length, and includes initial transformation and final transformation and 32 rounds. Through this, encryption and decryption operations can be performed.

The HIGHT hardware implementation designed with the smallest area to date is a round-based method that calculates one round per clock cycle, and has an area of about 3000GE (Gate Equivalents), but passive RFID (passive RFID) In order to perform encryption in an environment where area and power consumption are limited, such as RFID), it is necessary to design a smaller size of 2000GE or less.

In conventional round-based HIGHT hardware, a 64-bit unit of a round operation unit and a 64-bit and 128-bit multiplexer (MUX) for selecting text and key data occupy a large area. It is possible to apply a traditional folding technique that shares hardware by making it in 32-bit or 16-bit units, but not only does not see much effect due to the additional cost of a multiplexer (MUX) to control it, and the auxiliary functions F0, Since the F1 and addition operations are performed in units of 8 bits (1 byte), there is a problem in that it is difficult to implement a HIGHT operation structure of 8 bits or less with a simple folding technique.

1. Korean Patent Registration No. 10-1330664 (registered on Nov. 08, 2013) 2. Korean Patent Publication No. 10-2015-0123476 (published on November 4, 2015)

In the present invention, by implementing a text register and a key register as a shift register, the multiplexer required for data control can be minimized, and by implementing an auxiliary function in units of 1 bit through an additional shift register, the position of the data to be operated is adjusted. It is intended to provide a bit serial HIGHT computing device and method capable of performing 1-bit operation every cycle without delay, and a computer-readable recording medium and computer program including instructions for causing a processor to perform the method. .

In addition, the present invention selects and provides a WhiteningKey for initial conversion and final conversion and a SubKey for round operation using the input MasterKey, but the master key is provided through a key shift register. Calculates to generate a whitening key or subkey, and outputs the input plaintext by performing initial conversion, round operation, and final conversion using the whitening key or subkey, but the plaintext is input and the shift data stored in the first text shift register A bit serial HIGHT computing device and method capable of operating using a whitening key or a subkey, and a computer-readable recording medium and a computer program including instructions for causing a processor to perform the method.

The objects of the embodiments of the present invention are not limited to the above-mentioned objects, and other objects not mentioned will be clearly understood by those of ordinary skill in the technical field to which the present invention pertains from the following description. .

According to an aspect of the present invention, a WhiteningKey for initial conversion and final conversion and a SubKey for round operation are selected and provided using an input MasterKey, wherein the master key is used as a key. A key scheduling module unit that operates through a shift register to provide the whitening key or subkey, and the input plain text by using the whitening key or subkey to perform the initial transformation, round operation, and final transformation. A bit serial HIGHT operation apparatus including a round function module unit which outputs the plain text and operates using the shift data stored in the first text shift register and the whitening key or the sub key may be provided.

In addition, according to an aspect of the present invention, the key scheduling module unit includes a key shift register that is a basis for selective generation of either the whitening key or the subkey, each 1 bit through the key shift register. A bit serial HIGHT computing device may be provided that operates and selects and provides the whitening key or the subkey to the round function module unit by one bit.

Further, according to an aspect of the present invention, the round function module unit includes a bit serial having a second text shift register of 1 byte for calculating a first auxiliary function and a second auxiliary function in units of 8 bits in units of 1 bit. A HIGHT computing device can be provided.

Further, according to an aspect of the present invention, the round function module unit performs the round operation on the even-numbered byte text data and stores the round operation in the second text shift register, and the odd-numbered byte text data is rounded. When performing an operation, a bit serial HIGHT operation device may be provided that cyclically shifts a value stored in the second text shift register and outputs a result of the first or second auxiliary function bit by bit. have.

Further, according to an aspect of the present invention, the round function module unit outputs a result of the first or second auxiliary function bit by bit, and with respect to the result value of the first auxiliary function or the second auxiliary function. The round operation is performed, and the output value of the round operation is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a 1-bit flip-flop is used for each cycle. A bit serial HIGHT operation device for storing the carry that occurs every time may be provided.

According to another aspect of the present invention, a WhiteningKey for initial conversion and final conversion and a SubKey for round operation are selected using the input MasterKey, but the master key is used as the key. Providing the whitening key or subkey by calculating through a shift register, and performing the initial conversion, round operation, and final conversion using the whitening key or subkey to output the input plain text, A bit serial HIGHT operation method including the step of calculating the plaintext by using the shift data stored in the first text shift register and the whitening key or the subkey may be provided.

In addition, according to another aspect of the present invention, the providing of the whitening key or the subkey may include calculating 1 bit by each through a key shift register that is a basis for selective generation of either the whitening key or the subkey. A bit serial HIGHT operation method may be provided in which the whitening key or the subkey is selected and provided by one bit to the round function module unit.

In addition, according to another aspect of the present invention, the operation of using the whitening key or the subkey includes a second sub-function of 1 byte for calculating a first auxiliary function and a second auxiliary function in units of 8 bits in units of 1 bit. A bit serial HIGHT operation method having a text shift register can be provided.

In addition, according to another aspect of the present invention, the step of calculating using the whitening key or the subkey includes storing in the second text shift register while performing the round operation on text data of even-numbered bytes, and storing an odd-numbered byte in the second text shift register. When performing the round operation on text data of bytes, a bit for cyclic shifting a value stored in the second text shift register and outputting the result of the first or second auxiliary function bit by bit A serial HIGHT operation method may be provided.

In addition, according to another aspect of the present invention, the step of calculating using the whitening key or the subkey includes outputting the result of the first auxiliary function or the second auxiliary function bit by bit, and the first auxiliary function or the second auxiliary function 2 The round operation is performed on the result value of the auxiliary function, and the output value of the round operation is stored in the first text shift register. -flop) may be used to provide a bit serial HIGHT calculation method for storing the carry occurring every cycle.

According to another aspect of the present invention, as a computer-readable recording medium storing a computer program, the computer program, when executed by a processor, is used for initial conversion and final conversion using an input MasterKey. Selecting and providing a whitening key and a subkey for round operation, but calculating the master key through a key shift register to provide the whitening key or subkey, and plain text to be input The initial conversion, round operation, and final conversion are performed using the whitening key or subkey, and output, but the plaintext is input and calculated using the shift data stored in the first text shift register and the whitening key or subkey. A computer-readable recording medium including instructions for causing the processor to perform a method including the step of performing may be provided.

According to another aspect of the present invention, as a computer program stored in a computer-readable recording medium, the computer program is for initial conversion and final conversion using a master key (MasterKey) input when executed by a processor. Selecting and providing a whitening key and a subkey for round operation, but calculating the master key through a key shift register to provide the whitening key or subkey, and input plain text The initial conversion, round operation, and final conversion are performed using the whitening key or subkey, and output, but the plaintext is input and calculated using the shift data stored in the first text shift register and the whitening key or subkey. A computer program including instructions for causing the processor to perform a method including the step of performing may be provided.

In the present invention, by implementing a text register and a key register as a shift register, the multiplexer required for data control can be minimized, and by implementing an auxiliary function in units of 1 bit through an additional shift register, the position of the data to be operated is adjusted. , It is possible to perform 1-bit operation every cycle without delay.

In addition, the present invention selects and provides a WhiteningKey for initial conversion and final conversion and a SubKey for round operation using the input MasterKey, but the master key is provided through a key shift register. Calculates to generate a whitening key or subkey, and outputs the input plaintext by performing initial conversion, round operation, and final conversion using the whitening key or subkey, but the plaintext is input and the shift data stored in the first text shift register It can be calculated using and whitening key or subkey.

In particular, the structure of the bit serial HIGHT operation device proposed in the present invention replaces text registers and key registers with shift registers, and most of the registers except for a specific position are shifted to the next position without exception. It has the advantage of being able to eliminate most of the multiplexers.

In addition, in the present invention, by using a 1-byte shift register, it is possible to implement a 1-bit unit of the auxiliary functions (F0, F1) including a cyclic shift operation in units of bytes, thereby configuring the entire round operation unit in units of 1 bit. In addition, since the hardware that performs encryption and decryption operations is the same except for the control signal, hardware that can be reconfigured between encryption and decryption without additional cost can be implemented in a low area, and the entire hardware area is built into the conventional round-based HIGHT structure. Compared to this, it can be drastically reduced.

1A to 1C are diagrams illustrating a conventional HIGHT algorithm,
2 is a block diagram showing a bit serial HIGHT operation device according to an embodiment of the present invention.
3 to 6 are diagrams for explaining a bit serial HIGHT operation according to an embodiment of the present invention,
7 is a step-by-step flowchart illustrating a process of performing a bit serial HIGHT operation according to another embodiment of the present invention.

Advantages and features of the embodiments of the present invention, and a method of achieving them will be apparent with reference to the embodiments described later in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms, and only these embodiments make the disclosure of the present invention complete, and are common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

In describing the embodiments of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In addition, terms to be described later are terms defined in consideration of functions in an embodiment of the present invention, which may vary according to the intention or custom of users or operators. Therefore, the definition should be made based on the contents throughout the present specification.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a bit serial HIGHT operation apparatus according to an embodiment of the present invention, and FIGS. 3 to 6 are diagrams for explaining a bit serial HIGHT operation according to an embodiment of the present invention.

Here, the encryption process using the bit serial HIGHT computing device according to an embodiment of the present invention may consist of an initial conversion, a round operation, and a final conversion, and the decryption process is an inverse conversion of the encryption final conversion: an initial conversion, a round operation, and an encryption. It can consist of the final conversion, which is the inverse conversion of the initial conversion, and the operation and operation time of the register can be synchronized through a clock signal under the control of the controller, and the encryption operation and decryption operation through the mode signal under the control of the controller. You can choose.

Referring to FIG. 2, a bit serial HIGHT operation apparatus according to an embodiment of the present invention may include a key scheduling module unit 110, a round function module unit 120, and the like.

The key scheduling module unit 110 selects and provides a WhiteningKey for initial conversion and final conversion and a SubKey for round operation using an input MasterKey, but shifts the master key to a key. Whitening keys or subkeys can be provided by operating through registers.

Here, the key scheduling module unit 110 includes a key shift register that is a basis for selective generation of either a whitening key or a sub key, and calculates a whitening key or a sub key by 1 bit each through the key shift register. The round function module unit can select and provide 1 bit at a time.

The round function module unit 120 outputs the input plain text by performing initial conversion, round operation, and final conversion using a whitening key or a subkey, but the plain text is inputted and stored in the first text shift register. It can be calculated using data and whitening keys or subkeys.

Here, the round function module unit 120 may include a 1 byte second text shift register for calculating the first auxiliary function F0 and the second auxiliary function F1 in units of 8 bits in units of 1 bit. have.

In addition, the round function module unit 120 performs a round operation on text data of even-numbered bytes and stores it in a second text shift register, and when performing a round operation on text data of odd-numbered bytes, the second text shifts. A result of the first auxiliary function or the second auxiliary function may be output one bit by one while cyclic shifting the value stored in the register.

In addition, the round function module unit 120 outputs the result of the first auxiliary function or the second auxiliary function bit by bit, performs a round operation on the result value of the first auxiliary function or the second auxiliary function, and performs a round operation. The output value of is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a carry that occurs every cycle may be stored using a 1-bit flip-flop.

For example, the bit serial HIGHT operation apparatus according to an embodiment of the present invention performs a module that performs a round function as shown in FIG. 3 and a key scheduling as shown in FIG. 4. It can be provided as a performing module. In each module, text is stored in a 64-bit shift register, and a key value is stored in a 128-bit shift register, so that it can be shifted by 1 bit every clock cycle.

In addition, the round function module may perform a 1-bit round operation using 1-bit data selected at an appropriate location among 8 locations of a text register and 1-bit key received from a key scheduler.

In particular, as shown in FIG. 5, in order to implement the auxiliary functions F0 and F1 in units of 8 bits (1 byte) in units of 1 bit, a 1 byte shift register may be provided, and text of an even numbered byte (Even Byte) May be stored in the shift register provided at the same time as the round operation. After that, when the text of the odd-numbered byte is rounded, the previously stored value is cyclically shifted and F0, F1 in 1-bit units. Function results can be printed.

In particular, in the hardware of the bit serial HIGHT operation apparatus according to an embodiment of the present invention, round operation and conversion operation are combined into one, and a result of one of two types (Type A and Type B) to be calculated is selected and the text register is displayed. It can be stored in an appropriate location, and in the case of an addition operation in which a carry occurs, a carry that occurs every cycle can be stored using a 1-bit flip-flop.

Meanwhile, the key scheduler module operates one bit by one through a shift register in a manner similar to that of the round function module, and may provide a whitening key and a subkey to the round function module by one bit.

Referring to FIG. 6, the entire operation process over time of the bit serial HIGHT operation device according to the embodiment of the present invention as described above will be described with reference to FIG. 6, and one cycle may correspond to 8 clock cycles, and each index Is in units of 1 byte, the location of the data selected for round operation in the text register is indicated by a dotted line, values that have been calculated are indicated in gray, and in the key register, the key used for round operation is indicated in gray. .

Here, in the encryption process, the location of the data computed within one round is constant, but in the decryption process, considering that the LFSR (Linear Feedback Shift Register) value changes in the reverse order, it can be seen that the computation location is not constant. At the end of the round operation, a 1-byte rotation operation is performed on the data. In the hardware of the bit serial HIGHT operation device according to an embodiment of the present invention, instead of actually rotating it, the position where the round operation is performed in the text register is appropriately determined. By selecting, you can perform a virtual rotation.

Accordingly, the present invention can minimize the multiplexer (MUX) required for data control by implementing a text register and a key register as a shift register, and an auxiliary function in units of byte through an additional shift register. By implementing and adjusting the position of the calculated data, it is possible to perform a 1-bit operation every cycle without delay.

Next, in the bit serial HIGHT operation device having the configuration as described above, a whitening key and a sub key are provided by operating through a 128-bit shift register using a master key, and the data selected from the 64-bit shift register and the whitening key or sub key are provided. Describes the process of performing a round operation through a key.

7 is a step-by-step flowchart illustrating a process of performing a bit serial HIGHT operation according to another embodiment of the present invention.

Referring to FIG. 7, a whitening key for initial transformation and final transformation and a subkey for round operation are selected and provided using the input master key, but the whitening key or the subkey is calculated by calculating the master key through a key shift register. Can be provided (step 710).

Here, the key scheduling module unit 110 includes a key shift register that is a basis for selective generation of either a whitening key or a subkey, and calculates a whitening key or a subkey by 1 bit each through the key shift register. The round function module unit can select and provide 1 bit at a time.

Next, the input plaintext is output by performing initial conversion, round operation, and final conversion using a whitening key or a subkey, but the plaintext is input and the shift data stored in the first text shift register and the whitening key or subkey are used. And can be calculated (step 720).

Here, the round function module unit 120 may include a 1-byte second text shift register for calculating the first auxiliary function (F0) and the second auxiliary function (F1) in units of 8 bits in units of 1 bit. have.

In addition, the round function module unit 120 performs a round operation on text data of even-numbered bytes and stores it in a second text shift register, and when performing a round operation on text data of odd-numbered bytes, the second text is shifted. While cyclically shifting the value stored in the register, the result of the first auxiliary function or the second auxiliary function may be output one bit at a time.

In addition, the round function module unit 120 outputs the result of the first auxiliary function or the second auxiliary function bit by bit, performs a round operation on the result value of the first auxiliary function or the second auxiliary function, and performs a round operation. The output value of is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a carry that occurs every cycle may be stored using a 1-bit flip-flop.

Accordingly, the present invention also provides a whitening key for initial transformation and final transformation and a subkey for round operation by using the input master key, but the whitening key or subkey by calculating the master key through a key shift register. Is generated, and the input plaintext is output by performing initial conversion, round operation, and final conversion using the whitening key or subkey, but the shift data and the whitening key or subkey stored in the first text shift register by inputting the plaintext are output. It can be calculated using.

In particular, the structure of the bit serial HIGHT operation device proposed in the present invention replaces text registers and key registers with shift registers, and most of the registers except for a specific position are shifted to the next position without exception. It has the advantage of being able to eliminate most of the multiplexers.

In addition, in the present invention, by using a 1-byte shift register, it is possible to implement a 1-bit unit of the auxiliary functions (F0, F1) including a cyclic shift operation in units of bytes, thereby configuring the entire round operation unit in units of 1 bit. In addition, since the hardware that performs encryption and decryption operations is the same except for the control signal, hardware that can be reconfigured between encryption and decryption without additional cost can be implemented in a low area, and the entire hardware area is built into the conventional round-based HIGHT structure. Compared to this, it can be drastically reduced.

Meanwhile, the bit serial HIGHT operation method as described above may be provided as a computer-readable recording medium storing a computer program.

When the computer program is executed by a processor,

Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. Providing a key or subkey, and

The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, but the shift data and the whitening key stored in the first text shift register after the plain text is input Alternatively, it may include an instruction for causing the processor to perform a method including the step of calculating using a subkey.

In addition, the bit serial HIGHT operation method as described above may be provided as a computer program stored in a computer-readable recording medium.

When the computer program is executed by a processor,

Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. Providing a key or subkey, and

The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, but the shift data and the whitening key stored in the first text shift register after the plain text is input Alternatively, it may include an instruction for causing the processor to perform a method including the step of calculating using a subkey.

In the above description, various embodiments of the present invention have been presented and described, but the present invention is not necessarily limited thereto, and those of ordinary skill in the art to which the present invention pertains, within the scope of the technical spirit of the present invention. It will be easy to see that branch substitutions, modifications and changes are possible.

110: key scheduling module unit
120: round function module unit

Claims (12)

Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. A key scheduling module unit that provides a key or subkey;
The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, but the shift data and the whitening key stored in the first text shift register after the plain text is input Or round function module part that calculates using subkeys
Bit serial HIGHT operation device comprising a.
The method of claim 1,
The key scheduling module unit includes a key shift register that is a basis for selective generation of either the whitening key or the subkey, and calculates the whitening key or the subkey by 1 bit each through the key shift register. A bit serial HIGHT operation device that selectively provides 1 bit to the round function module unit.
The method of claim 2,
The round function module unit includes a 1-byte second text shift register for calculating a first auxiliary function in an 8-bit unit and a second auxiliary function in a 1-bit unit.
The method of claim 3,
The round function module unit performs the round operation on text data of even-numbered bytes and stores it in the second text shift register, and when performing the round operation on text data of odd-numbered bytes, the second text shifts A bit serial HIGHT operation device that outputs a result of the first or second auxiliary function bit by bit while cyclic shifting a value stored in a register.
The method of claim 4,
The round function module unit outputs the result of the first auxiliary function or the second auxiliary function bit by bit, performs the round operation on the result value of the first auxiliary function or the second auxiliary function, and performs the round operation. A bit serial that stores the output value performed by the first text shift register, but stores the carry occurring every cycle using a 1-bit flip-flop in the case of an addition operation in which a carry occurs. HIGHT computing device.
Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. Providing a key or subkey, and
The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, but the shift data and the whitening key stored in the first text shift register after the plain text is input Or the step of calculating using a subkey
Bit serial HIGHT operation method comprising a.
The method of claim 6,
In the providing of the whitening key or the subkey, the whitening key or the subkey is rounded by calculating 1 bit each through a key shift register that is a basis for selective generation of any one of the whitening key or the subkey. Bit serial HIGHT operation method that selects and provides 1 bit at a time to the function module part.
The method of claim 7,
The operation using the whitening key or the subkey may include a bit serial HIGHT operation including a 1 byte second text shift register for calculating a first auxiliary function and a second auxiliary function in units of 8 bits in units of 1 bit. Way.
The method of claim 8,
The operation using the whitening key or subkey includes performing the round operation on text data of even-numbered bytes and storing them in the second text shift register, and performing the rounding operation on text data of odd-numbered bytes. When executed, a bit serial HIGHT operation method for cyclic shifting a value stored in the second text shift register and outputting a result of the first auxiliary function or the second auxiliary function bit by bit.
The method of claim 9,
In the step of calculating using the whitening key or subkey, the result of the first or second auxiliary function is output one bit at a time, and the result of the first or second auxiliary function is rounded. The operation is performed and the output value of the round operation is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, it occurs every cycle using a 1-bit flip-flop. Bit serial HIGHT operation method for storing the carry.
As a computer-readable recording medium storing a computer program,
When the computer program is executed by a processor,
Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. Providing a key or subkey; and
The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, and the shift data and the whitening key stored in the first text shift register after the plain text is input Or including instructions for causing the processor to perform a method comprising the step of calculating using a subkey
Computer-readable recording medium.
As a computer program stored on a computer-readable recording medium,
When the computer program is executed by a processor,
Whitening Key for initial conversion and final conversion and SubKey for round operation are selected and provided using the input MasterKey, but the whitening is performed by calculating the master key through a key shift register. Providing a key or subkey, and
The input plain text is output by performing the initial conversion, round operation, and final conversion using the whitening key or subkey, and the shift data and the whitening key stored in the first text shift register after the plain text is input Or including instructions for causing the processor to perform a method comprising the step of calculating using a subkey
Computer program.

Images