KR20200034560A - Storage device and operating method of storage device - Google Patents

Abstract

The present invention relates to a storage device, which supports committing of an operating system to reduce committing time and have reduced latency. According to an embodiment of the present invention, the storage device comprises: a nonvolatile memory device; a random access memory including a first area and a second area; and a controller that uses the first area of the random access memory as a buffer memory of the nonvolatile memory device, exposes a user area of the nonvolatile memory device to an external host device as a first access area in a block unit, and exposes the second area of the random access memory to the external host device as both a second access area in the block unit and a third access area in a byte unit.

Description

Storage device and how to operate the storage device {STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a storage device that allows block-by-block access and memory mapped access of a portion of a storage area and a method of operating the storage device.

The operating system or application uses main memory and auxiliary storage. The primary memory is used to temporarily store data, and the secondary storage can be used to store the data nonvolatilely for a long time. The operating system can manage auxiliary storage based on the file system. The file system may include various information about the file, such as the address where the data of the file is stored and the capacity of the file.

When an operating system or application modifies or updates data (hereinafter, user data) stored in the auxiliary storage, an update of the file system occurs. Updating the file system whenever user data is modified or updated causes an increase in access to the auxiliary storage, and may increase latency of the auxiliary storage.

To avoid this problem, the operating system may store user data and update data of the file system associated with the user data (hereinafter, meta data) in main memory. When synchronization of the user data and file system driven by the operating system and the user data and file system stored in the auxiliary storage is required, the operating system may perform a commit.

Commitment includes the operating system writing user data to the user area of the auxiliary storage, and writing metadata to the journal area of the auxiliary storage. When a commit is performed, even when a sudden power off (SPO) occurs, the operating system may recover the user data and file system by referring to the journal area.

The operating system may reflect data and metadata of the journal area in the user area at power-on, power-off, or at a separate time. For example, the operating system may copy user data from the journal area to the user area. In addition, the operating system may reflect the metadata of the journal area to data of the file system stored in the user area.

As noted above, commits involve operations to write user data and metadata to auxiliary storage. These operations can increase the execution time of the commit and increase the latency of the auxiliary storage.

An object of the present invention is to provide a storage device having a reduced latency and a method of operating a storage device with reduced latency by supporting a commit of an operating system.

The storage device according to an embodiment of the present invention uses a nonvolatile memory device, a random access memory including the first area and the second area, and a first area of the random access memory as a buffer memory of the nonvolatile memory device, The user area of the volatile memory device is exposed to the external host device as the first access area in the block unit, and the second area of the random access memory is external as both the second access area in the block unit and the third access area in the byte unit. It includes a controller configured to be exposed to the host device.

A storage device according to an embodiment of the present invention uses a nonvolatile memory device, a dynamic random access memory including a first area and a second area, and a first area as a buffer memory of a nonvolatile memory device, and a nonvolatile memory device It includes a controller configured to expose the user area of the block as a first access area in a block unit to an external host device. The second area includes segments, the controller selects a first one of the segments, and selects at least two second segments from segments other than the first segment, and is non-volatile to the selected segments. -volatility), and at least two second segments are dynamically changed in a ring buffer manner in the remaining segments.

An operation method of a storage device according to an embodiment of the present invention including a nonvolatile memory device and a dynamic random access memory includes providing a portion of the storage space of the nonvolatile memory device to an external host device as a user area, and dynamic And providing a portion of the storage space of the random access memory to an external host device as a journal area in which writing in bytes and reading in blocks are allowed. The storage space of the journal area includes segments. Providing the external host device as a journal area includes providing non-volatility to a fixed first segment and at least two second segments that are dynamically changed.

According to embodiments of the present invention, a storage device provides a storage area that allows block-by-block access and memory mapped access. The storage area can be configured to support the commit of the operating system. Accordingly, a storage device having reduced execution time and latency of a commit and a method of operating the storage device are provided.

1 shows a storage device according to an embodiment of the present invention.
2 shows an example of a method in which a storage device provides device information to an external host device during an initialization operation.
3 shows the capacity of actual storage areas of the storage device and the areas shown to the external host device.
4 shows an example in which a normal access request based on a logical block address is processed in a storage device.
5 shows an example in which a write request based on a memory mapped input and output is processed in a storage device.
6 shows an example in which the storage device backs up data in the persistent memory area when a sudden power off occurs.
7 shows an example in which the storage device loads data into the persistent memory area and restores it when power supply from an external host device is resumed.
8 shows an example in which the controller manages the persistent memory area.
9 shows an example in which the storage device processes a flush request.
10 shows an example in which the persistent memory area is managed by the flush request.
11 shows an example in which a controller processes a read request based on a logical block address.
12 shows an example of a computing system.
13 shows an example in which the first application running on the processor updates the first user data.
14 shows examples of the first user data, the first meta data, and the first bitmap.
FIG. 15 shows an example in which the second application modifies the second user data subsequent to FIG. 13.
16 shows an example in which the first application and the third application modify the third user data and the fourth user data, respectively, following FIG. 15.
FIG. 17 shows an example in which commit is performed in the computing system subsequent to FIG. 16.
18 shows an example in which the first to third applications modify the fifth to seventh user data D5 to D7 subsequent to FIG. 17.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person having ordinary knowledge in the technical field of the present invention can easily implement the present invention.

1 shows a storage device 100 according to an embodiment of the present invention. Referring to FIG. 1, the storage device 100 includes first and second nonvolatile memory devices 111 and 112, a dynamic random access memory 120, and a controller 130. The storage device 100 may include a solid state drive (SSD).

The first and second nonvolatile memory devices 111 and 112 may perform a write operation, a read operation, and an erase operation under the control of the controller 130. The first and second nonvolatile memory devices 111 and 112 may communicate with the controller 130 through different channels and operate independently of each other.

A portion of the storage space of the first and second nonvolatile memory devices 111 and 112 may be exposed to an external host device by the controller 130. The first and second nonvolatile memory devices 111 and 112 may include various nonvolatile memory devices such as a flash memory device, a phase change memory device, a magnetic memory device, a resistive memory device, and a ferroelectric memory device.

The dynamic random access memory 120 may perform a write operation and a read operation under the control of the controller 130. The storage space of the dynamic random access memory 120 may be divided into the device memory area 121 and the persistent memory area 122 by the controller 130.

The persistent memory area 122 may be exposed to an external host device by the controller 130. For example, the persistent memory area 122 may be exposed to an external host device as a memory mapped area. Also, the persistent memory area 122 may be exposed to an external host device as an area where block-based access is allowed.

The device memory area 121 is not exposed to an external host device and can be accessed by the controller 130. The device memory area 121 may be used to store management data (or meta data) and codes necessary for managing the storage device 100. The device memory area 121 may be used as a buffer memory or a cache memory.

The storage areas of the dynamic random access memory 120 are described with specific names of the device memory area 121 and the persistent memory area 122. However, the names of the device memory area 121 and the persistent memory area 122 are for classification, and functions and characteristics of the device memory area 121 and the persistent memory area 122 are not limited by the names.

The controller 130 controls the first and second nonvolatile memory devices 111 and 112 and may control the dynamic random access memory 120. The controller 130 can communicate with an external host device. The controller 130 includes an interface block 131, a device information block 132, a first control block 133, a second control block 134, a buffer block 135, a memory control block 136, and a first management It may include a block 137, a second management block 138, and an auxiliary power block 139.

Interface block 131, first control block 133, second control block 134, buffer block 135, memory control block 136, first management block 137, and second management block 138 ) Can communicate with each other via the internal bus. The interface block 131 may communicate with an external host device.

When power is supplied to the storage device 100, the interface block 131 may receive device information of the storage device 100 from the device information block 132. The interface block 131 may provide device information of the storage device 100 to an external host device. For example, the device information of the storage device 100 includes information of a portion exposed to an external host device among the first and second nonvolatile memory devices 111 and 112 and information of the persistent memory area 122. It can contain. Providing device information of the storage device 100 may be performed as part of an initialization operation.

After the initialization operation is completed, normal operations may be performed. For example, the interface block 131 may receive a request from an external host device and parse the received request. The interface block 131 may allow block-based requests and memory mapped requests to external host devices. The block-based request may include a logical block address (LBA). The block-based request may indicate a location where data is to be written or a location to read data using a logical block address (LBA).

The memory mapped request may include a virtual address (VA) in bytes. The memory-mapped request may indicate where the data is to be written or where to read the data using a virtual address (VA). The interface block 131 may transmit a block-based request to the first control block 133 and a memory-mapped request to the second control block 134.

The interface block 131 may be based on Peripheral Component Interconnect Express (PCIe) or Non-Volatile Memory Express (NVMe). The interface block 131 may receive a memory mapped request from a memory mapped input and output (memory mapped I / O) of PCIe or NVMe. The interface block 131 may receive a block-based request in a block input / output (Block I / O) mode of PCIe or NVMe.

The interface block 131 may transmit data received from an external host device to the device memory area 121 through the memory control block 136. The interface block 131 may output data transmitted from the device memory area 121 to an external host device.

The device information block 132 is configured to provide device information of the storage device 100 to the interface block 131 during an initialization operation. The device information block 132 may include various nonvolatile elements such as EEPROM, flash memory, phase change memory, magnetic memory, ferroelectric memory, and resistive memory.

The first control block 133 may receive a block-based request from the interface block 131. The first control block 133 may determine whether the block-based request is the first type or the second type. For example, when the logical block address (LBA) included in the block-based request points to at least one of the first and second nonvolatile memory devices 111 and 112, the block-based request may be of the first type.

When the logical block address (LBA) included in the block-based request points to the persistent memory area 122, the block-based request may be of the second type. When the block-based request is of the first type, the first control block 133 may refer to the first mapping table. When the block-based request is of the second type, the first control block 133 may refer to the second mapping table.

The first mapping table may include mapping information between physical block addresses PBA and logical block addresses LBA of the first and second nonvolatile memory devices 111 and 112. The second mapping table may include mapping information between physical addresses PA and logical block addresses LBA of the persistent memory area 122.

The first mapping table and the second mapping table may be stored in the device memory area 121 of the dynamic random access memory 120. The first control block 133 may convert the logical block address LBA of the block-based request of the first type into a physical block address PBA by referring to the first mapping table. The first control block 133 may transfer the converted physical block address (PBA) to the first management block 137 or the second management block 138 together with a write command or a read command.

The first control block 133 may convert the logical block address LBA of the block-based request of the second type into the physical address PA of the persistent memory area 122 by referring to the second mapping table. The first control block 133 may access the persistent memory area 122 through the memory control block 136 based on the converted physical address PA.

In addition, the first control block 133 is such that data transmitted from the external host device through the interface block 131 is written to the device memory area 121, and data stored in the device memory area 121 is an interface block ( 131), direct memory control (DMA) may be performed to be output to an external host device.

When a sudden power off (SPO) occurs, the storage device 100 may receive auxiliary power from the auxiliary power block 139. While the auxiliary power is supplied, the first control block 133 can back up data of at least a portion of the persistent memory area 122 to at least one of the first and second nonvolatile memory devices 111 and 112. have.

The first control block 133 also includes first and second nonvolatile memory devices 111 and 112 that need data to be backed up (eg, metadata such as a mapping table) among data stored in the device memory area 121. ).

When power is supplied again, the first control block 133 may load the backed up data into the persistent memory area 122. In addition, the first control block 133 may load data corresponding to the device memory area 121 among the backed up data into the device memory area 121. By performing backup and load based on the auxiliary power block 139, the first control block 133 may provide non-volatility to the persistent memory area 122.

The second control block 134 may receive a memory mapped request from the interface block 131. The second control block 134 may refer to the third mapping table. The third mapping table may include mapping information between the virtual addresses VA of the memory mapped request and the physical addresses PA of the persistent memory area 122. The third mapping table may be stored in the device memory area 121 or the persistent memory area 122 of the dynamic random access memory 120.

The second control block 134 may convert the virtual address VA of the memory-mapped request into a physical address PA by referring to the third mapping table. The second control block 134 may access the persistent memory area 122 through the memory control block 136 based on the converted physical address PA.

The buffer block 135 may be used to store codes and instructions executed by the first control block 133 or the second control block 134. Also, the buffer block 135 may be used to store important data, such as metadata used by the first control block 133 or the second control block 134.

The memory control block 136 can be configured to control the dynamic random access memory 120. The memory control block 136 may transmit commands and addresses to the dynamic random access memory 120 according to the command system and address system of the dynamic random access memory 120. The memory control block 136 may exchange data with the dynamic random access memory 120 according to the data communication scheme of the dynamic random access memory 120.

The first management block 137 is configured to control the first nonvolatile memory device 111. The second management block 138 is configured to control the second nonvolatile memory device 112. The first management block 137 and the second management block 138 are the first and second nonvolatile memory devices according to the command system and address system of the first and second nonvolatile memory devices 111 and 112 ( 111, 112). The first management block 137 and the second management block 138 are the first and second nonvolatile memory devices 111, according to the data communication system of the first and second nonvolatile memory devices 111 and 112. 112).

The auxiliary power block 139 is configured to supply auxiliary power to the storage device 100 when a sudden power off (SPO) occurs. The auxiliary power block 139 may be charged when power is normally supplied from an external host device. The auxiliary power block 139 may include a tantalum cap or a super cap. The auxiliary power block 139 is illustrated as being located inside the controller 130, but the auxiliary power block 139 may be located outside the controller 130.

2 shows an example of a method in which the storage device 100 provides device information to an external host device during an initialization operation. 1 and 2, in step S110, the controller 130 uses the capacity of the user area of the first and second nonvolatile memory devices 111 and 112 as a logical block address (LBA) area, as an external host. Device.

The logical block address (LBA) area refers to an area accessible by an external host device based on the logical block address (LBA). The external host device may allocate logical block addresses (LBA) to the capacity exposed in step S110. The external host device may identify the exposed capacity in step S110 using a logical block address (LBA).

In step S120, the controller 130 may expose at least a portion of the capacity of the persistent memory area 122 as an addressable area in bytes to an external host device. The addressable area in bytes may be an area that can be incorporated into a memory map by an external host device. The external host device may allocate virtual addresses VA to the capacity exposed in step S120. The external host device may identify the exposed capacity in step S120 using the virtual address VA.

In step S130, the controller 130 may expose the capacity of at least a portion of the persistent memory area 122 to an external host device as a logical block address (LBA) area. The external host device may allocate logical block addresses (LBA) to the exposed capacity in step S130. The external host device may identify the exposed capacity in step S130 using a logical block address (LBA).

For example, the capacity of the persistent memory area 122 exposed in steps S120 and S130 may be a ring-fenced area. For example, the persistent memory area 122 may be configured to be used as a journal region by an operating system of an external host device.

The controller 130 may support block-based reading of the persistent memory area 122 to an external host device, and memory mapped writes to an external host device. The controller 130 may prohibit block-based writing of the persistent memory area 122 to an external host device, and prohibit memory mapped reads from the external host device.

The controller 130 may perform access based on the physical address PA to the device memory area 121 and the persistent memory area 122 of the dynamic random access memory 120. That is, regardless of allowing block-based read and memory mapped write to an external host device, the controller 130 can freely access the device memory area 121 and the persistent memory area 122.

3 shows capacities of actual storage areas of the storage device 100 and capacities of areas visible to an external host device. Referring to FIGS. 1 and 3, the controller 130 is configured such that the non-volatile memory devices 111 and 112 are external to the capacity 21 of the user area excluding the capacity 22 of the excess providing area among the capacity 20. It can be exposed to the host device.

The capacity 22 of the excess provision area can be used by the controller 130 to perform various background operations such as read reclaim, wear leveling, and garbage collection. Further, the capacity 22 of the over-provision area can be used to write update data of data written in the capacity 21 of the user area. That is, the capacity 22 of the excess provision area may be used to prevent the latency of the storage device 100 from increasing and the lifespan to decrease due to an erase-before-write specification.

The external host device may identify the capacity 21 of the user area as part of the area 31 to which the logical block address LBA is allocated. The external host device may allocate logical block addresses LBA to the capacity 21 of the user area, and access the capacity 21 of the user area using the logical block addresses LBA.

The controller 130 may expose the capacity 10 of the persistent memory area 122 to an external host device. For example, the controller 130 may expose the capacity 10 of the persistent memory area 122 to an external host device in a capacity capable of block-based access and memory mapped access.

The external host device may have the capacity 10 of the persistent memory area 122 to which block-based access is permitted, the capacity of the first persistent memory area (PMR) 11 that is part of the area 31 to which the logical block address LBA is allocated ). The external host device allocates logical block addresses LBA to the capacity 11 of the first persistent memory area PMR, and uses the logical block addresses LBA to store the capacity of the first persistent memory area PMR. (11) can be accessed.

The external host device may identify the capacity 10 of the persistent memory area 122 to which the memory mapped access is permitted as the capacity of the second persistent memory area (PMR), which is the memory mapped area 32. The external host device allocates virtual addresses VA to the capacity 12 of the second persistent memory area PMR, and uses the virtual addresses VA to store the capacity 12 of the second persistent memory area PMR. ).

In summary, the external host device may identify storage capacities of the storage device 100 as an area 31 to which a logical block address LBA is allocated and a memory mapped area 32. When an external host device accesses the capacity 21 of the user area in the area 31 to which the logical block address (LBA) is allocated, the storage device may first and second nonvolatile memory according to the request of the external host device. Devices can be accessed.

When an external host device accesses (eg, reads) the capacity 11 of the first persistent memory area (PMR) of the area 31 to which the logical block address (LBA) is allocated, the storage device is an external host. The persistent memory area 122 may be accessed (eg, read) at the request of the device.

When an external host device accesses (eg, writes) the capacity 12 of the second persistent memory area (PMR) of the area 31 to which the logical block address (LBA) is allocated, the storage device is an external host. The persistent memory area 122 may be accessed (eg, written) at the device's request.

The capacity 12 of the second persistent memory area PMR may be used as a journal area in which user data and modification data (eg, meta data) of the file system are committed. The capacity 11 of the first persistent memory area PMR may be used as a journal area for reading user data and metadata when restoring the file system or when reflecting information in the journal area to the file system.

4 shows an example in which a normal access request based on a logical block address (LBA) is processed in the storage device 100. For example, the normal access request may be a first type of access request including the logical block address (LBA) of the first and second nonvolatile memory devices 111 and 112.

The interface block 131 may transmit an access request to the first control block 133. The first control block 133 controls operations accompanying an access request, and may convert the logical block address LBA into a physical block address PBA by referring to the first mapping table. The first control block 133 may transfer the access request to the first nonvolatile memory device 111 or the second nonvolatile memory device 112.

The access request may be processed by involving the device memory area 121. For example, when the access request is a write request, the user data received from the external host device is buffered in the device memory area 121 and then the first nonvolatile memory device 111 or the second nonvolatile memory device 112 ). When the access request is a read request, user data read from the first nonvolatile memory device 111 or the second nonvolatile memory device 112 may be output to an external host device after being buffered in the device memory area 121. have.

5 shows an example in which a write request based on a memory mapped input and output (MMIO) is processed in the storage device 100. For example, an access request based on MMIO may be a write to the journal area. Referring to FIG. 5, the interface block 131 may transmit an MMIO-based write request to the second control block 134.

The second control block 134 controls operations accompanying the MMIO-based write request, and may convert the virtual address VA into a physical address PA by referring to the third mapping table. The second control block 134 may write data, for example, metadata, to the persistent memory area 122 through the memory control block 136 using the physical address PA.

6 illustrates an example in which the storage device 100 backs up data in the persistent memory area 122 when a sudden power off (SPO) occurs. 3 and 6, when power supplied from an external host device is cut off, the auxiliary power block 139 may supply auxiliary power to the storage device 100.

While the auxiliary power is supplied, the first control block 133 may back up data stored in the persistent memory area 122 to the first nonvolatile memory device 111 or the second nonvolatile memory device 112. As another example, the first control block 133 may store a specific range of addresses in the persistent memory area 122. While the auxiliary power is supplied, the first control block 133 may back up data stored in a specific range to the first nonvolatile memory device 111 or the second nonvolatile memory device 112.

For example, the first control block 133 may include addresses in which data is stored in the persistent memory area 122 and a second mapping table or a third mapping table associated with the persistent memory area 122 in the first nonvolatile memory. The device 111 or the second nonvolatile memory device 112 can be backed up together. The first control block 133 is a first nonvolatile memory device (e.g., meta data such as a mapping table stored in the device memory area 121) that needs to be backed up among data stored in the device memory area 121 ( 111) or the second nonvolatile memory device 112 together.

For example, data read from the persistent memory area 122 may be written to the empty storage capacity of the capacity 21 of the user area of the first nonvolatile memory device 111 or the second nonvolatile memory device 112. . As another example, the data read from the persistent memory area 122 may be written to the empty storage capacity of the capacity 22 of the excess providing area of the first nonvolatile memory device 111 or the second nonvolatile memory device 112. .

For example, data read from the persistent memory area 122 may be written to a fixed storage space of the first nonvolatile memory device 111 or the second nonvolatile memory device 112. As another example, the storage space of the first nonvolatile memory device 111 or the second nonvolatile memory device 112 to which data read from the persistent memory area 122 is written may vary.

7 shows an example in which the storage device 100 loads data into the persistent memory area 122 and restores it when power supply from an external host device is resumed. Referring to FIG. 7, when power is supplied from an external host device, the first control block 133 may determine whether there is data requiring restoration.

For example, the first control block 133 may determine whether there is data that needs to be restored by checking flags or information added when backing up the data in the persistent memory area 122. As another example, the first control block 133 needs to be restored by checking whether there is valid data in the storage capacity stored for backup in the first nonvolatile memory device 111 or the second nonvolatile memory device 112. You can determine if data exists.

When data that needs to be restored exists, the first control block 133 can read data that needs to be restored from the first nonvolatile memory device 111 or the second nonvolatile memory device 112. The first control block 133 may perform restoration by loading the read data into the persistent memory area 122.

The first control block 133 reads the addresses backed up from the first nonvolatile memory device 111 or the second nonvolatile memory device 112 and loads data into the persistent memory area 122 based on the read addresses. can do. Also, the first control block 133 reads the second mapping table or the third mapping table backed up from the first nonvolatile memory device 111 or the second nonvolatile memory device 112, and reads the second mapping table or Restoration may be completed by loading the third mapping table into the device memory area 121 or the persistent memory area 122.

For example, the first control block 133 reads data backed up from the device memory area 121 from the first nonvolatile memory device 111 or the second nonvolatile memory device 112 and reads the read data from the device memory Restoration can be completed by loading in the region 121.

8 shows an example in which the controller 130 manages the persistent memory area 122. 1 and 8, the controller 130 may divide the persistent memory area 122 into segments SEG1 to SEG8. The controller 130 may manage a segment at a fixed position among the first to eighth segments SEG1 to SEG8, for example, the first segment SEG1 as a first area.

The controller 130 may manage the remaining second to eighth segments Seg2 to Seg8 as the second area. When a sudden power off (SPO) occurs, the controller 130 may be configured to back up data stored in the first segment SEG1 of the first area 123. For example, the first segment SEG1 may have the lowest physical address or the highest physical address in the persistent memory area 122.

In addition, the controller 130 further adds data stored in the third to fifth segments SEG3 to SEG5 of the selected region 125 among the second to eighth segments SEG2 to SEG8 in the second region 124. It can be configured to back up.

For example, the controller 130 may store addresses of the third to fifth segments SEG3 to SEG5 of the selected area 125. When a sudden power off (SPO) occurs, the controller 130 may back up data of the third to fifth segments SEG3 to SEG5 of the selected area 125 based on the stored address.

For example, the first segment of the first area 123 may be configured to store a super block of the journal area. The super block may include information about a location, length, etc. in which data is stored in the journal area. Since the location where the super block is stored is fixed, the controller 130 can back up the data of the fixed first region 123 where the super block is stored.

The second area 124 may be configured to store user data and metadata in the journal area. The controller 130 can ensure non-volatility only for the region 125 selected in the second region 124. When the size of the data written by the external host device to the second area 124 is larger than the capacity of the selected area 125, non-volatility may not be guaranteed for a part of the data.

In order to prevent such a problem, the storage device 100 according to an embodiment of the present invention may support a flush request. When a flush request is received from an external host device, the controller 130 may perform an operation to ensure non-volatile data being written to the second area 124 from the external host device.

9 shows an example in which the storage device 100 processes a flush request. 10 shows an example in which the persistent memory area 122 is managed by the flush request. 9 and 10, a flush request may be received from an external host device. In response to the flush request, the first control block 133 can read data from the persistent memory area 122.

For example, the third segment (SEG3) at the head of the selected area 125 is indicated by a head pointer, and the fifth segment (SEG5) at the end of the selected area 125 has a tail pointer. Can point. The first control block 133 may read data of the segment indicated by the head pointer, for example, the third segment (SEG3).

User data written in the journal area may include data and logical block addresses (LBAs). The first control block 133 may convert the logical block address LBA into a physical block address PBA. The first control block 133 may write user data to the first nonvolatile memory device 111 or the second nonvolatile memory device 112 based on the physical block address PBA.

That is, in response to the flush request, the third segment (SEG3) indicated by the head pointer of the selected area 125 is selected as the flush area 126, and the data of the flush area 126 is the first nonvolatile memory device 111 ) Or the second nonvolatile memory device 112. Therefore, non-volatile data for the third segment SEG3 is guaranteed.

After the flush is performed, the controller 130 may remove the third segment SEG3 of the flush region 126 from the selected region 125. Accordingly, the head pointer can be updated to point to the fourth segment SEG4. The controller 130 may include the sixth segment SEG6 following the tail pointer of the selected area 125 in the selected area 125. Accordingly, the tail pointer can be updated to include the sixth segment (SEG6).

As such, the controller 130 may allocate the selected area 125 in the second area 124 in the same way as a ring buffer. For example, the controller 130 writes data stored in the segment having the lowest address (or the segment indicated by the head pointer) among at least two segments of the selected area 125 to the nonvolatile memory device 111 or 112. Then, the segment with the lowest address can be deselected.

The controller 130 selects a segment (eg, a segment pointed to by a tail pointer) corresponding to an address that is higher than the highest address among the addresses of at least two second segments of the selected area 125 and the highest address. It can be further selected as the region 125. That is, when the capacity of the selected area 125 is insufficient, the controller 130 may flush data at the head of the selected area 125 and move the selected area 125. Thus, non-volatile data is written by an external host device.

For example, a write operation to the first nonvolatile memory device 111 or the second nonvolatile memory device 112 according to the flush request may have a high priority. The write operation of the flush request may be performed in preference to other write operations or read operations. By first performing the write operation of the flush request, the controller 130 can reduce the latency of writing the journal area of the external host device.

11 shows an example in which the controller 130 processes a read request based on a logical block address (LBA). 3 and 11, the logical block address LBA may indicate the capacity 11 of the first persistent memory area PMR to which the logical block address LBA is allocated.

The first control block 133 may convert the logical block address LBA into a physical address PA by referring to the second mapping table. The first control block 133 may read data from the persistent memory area 122 using the physical address PA.

12 shows an example of a computing system 200. 3 and 12, the computing system 200 includes a processor 210, a main memory 220, a root complex 230, and a storage device 240. The processor 210 may drive operating systems and applications. The processor 210 may include a central processing unit (CPU) or an application processor.

The main memory 220 may be system memory used by the processor 210. The main memory 220 may include dynamic random access memory. The processor 210 may load and use user data stored in the storage device 240 and meta data such as a file system in the main memory 220.

The root complex 230 may provide means for the processor 210 to control peripheral devices. The storage device 240 may be connected to the root complex 230. The storage device 240 may include the storage device 100 described with reference to FIGS. 1 to 11. From the perspective of the processor 210, the storage device 240 includes a user area 241 to which a logical block address (LBA) is allocated, a first persistent memory area 242 to which a logical block address (LBA) is allocated, and a memory map. It can be seen as including the second persistent memory area 243.

13 shows an example in which the first application running on the processor 210 updates the first user data D1. 12 and 13, the first application, the second application, and the third application driven by the processor 210 are a first thread (T1), a second thread (T2), and a third thread (T3), respectively. You can run

The first thread T1 of the first application may modify the first user data D1 stored in the storage device 240. At this time, as described with reference to FIG. 5, instead of storing the modified first user data D1 in the main memory 220, the first application first persistent memory area 242 of the storage device 240 That is, you can write directly in the journal area.

For example, the first application may directly write the first user data or call a journal driver driven in the kernel to write the first user data D1. The first persistent memory area 242 is a memory mapped area. Accordingly, the first application or journal driver driven by the processor 210 may directly write the first user data D1 in units of bytes to the first persistent memory area 242.

For example, the first user data D1 may be written in the first persistent memory area 242 which is a journal area as part of the first transaction TX1. As the first user data D1 is modified, the file system associated with the first user data D1 may be modified. The journal driver may store the modified data of the file system in the main memory 220 as the first meta data M1.

The journal driver may store and manage the first bitmap B1 including information on modifications of the file system in the main memory 220. As the first meta data M1 indicating the modification of the file system is stored in the main memory 220, the journal driver writes information indicating the location of the first meta data M1 to the first bitmap B1. You can.

14 shows examples of the first user data D1, the first meta data M1, and the first bitmap B1. 12 and 14, a unit of data managed by the computing system 200 may be a block (eg, a logical block). The computing system 200 may write and read the user area 241 of the storage device 240 in units of blocks.

For example, the first user data D1 may correspond to four blocks. When the first application of the processor 210 wants to access the first user data D1, the four blocks of the first user data D1 are the main memory 220 from the user area 241 of the storage device 240. ).

The first application of the processor 210 may access the first user data D1 loaded in the main memory 220 in units of bytes. For example, the first application of the processor 210 may modify the first user data D1 in units of bytes. A portion modified by the first application of the processor 210 may be areas filled with diagonal lines in the first user data D1.

As the first application of the processor 210 modifies the first user data D1, the first user data D1 may be written in the first persistent memory area 242, which is a journal area. As the first user data D1 is modified, the file system FS corresponding to the first user data D1 may also be modified.

For example, the file system FS may also be managed in block units. Data of the file system FS is managed in units of blocks, but a portion corresponding to the first user data D1 in the block may be minute. In the block of the file system FS, the modified parts may be indicated by diagonally filled areas. In the block of the file system FS, modified parts may correspond to four sub-blocks.

Journal driver of the processor 210, instead of waiting for the entire block of the file system (FS) to commit (commit), the first meta data (M1) only four sub-blocks modified in the block of the file system (FS) As it can be queued for a commit. Information indicating the positions of the first meta data M1 in the block of the file system FS may be recorded in the first bitmap B1.

For example, the first bitmap B1 may include bits corresponding to the number of correction units (eg, bytes or bytes) belonging to a block of the file system FS. Each bit may be set to a value indicating whether the correction unit of the corresponding position has been modified or not. Depending on the values of the bits, the first bitmap B1 may indicate locations of the modified portion in the block of the file system FS.

That is, instead of waiting for the entire block of the file system FS to commit, the journal driver first metadata M1 and first metadata M1 corresponding to the modified portion of the block of the file system FS. Only the first bitmap (B1) indicating the positions of can be queued for commit. Accordingly, the amount of data to be written to the first persistent memory area 242 that is the journal area when performing the commit is reduced, and the time of the commit is reduced.

Further, when a modification occurs in the first user data D1, the first user data D1 is immediately written into the first persistent memory area 242, which is a journal area, instead of waiting for a commit. Therefore, since it is not necessary to write the first user data D1 when performing the commit, the amount of data of the commit is reduced, and the time of the commit is reduced.

15 shows an example in which the second application modifies the second user data D2 subsequent to FIG. 13. 12, 13 and 15, the second application may modify the second user data D2. As described with reference to FIG. 5, the second application can immediately write the modified second user data D2 as part of the first transaction TX1 in the first persistent memory area 242 which is the journal area. .

As the second user data D2 is modified, as described with reference to FIG. 14, the journal driver of the processor 210 may modify the file system's correction data corresponding to the second user data D2 as second meta data. It can be stored in the main memory 220 as (M2). In addition, the journal driver of the processor 210 may record the positions of the second meta data M2 in the first bitmap B1.

16 shows an example in which the first application and the third application modify the third user data D3 and the fourth user data D4, respectively, following FIG. 15. 12, 15, and 16, the first application may modify the third user data D3. As described with reference to FIG. 5, the first application can immediately write the modified third user data D3 as part of the first transaction TX1 in the first persistent memory area 242 as a journal area. .

As the third user data D3 is modified, as described with reference to FIG. 14, the journal driver of the processor 210 converts the modification data of the file system corresponding to the third user data D3 to third meta data. It can be stored in the main memory 220 as (M3). In addition, the journal driver of the processor 210 may record the positions of the third meta data M3 in the first bitmap B1.

The third application can modify the fourth user data D4. As described with reference to FIG. 5, the third application may immediately write the modified fourth user data D4 as part of the first transaction TX1 in the first persistent memory area 242 as a journal area. . As the fourth user data D4 is corrected, as described with reference to FIG. 14, the journal driver of the processor 210 may modify the file system correction data corresponding to the fourth user data D4 as fourth metadata. It can be stored in the main memory 220 as (M4). In addition, the journal driver of the processor 210 may record the positions of the fourth meta data M4 in the first bitmap B1.

17 shows an example in which the commit is performed in the computing system 200 subsequent to FIG. 16. 12, 16, and 17, as the amount of data of the first transaction TX1 reaches a threshold specified by the journal driver, or any one of the first to third applications requests synchronization Accordingly, a commit can be performed. While the commit is being performed, modification of the user data of the first to third applications may be blocked.

As described with reference to FIG. 5, the journal driver of the processor 210 uses the first to fourth meta data M1 to M4 stored in the main memory 220 as a part of the first transaction TX1. It is possible to write to the first persistent memory area 242. In addition, the journal driver of the processor 210 converts the first bitmap B1 stored in the main memory 220 into a second bitmap B2 as part of the first transaction TX1, and is the first persistent memory area that is a journal area. (242).

The journal driver of the processor 210 may write a commit mark CM indicating that the commit is completed in the first persistent memory area 242 which is a journal area as part of the first transaction TX1. As the commit mark CM is added, the first transaction TX1 may be completed. For example, as the commit is completed, the first bitmap B1 may be initialized.

Thus, the commit is completed by writing the first to fourth meta data M1 to M4, and adding the commit mark CM. Therefore, the amount of data to be written at the time of commit is reduced, and the time of commit is reduced. Accordingly, the operation speed of the storage device 240 and the computing system 200 is improved.

18 shows an example in which the first to third applications modify the fifth to seventh user data D5 to D7 subsequent to FIG. 17. 12, 17, and 18, as described with reference to FIG. 5, the fifth to seventh user data D5 to D7 are first continuations that are journal regions as part of the second transaction TX2. It can be written in the memory area 242. The fifth to seventh metadata M5 to M7 respectively corresponding to the fifth to seventh user data D5 to D7 may be stored in the main memory 220. The positions of the fifth to seventh metadata M5 to M7 may be recorded in the first bitmap B1.

As described above, the storage device 100 or 240 according to an embodiment of the present invention is a memory-mapped area (eg, persistent memory) capable of accessing a portion of the storage capacity of the dynamic random access memory 120 in bytes. Region 122 or 242) to the processor 210. Accordingly, as described with reference to FIG. 5, the application or operating system of the processor 210 may directly write the modified user data to the persistent memory area 122 or 242.

By directly writing the modified user data, and waiting for the commit only as the metadata of the file system, the amount of data that the computing system 200 performs the commit is reduced, and the time of the commit is reduced.

As described with reference to FIG. 11, after data in the persistent memory area 122 or 243 has been restored after a sudden power off (SPO), the journal driver of the processor 210 may perform a committed transaction (eg, TX1) to restore the file system. Alternatively, when the committed transaction TX1 is reflected in the user area 121 or 241, the journal driver of the processor 210 may read the committed transaction TX1 from the persistent memory area 122 or 243.

The read performed in the persistent memory area 122 or 243 may be performed based on a logical block address (LBA). When comparing the input and output of the MMIO mode and block unit of PCIe or NVMe, the read speed of block unit is higher than that of MMIO as the amount of data increases. By allowing MMIO-based writes to the persistent memory area 122 and allowing block-based reads, the read speed of the committed transaction TX1 can be further improved.

As described above, the components of the storage device 100 have been described using terms such as first, second, and third. However, terms such as first, second, and third are used to distinguish components from each other, and do not limit the present invention. For example, terms such as first, second, third, etc., do not imply numerical meaning in any order or in any form.

In the above-described embodiments, components according to embodiments of the present invention have been referenced using blocks. Blocks include various hardware devices such as integrated circuit (IC), application specific IC (ASIC), field programmable gate array (FPGA), and complex programmable logic device (CPLD), software running on hardware devices, software such as applications, Alternatively, a hardware device and software may be combined. Further, the blocks may include circuits composed of semiconductor elements in an IC or IP (Intellectual Property).

The above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will also include techniques that can be easily modified and implemented using embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims to be described later but also by the claims and equivalents of the present invention.

100: storage device
111, 112: non-volatile memory devices
120: dynamic random access memory
121: device memory area
122: persistent memory area
130: controller
131: interface block
132: device information block
133: first control block
134: second control block
135: buffer block
136: memory control block
137: first management block
138: second management block
139: auxiliary power block

Claims (20)

A nonvolatile memory device;
A random access memory including a first area and a second area; And
The first area of the random access memory is used as a buffer memory of the nonvolatile memory device, the user area of the nonvolatile memory device is exposed to an external host device as a block-based first access area, and the random area And a controller configured to expose the second area of the access memory to the external host device as both the second access area in the block unit and the third access area in the byte unit. According to claim 1,
The controller is a storage device supporting writing of the byte unit and reading of the block unit for the second area. According to claim 2,
In the normal mode, the controller prohibits the reading of the block unit for the second area, and
In a recovery mode, the controller prohibits the write of the byte unit to the second area. According to claim 1,
When the request received from the external host device includes a logical block address pointing to the user area, the controller forwards the request to the nonvolatile memory device, and
When the request includes a logical block address pointing to the second area, the controller forwards the request to the second area. According to claim 1,
When the request received from the external host device includes a logical block address pointing to the second area, the controller converts the logical block address to a corresponding first physical address among the physical addresses of the second area. , And
When the request includes a virtual address pointing to the second area, the controller converts the virtual address to a corresponding second physical address among the physical addresses in the second area. According to claim 1,
Further comprising an auxiliary power supply configured to supply auxiliary power when the power from the external host device is cut off,
When the auxiliary power is supplied after the power is cut off, the controller is further configured to back up data stored in the second area to the nonvolatile memory device, and
When the power is supplied from the external host device again, the controller is further configured to load the backed-up data into the second area. The method of claim 6,
The auxiliary power is a storage device including a tantalum cap or a supercap that is charged when the power is supplied. The method of claim 6,
The nonvolatile memory device further includes an excess providing area not visible by the external host device,
The controller is a storage device that backs up the data stored in the second area to a free storage space in the user area or the excess provision area of the nonvolatile memory device. The method of claim 6,
The second region includes segments,
The data stored in the second area backed up by the controller to the nonvolatile memory device is data stored in selected segments among the segments of the second area. The method of claim 9,
The controller fixedly selects the first segment of the lowest or highest address among the segments, and
The controller further selects at least two second segments having consecutive addresses from among segments other than the first segment,
A storage device in which addresses of the at least two second segments are changed. The method of claim 10,
And the controller changes the addresses of the at least two second segments according to the request of the external host device. The method of claim 11,
In response to the request, the controller writes the data stored in the segment with the lowest address of the at least two second segments to the nonvolatile memory device, and then the one of the at least two second segments Deselect the segment with the lowest address, and
The storage device further selects a segment that is continuous with the highest address among the addresses of the at least two second segments and corresponds to an address higher than the highest address of the at least two second segments. The method of claim 12,
The data includes a logical block address,
The controller converts the logical block address of the data into a physical block address of the nonvolatile memory device, and writes the data to the nonvolatile memory device based on the physical block address. The method of claim 10,
The controller selects the at least two second segments from among the remaining segments in a ring buffer method. According to claim 1,
The controller provides the second area as a journal area to the external host device. A nonvolatile memory device;
A dynamic random access memory including a first area and a second area; And
A controller configured to use the first area as a buffer memory of the nonvolatile memory device, and expose the user area of the nonvolatile memory device to an external host device as a block-based first access area,
The second region includes segments,
The controller selects a first one of the segments, and selects at least two second segments from segments other than the first segment, and provides non-volatility to the selected segments Configured to
The at least two second segments are dynamically changed in a ring buffer manner in the remaining segments. The method of claim 16,
Further comprising an auxiliary power supply configured to supply auxiliary power when the power from the external host device is cut off,
When the auxiliary power is supplied after the power is cut off, the controller is further configured to back up data stored in the selected segments to the nonvolatile memory device, and
When the power is supplied again from the external host device, the controller is further configured to load the backed-up data into the selected segments. The method of claim 16,
The controller provides the first segment as a storage space of a super block of the journal area of the external host device, and the at least two second segments of at least the journal area of the external host device. A storage device further configured to serve as a storage space for one transaction. The method of claim 16,
The controller exposes the second area to the external host device as both the second access area in the block unit and the third access area in the byte unit. A method of operating a storage device comprising a non-volatile memory device and a dynamic random access memory:
Providing a portion of the storage space of the nonvolatile memory device as a user area to an external host device; And
And providing a portion of the storage space of the dynamic random access memory to the external host device as a journal area in which writing in bytes and reading in blocks are allowed,
The storage space of the journal area includes segments,
Providing the external host device as the journal area includes providing non-volatility to a fixed first segment of the segments and at least two second segments that are dynamically changed. How it works.

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