KR20200030911A - Multi channel high resolution video system - Google Patents

Abstract

The present invention relates to a multichannel high resolution image system. The multichannel high resolution image system comprises: a plurality of input devices that decode each of a plurality of different original images prestored for transmission of a multichannel image as a control signal is received; a matrix switcher that receives each of the decoded original images from the plurality of input devices through an input terminal, determines an order of output terminals according to preset output information, corrects the decoded original images, and generates an output clock for outputting the corrected original images through the output terminals; and a plurality of output devices outputting the corrected original images transmitted according to the output clock on a screen. Therefore, there is an effect of reducing memory usage of the matrix switcher and outputting a clearer image.

Description

Multi-channel high resolution video system {MULTI CHANNEL HIGH RESOLUTION VIDEO SYSTEM}

The disclosed technology relates to a system for outputting multi-channel high-resolution images.

Currently, only some channels are broadcasting UHD quality, but it is expected that in the near future UHD quality broadcasting will be transmitted from all channels. Accordingly, interest in a system supporting 4K ultra-high definition images is increasing, centering on companies providing video services.

On the other hand, when outputting such a high-definition image quality, when a plurality of images are input, a matrix switcher that performs a relaying role is transmitted to be transmitted to a specific port. The matrix switcher is capable of setting a transmission path for each of a plurality of images input according to a table set therein like a router of a network. Accordingly, each inputted image is output through a different display.

On the other hand, in the conventional case, the matrix switcher simply serves to set the port for outputting the image, so if the image processing bandwidth is sufficiently secured, there is little difficulty in performing the function. However, when the number of channels increases or the number of image data increases, a problem such as exceeding the image processing bandwidth or increasing the memory usage of the matrix switcher causes a lag on the screen.

Referring to Korean Patent Registration No. 10-1600865 (Invention name: HD / UHD-class multi-channel video data routing switch system and method for studio), routing video data to a specific port and performing switching simultaneously, one at each port A technique for preventing a rack by integrating the above channels has been disclosed. However, in a system having a certain number of channels, it may be efficient, but since each channel has a different setting according to video transmission, a lag may occur and an increase in the amount of processed video data may still cause the same problem.

The disclosed technology is to provide a multi-channel high resolution imaging system that reduces image processing bandwidth and memory usage of a matrix switcher.

In order to achieve the above technical problem, a first aspect of the disclosed technology is a plurality of input devices for decoding each of a plurality of different original images pre-stored for transmission of a multi-channel image as a control signal is received, and the plurality of inputs through an input terminal. Each received original decoded image from the input device determines the order of the output terminal according to the preset output information, corrects the decoded original image, and generates an output clock for outputting the corrected original images through the output terminal The present invention provides a multi-channel high-resolution image system including a matrix switcher and a plurality of output devices that output the corrected original images transmitted according to the output clock on a screen.

The second aspect of the disclosed technology to achieve the above technical problem is a plurality of frame buffers for storing a plurality of image data transmitted through a plurality of input terminals, a separate output clock for outputting the plurality of image data, and the Memory for storing a transmission table for outputting a plurality of image data and calling the transmission table to set an output path for each of the plurality of image data and changing a clock signal included in the plurality of image data to the output clock Accordingly, there is provided a matrix switcher including a processor that aligns a starting point of the image data.

Embodiments of the disclosed technology may have effects including the following advantages. However, since the embodiments of the disclosed technology are not meant to include all of them, the scope of rights of the disclosed technology should not be understood as being limited thereby.

According to an embodiment of the disclosed technology, a multi-channel high-resolution image system has an advantage of receiving an image from an input device even with a low image processing bandwidth of a matrix switcher.

In addition, there is an effect of reducing the memory usage of the matrix switcher by processing the uncorrected original image.

Also, when outputting the original image, there is an effect of outputting a clearer image through chroma upsampling.

1 is a block diagram of a multi-channel high-resolution imaging system according to an embodiment of the disclosed technology.
2 is a block diagram of a matrix switcher according to one embodiment of the disclosed technology.
3 is a view showing a control signal transmitted by using a remote control according to an embodiment of the disclosed technology.
4 is a diagram showing that the clock of the original video signal is changed to the output clock of the matrix switcher.

The present invention can be applied to various changes and may have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, A, B, etc. may be used to describe various components, but the components are not limited by the above terms, and only for the purpose of distinguishing one component from other components Used only. For example, the first component may be referred to as a second component without departing from the scope of the present invention, and similarly, the second component may be referred to as a first component. The term and / or includes a combination of a plurality of related described items or any one of a plurality of related described items.

It should be understood that a singular expression in the terminology used herein includes a plural expression unless the context clearly interprets otherwise. And the term "comprises" means that there are features, numbers, steps, operations, components, parts or combinations of the features described, and one or more other features, numbers, steps, operating elements, parts. Or it should be understood that it does not exclude the possibility of the presence or addition of those in combination.

Prior to the detailed description of the drawings, it is intended to clarify that the division of components in this specification is only divided by the main functions of each component. That is, two or more components to be described below may be combined into one component, or one component may be divided into two or more for each subdivided function.

In addition, each of the components to be described below may additionally perform some or all of the functions of other components in addition to the main functions in charge of the components, and some of the main functions of each of the components are different. Needless to say, it may also be carried out in a dedicated manner. Therefore, the presence or absence of each component described through this specification should be interpreted functionally.

1 is a block diagram of a multi-channel high-resolution imaging system according to an embodiment of the disclosed technology. Referring to FIG. 1, the multi-channel high resolution imaging system 100 includes a plurality of input devices 110, a matrix switcher 120, and a plurality of output devices 130.

The plurality of input devices 110 store a plurality of original images for multi-channel image transmission. Referring to FIG. 1, different images are stored in each of the input devices 110a, 110b, 110c, and 110d. Then, when a control signal is received, each of the input devices 110a, 110b, 110c, and 110d decodes the original image.

As described above, the plurality of input devices 110 store different original images as described above. For example, an image of 60p may be stored in the input device 1110a, and an image of 30p may be stored in the input device 2110b. Of course, even if 60p images are stored identically to each other, images of other contents that are not related at all may be stored.

Meanwhile, each input device 110 decodes the original image stored according to different clocks. For example, the input devices 1 to 4 (110a, 110b, 110c, 110d) may be provided with different models or different products. The input devices 110 may be provided with the same model or product, but in this case, since all input devices 110 must be provided with the same in advance, some limitations in configuring the system occur. On the other hand, in the case of the present application, it is possible to have a slight advantage in that a device for storing the original image can be freely provided regardless of its type.

On the other hand, each input device 110 decodes each stored image and outputs a signal based on the respective clock. Each of the input devices 110 decodes the original image stored by each using a decoding module provided. At this time, in the conventional case, it is common to increase the capacity of image data in order to improve image quality or clarity while decoding an image. For example, an input device may perform both decoding and correction of an image, and a matrix switcher or display may output it as it is. In this case, since the amount of data of the processed image increases, in the disclosed technology, the input device 110 performs only decoding of the original image and correction of the decoded image is performed by the matrix switcher 120 below.

The matrix switcher 120 receives a plurality of decoded original images transmitted from the input device 110 through an input terminal. The matrix switcher 120 receives each original image transmitted to each input device and stores it in a frame buffer. At this time, the number of frame buffers is the same as the number of each input image. For example, if there are four input original images, the frame buffer may also be four.

On the other hand, the matrix switcher 120 may output each original image to a specific output terminal (Port) like a conventional matrix switcher or matrix switch. The matrix switcher 120 can determine the order of output terminals according to preset output information. In one embodiment, the matrix switcher 120 may include a transmission table for setting an output terminal for each of the decoded original images, and determine the order of terminals output for each original image based on the transmission table. That is, the original image transmitted from the input device 1 (110a) can be set to be transmitted by the output device 2 (130b) or the original image transmitted from the input device 4 (110d) is transmitted by the output device 3 (130c). Of course, the original image transmitted from the input device 1 (110a) may be transmitted to two or more output devices, or an image transmitted from one input device may be transmitted to all output devices.

On the other hand, as described above, the output information capable of setting the output path for each original image is a transmission table set in the matrix switcher 120 as described above, or the administrator inputs a table value before the system 100 is installed or It may be set by inputting a table value directly to the matrix switcher 120 in the field where the system 100 is installed.

Meanwhile, the matrix switcher 120 receives the decoded original images and corrects the decoded original images after setting an output path for each original image according to output information. That is, correction is performed for each original image at the output terminal. Correction of the image may be performed in a manner that allows a person to sense the image quality improvement more sensitively when the image is viewed by the human eye. In one embodiment, the matrix switcher 120 may perform chroma upsampling on each original image to correct the original image of the YUV 420 format to the YUV422 format.

On the other hand, the matrix switcher 120 has an output terminal for transmitting the image on the opposite side provided with the input terminal to which the original image is transmitted. The matrix switcher 120 outputs a chroma up-sampled image using an output terminal. At this time, the matrix switcher 120 is not the clock of the input devices 110 that decodes the original images, but the output clock generated by the matrix switcher 120 itself. Each original image is output accordingly. To this end, the matrix switcher 120 generates an output clock for video transmission.

In the case of a general multi-channel video transmission system, when an image is input to a matrix switcher, decoding and correction of the image are performed, and the matrix switcher simply sets a path for outputting these images. That is, the input device simply determines to which port the video signal transmitted according to its clock is output. If an error is included in the video signal transmitted from the input device, the corresponding jitter characteristics are matrixed as it is. It can be delivered to the output device via a switcher. Due to this problem, there is a possibility that at least one of the output devices outputting a multi-channel image may flicker on the screen or may be interrupted in a specific section depending on the jitter characteristics of each.

Therefore, in the disclosed technology, in order to prevent this phenomenon, the matrix switcher 120 generates a separate output clock and transmits each original image to the output device 130 based on this. According to this method, since the video signal is not output according to the clock of the input device 110, the jitter characteristic of the clock of the input device 110 disappears and the signal of the original video is output according to the output clock of the matrix switcher 120. It is possible to output the screens of each output device cleanly without errors.

The output device 130 outputs the images transmitted according to the output clock set in the matrix switcher 120 on the screen. Here, the images transmitted to the output device 130 are corrected according to chroma upsampling in the matrix switcher 120, and the capacity is slightly increased compared to the original images transmitted from the input device 110 to the matrix switcher 120. have. This is because the color values included in the original image slightly increased as chroma upsampling was applied. Since this correction is applied when each image is transmitted to the output device 130 rather than when it enters the matrix switcher 120, the size of the bandwidth in which the actual matrix switcher 120 processes image data is reduced compared to the prior art, and the memory usage is also Is saved. Depending on the size of the image and the number of input devices 110 and output devices 130, the degree of bandwidth reduction and the amount of memory usage reduction may vary.

2 is a block diagram of a matrix switcher according to one embodiment of the disclosed technology. Referring to FIG. 2, the matrix switcher 120 includes a frame buffer 120a, a clock generation module 120b, a processor 120c, and a chroma upsampling module 120d. The frame buffer 120a stores decoded images transmitted from the input devices 110. The capacity of the frame buffer 120a may vary slightly depending on the type of the matrix switcher 120, but the number of buffers is the same as the number of original images input from the input device 110. Referring to FIG. 2, since the matrix switcher 120 has four input ports and output ports, the number of original images input from the input device 110 is four corresponding to the number of input ports.

The clock generation module 120b generates an output clock for outputting an image according to a preset value stored in the matrix switcher 120. The output clock can be arbitrarily set by the user of the system 100 or the default value of the matrix switcher 120 can be used.

The processor 120c transmits the original images decoded according to the output clock to the output terminal. The processor 120c executes control commands for the overall operation of the matrix switcher 120 and may be configured as one with the clock generation module 120b.

The chroma upsampling module 120d performs chroma upsampling of the decoded original images transmitted to the output terminal. As described above, the original image in YUV 420 format may be corrected in YUV 422 format. At this time, the chroma upsampling is performed at the time when the original image is transmitted through the output terminal. For example, chroma upsampling may be performed after setting an output path for each original image and replacing the clock of the input device 110 included in the original image with the output clock of the matrix switcher 120.

3 is a view showing that the control signal 101a is transmitted using a remote control according to an embodiment of the disclosed technology. Referring to FIG. 3, a plurality of input devices 110a to 110d are wirelessly connected to a remote control 101 that transmits a control signal 101a. In one embodiment, the remote control 101 and each input device (110a ~ 110d) may be wirelessly connected through a predetermined channel so as not to be affected by the signal of the other remote control or terminal.

Meanwhile, the remote control 101 generates a control signal 101a when at least one button provided on the body is input from the user. And between the images transmitted from each of the input devices (110a ~ 110d) in the process of simultaneously transmitting to a plurality of input devices (110a ~ 110d) matrix switcher 120 to match the start time of each image using a separate output clock The decoding process of each of the input devices 110a to 110d may be controlled to proceed at least at the same or similar moments so that the difference of does not exceed the size of the frame buffer.

4 is a diagram showing that the clock of the original video signal is changed to the output clock of the matrix switcher 120. 4, the matrix switcher 120 replaces the clock included in the original image of the input device 110 with the output clock generated by itself. Each of the input devices 110 transmits the signal of the original video decoded according to the respective clock to the matrix switcher 120. At this time, the characteristics of the unfavorable jitter according to the clock of each input device may be included in the signal of the original image. This is that the matrix switcher 120 creates a new clock and applies it to the signal of the original image, but it is possible to restore the image. However, if the signal of the original image is transmitted to the output device using the clock of the input device as it is, this jitter characteristic will be expressed as it is. You can.

In a matrix switcher without a conventional frame memory, the problem of jitter characteristics due to the clock of the input device cannot be solved unless a separate genlock circuit is provided. However, in the matrix switcher 120 according to the disclosed technology, it is possible to solve the jitter problem by using a separate output clock generated by the user instead of the clock of the input device according to the method described above.

On the other hand, the matrix switcher according to an embodiment of the disclosed technology may be implemented as a frame buffer, a memory, and a processor in terms of actual devices.

The frame buffer stores a plurality of image data respectively transmitted through a plurality of input terminals. Similar to the frame buffer 120a described above with reference to FIG. 2, the frame buffer provided in the actual matrix switcher is provided with the same number of image data.

The memory is a data recording device provided in the matrix switcher. The memory stores a separate output clock and a transmission table for outputting image data in advance. The user of the matrix switcher can input an output clock and a transmission table through an external input device or a user interface provided in the matrix switcher.

The processor is an arithmetic unit provided in the matrix switcher, and sets an output path for each of a plurality of image data by calling a transfer table from memory. For example, a path may be set to transmit each image data to an output terminal of a specific port according to routing information included in a transmission table.

Meanwhile, when the output path is set, the processor changes the clock signal included in the plurality of image data to an output clock stored in the memory. That is, the start times of the different image data are set to the same viewpoint. In general, image data has a format in which a number of frames are connected, but some frames in the front part remain black and indicate a specific value from the frame where the image starts. That is, the processor can determine when the start time of each image data stored in the frame buffer starts, so that the timing of these image data can start at the same time in the frame buffer.

Meanwhile, the processor outputs the image data by chroma upsampling after aligning the starting point of the image data. In one embodiment, the processor may convert image data from YUV 420 format to YUV 422 format according to chroma upsampling. Therefore, the video data coming into the frame buffer is processed at a relatively low capacity, and it is possible to reduce the amount of memory used slightly by controlling the output to the same point using the output clock without having to separately control the output settings for the video data. Since it does not follow various jitter characteristics included in the image data, it is possible to provide a higher quality multi-channel image.

The multi-channel high-resolution image system according to an embodiment of the disclosed technology has been described with reference to the embodiment shown in the drawings for ease of understanding, but this is only exemplary, and various modifications can be made by those skilled in the art. And it will be understood that other equivalent embodiments are possible. Therefore, the true technical protection scope of the disclosed technology should be defined by the appended claims.

100: multi-channel high-resolution video system 110: input device
120: matrix switcher 130: output device

Claims (11)

A plurality of input devices for decoding each of a plurality of different pre-stored original images for transmission of a multi-channel image as a control signal is received;
Receiving each of the decoded original images from the plurality of input devices through an input terminal, determining an output path according to preset output information, correcting the decoded original images, and outputting the corrected original images through the output terminal A matrix switcher for generating an output clock for the; And
And a plurality of output devices outputting the corrected original images transmitted according to the output clock on a screen. According to claim 1, wherein the matrix switcher,
A frame buffer for receiving the decoded original images;
A clock generation module that generates the output clock according to a pre-stored set value;
A processor that transmits the decoded original images to the output terminal according to the output clock; And
And a chroma upsampling module for chroma upsampling the decoded original images transmitted to the output terminal. According to claim 1,
The plurality of input devices are multi-channel high-resolution imaging systems that respectively transmit the plurality of original images to the matrix switcher according to different clocks. According to claim 1,
The plurality of input devices are wirelessly connected to a remote control that transmits the control signal, and the remote control is a multi-channel high-resolution image system that simultaneously transmits the control signal to the plurality of input devices when at least one button is input. According to claim 1,
The matrix switcher is a multi-channel high-resolution image system including a transmission table that sets an output terminal for each of the decoded original images. According to claim 1,
The matrix switcher is a multi-channel high resolution image system that performs chroma upsampling on the decoded original image after generating the output clock. The method of claim 6,
The matrix switcher is a multi-channel high resolution image system that converts the decoded original image from YUV 420 format to YUV 422 format through the chroma upsampling. According to claim 1,
The matrix switcher stores each of the decoded original images in a frame buffer of the same number as the number of the decoded original images, and sets a time point at which the decoded original images are output in the frame buffer according to the output clock. Channel high resolution imaging system. A plurality of frame buffers for storing a plurality of image data respectively transmitted through a plurality of input terminals;
A memory for storing a separate output clock for outputting the plurality of image data and a transmission table for outputting the plurality of image data; And
And a processor for setting an output path for each of the plurality of image data by calling the transmission table and changing a clock signal included in the plurality of image data to the output clock to align the starting point of the image data. Matrix switcher. The method of claim 9,
The processor is a matrix switcher that outputs the chroma data by chroma upsampling after the start time of the image data is aligned. The method of claim 8,
The processor is a matrix switcher that converts the image data from YUV420 format to YUV422 format according to the chroma upsampling.

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