KR20200014175A - Apparatus and method for performing garbage collection to predicting required time - Google Patents

Abstract

The present invention relates to a memory system for supporting garbage collection and an operating method thereof. The memory system comprises: a non-volatile memory device including a plurality of pages each including a plurality of memory cells, a plurality of blocks each including the pages, a plurality of planes each including the blocks, and a plurality of dies each including the planes, and including page buffers for caching data inputted/outputted to the blocks in page units; and a controller to group parallel-readable N blocks among the blocks in accordance with a set condition to manage grouped blocks as super blocks, generate required prediction times obtained by predicting and calculating required time needed when extracting valid data from the blocks for garbage collection in super block units, and refer to the required prediction times to select a victim block for the garbage collection among the blocks.

Description

APAPATUS AND METHOD FOR PERFORMING GARBAGE COLLECTION TO PREDICTING REQUIRED TIME}

The present invention relates to a memory system, and more particularly, to a memory system that supports garbage collection and a method of operating the memory system.

Recently, the paradigm of the computer environment has been shifted to ubiquitous computing, which enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like is increasing rapidly. Such portable electronic devices generally use a memory system using a memory device, that is, a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of a portable electronic device.

Unlike a hard disk, a data storage device using a nonvolatile memory device has no mechanical driving part, and thus has excellent stability and durability, and has an advantage of fast access to information and low power consumption. As an example of a memory system having such an advantage, a data storage device may include a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

According to an embodiment of the present invention, a memory for predicting a time required for extracting valid data from a block for garbage collection in superblock units and then selecting a victim block for garbage collection based on the predicted time required It provides a method of operating a system and a memory system.

A memory system according to an exemplary embodiment of the present invention may include a plurality of pages each including a plurality of memory cells, a plurality of blocks each including the pages, and a plurality of blocks, respectively. A plurality of planes including a plurality of planes, a plurality of dies each including the planes, and page buffers for caching data output from the blocks in units of pages. A nonvolatile memory device; And N blocks capable of parallel reading among the blocks according to a set condition to be managed as a plurality of superblocks, and required for extracting valid data from the blocks for garbage collection. A controller for generating predicted time predictions calculated by calculating a time in superblock units, and selecting a victim block for the garbage collection among the blocks by referring to the required prediction time, wherein N is a natural number of 2 or more Can be.

In addition, when the parallel read is possible only for pages of the same position in each of the N blocks grouped in the first superblock among the superblocks, the controller may be configured to generate a first number of valid pages of each of the N blocks. After calculating the first time obtained by multiplying the lead prediction time by the number obtained by subtracting the number of valid pages having the same position in the N blocks grouped in the first superblock, and calculating the second time by multiplying the transmission prediction time by the first number, The required time is generated by adding the first time and the second time, and a required prediction time generation method applied to the first super block is applied to each of the superblocks. Generating prediction times, and the read prediction time is a time for predicting that it will take to cache data of the blocks in the page buffers, and the transmission prediction time. The time may be a time for predicting that it will take to transmit data cached in the page buffers to the controller.

The controller reads the largest number of valid pages of each of the N blocks when parallel reading is possible for pages at different positions in each of the N blocks grouped in the second superblock among the superblocks. After calculating the third time multiplied by the prediction time and the fourth time multiplied by the estimated transmission time by the sum of the number of valid pages of each of the N blocks, the third time is added to the fourth time and the second super is added. Generating a required prediction time corresponding to a block; and generating the required prediction times by applying a method of generating a required prediction time applied to the second super block to each of the superblocks, and the read prediction time includes: The time to predict that it will take to cache data in the page buffers, and the transmission prediction time, the data cached in the page buffers It can be predicted that it will take time to transfer to the roller.

In addition, whenever a block having a variable number of valid pages occurs among the blocks, the controller may predictively calculate a value of a required prediction time corresponding to a superblock in which a block having a variable number of valid pages is grouped. have.

In addition, the controller checks whether there is a block having a variable number of valid pages among the blocks at each set time point, and if there is a check result, a required prediction corresponding to a superblock in which a block having a variable number of valid pages is grouped is present. The value of time can be predicted again.

The controller may select, as the victim block, a block including at least one or more valid pages among N blocks grouped in a superblock corresponding to a relatively small value of the required prediction time. .

The controller may further include N blocks grouped into one selected superblock when the number of valid pages of each of the N blocks grouped in each of the superblocks is equal to or less than a set number. At least two of the N blocks grouped in the superblock corresponding to the relatively smallest value among at least two or more required prediction time values corresponding to at least two or more superblocks are selected as the victim blocks and are at least two or more. A block including one or more valid pages may be selected as the victim block.

In addition, when the N blocks grouped in the third superblock among the superblocks are selected as the victim blocks, and all valid data is moved to the target block through the garbage collection, the controller may include the first block. 3 The required forecast time corresponding to the superblock can be set as a predetermined value.

The controller may generate and manage the required prediction times in a section in which the number of free blocks among the blocks is less than or equal to a first number, and in the section in which the required number of times is greater than or equal to the second number greater than the first number. You may not manage the times.

In addition, a first one of the dies is connected to a first channel, a second one of the dies is connected to a second channel, and the planes included in the first die are connected to the first channel. Are connected to a plurality of shared first paths, and the planes included in the second die are connected to a plurality of second paths sharing the second channel, and the controller is connected to the first die of the first die. Grouping a first block included in a first plane and a second block included in a second plane of the first die, and a third block and the second included in a third plane of the second die Grouping the fourth block included in the fourth plane of the die into the set condition, or the first block included in the first plane of the first die and the third plane of the second die Grouping a third block included in the second block, and a second block included in the second plane of the first die; Grouping the fourth block included in the fourth plane of the second die into the set condition, or the first block included in the first plane of the first die and the first die of the first die; The set condition includes grouping a second block included in two planes, a third block included in a third plane of the second die, and a fourth block included in a fourth plane of the second die. You can.

A method of operating a memory system according to still another embodiment of the present invention includes a plurality of pages each including a plurality of memory cells, a plurality of blocks each including the pages, and a plurality of pages. And a plurality of planes each including the blocks, a plurality of dies each including the planes, and caching data output from the blocks in units of pages. A method of operating a memory system including a nonvolatile memory device including page buffers, the method comprising: grouping N blocks capable of parallel reading among the blocks according to a set condition and managing the plurality of superblocks as a plurality of superblocks; A generation step of generating prediction time required by calculating a necessary time required to extract valid data from the blocks for garbage collection in a superblock unit; And selecting a victim block for the garbage collection among the blocks with reference to the required prediction times, where N may be a natural number of two or more.

In addition, when parallel reading is possible only for pages of the same position in each of the N blocks grouped in the first superblock among the superblocks, the generating step is effective for each of the N blocks grouped in the first superblock. Calculating a first time obtained by multiplying a lead prediction time by a number obtained by subtracting the number of valid pages having the same position in the N blocks grouped in the first superblock by the first number of pages; Calculating a second time obtained by multiplying the first number by a transmission prediction time; Generating a required prediction time corresponding to the first super block by adding the first time and the second time; And generating the required prediction times by applying a method of generating the required prediction time applied to the first superblock to each of the superblocks, wherein the read prediction time comprises: generating data of the blocks from the page buffers. It is a time to estimate that it will take to cache, and the transmission prediction time may be a time to predict that it will take to transmit data cached in the page buffers to the controller.

Further, when parallel reading is possible for pages at different positions in each of the N blocks grouped in the second superblock among the superblocks, the generating step may include generating each of the N blocks grouped in the second superblock. Calculating a third time obtained by multiplying a lead prediction time by the largest number of valid pages; Calculating a fourth time obtained by multiplying a transmission prediction time by a sum of the total number of valid pages of each of the N blocks grouped in the second superblock; Generating a required prediction time corresponding to the second superblock by adding the third time and the fourth time; And generating the required prediction times by applying the method of generating the required prediction time applied to the second superblock to each of the superblocks, wherein the read prediction time includes the data of the blocks in the page buffers. It is a time to estimate that it will take to cache, and the transmission prediction time may be a time to predict that it will take to transmit data cached in the page buffers to the controller.

The method may further include predicting and calculating a value of a required prediction time corresponding to the superblock in which the variable number of valid pages is grouped each time a block having a variable number of valid pages occurs. Can be.

In addition, it is determined whether a block having a variable number of valid pages among the blocks exists at each set time point, and if a check result is present, a required predictive time value corresponding to a superblock in which the variable number of valid pages is grouped is determined. The method may further include performing a prediction operation.

The selecting may include selecting, as the victim block, a block including at least one or more valid pages among N blocks grouped in a superblock corresponding to the required prediction time having a relatively small value among the required prediction times. have.

The selecting may include selecting N blocks grouped into one selected superblock when there is one superblock whose total number of valid pages of each of the N blocks grouped into each of the superblocks is equal to or less than a set number. Selecting the sacrificial block; And at least two or more prediction times corresponding to at least two or more superblocks when the number of valid pages of each of the N blocks grouped in each of the superblocks is equal to or smaller than a set number. The method may include selecting, as the victim block, a block including at least one or more valid pages among N blocks grouped in a superblock corresponding to a relatively small value among the values of.

In addition, when N blocks grouped in a third superblock among the superblocks are selected as the victim blocks and all valid data is moved to a target block through the garbage collection, the third superblock is included in the third superblock. The method may further include setting a corresponding required prediction time to a predetermined value.

The generating may include generating and managing the required prediction times in a section in which the number of free blocks among the blocks is less than or equal to a first number; And managing the required prediction times in a section in which the number of free blocks among the blocks is greater than or equal to the second number greater than the first number.

In addition, a first one of the dies is connected to a first channel, a second one of the dies is connected to a second channel, and the planes included in the first die are connected to the first channel. Are connected to a plurality of shared first paths, and the planes included in the second die are connected to a plurality of second paths sharing the second channel. Grouping a first block included in a first plane and a second block included in a second plane of the first die, and a third block and the third block included in a third plane of the second die Grouping a fourth block included in the fourth plane of the second die, or including a first block included in the first plane of the first die and a third plane included in the third plane of the second die; Grouping three blocks, and a second block included in the second plane of the first die and the second die Grouping a fourth block included in four planes, or a first block included in a first plane of the first die and a second block included in a second plane of the first die; Grouping the third block included in the third plane of the second die and the fourth block included in the fourth plane of the second die.

The present technology predicts the time required to extract valid data from blocks for garbage collection in superblock units, and then selects a victim block for garbage collection based on the predicted time required.

This minimizes the time it takes to perform garbage collection.

In addition, the performance of the memory collection is minimized due to the performance of the garbage collection.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.
2 is a diagram illustrating a controller in a memory system according to another exemplary embodiment of the present invention.
3 is a diagram illustrating an example of garbage collection used in a memory system according to an embodiment of the present invention.
4 is a diagram illustrating a concept of a super memory block used in a memory system according to an exemplary embodiment of the present invention.
5A and 5B illustrate garbage collection for a super memory block in a memory system according to a first embodiment of the present invention.
FIG. 6 is a diagram for explaining an operation of selecting a victim block when garbage collection is performed on a super memory block in the memory system according to the first embodiment of the present invention described with reference to FIGS. 5A and 5B.
7A and 7B illustrate garbage collection for a super memory block in a memory system according to a second embodiment of the present invention.
FIG. 8 is a diagram for explaining an operation of selecting a victim block when garbage collection is performed on a super memory block in a memory system according to the second embodiment of the present invention described with reference to FIGS. 7A and 7B.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1, the data processing system 100 includes a host 102 and a memory system 110.

In addition, the host 102 includes electronic devices, such as portable electronic devices such as mobile phones, MP3 players, laptop computers, or the like, or electronic devices such as desktop computers, game consoles, TVs, projectors, and the like, that is, wired and wireless electronic devices.

In addition, the host 102 includes at least one operating system (OS), and the operating system manages and controls the functions and operations of the host 102 as a whole, and the data processing system 100 or Provides interaction between the user and host 102 using the memory system 110. Here, the operating system supports functions and operations corresponding to a user's purpose and purpose of use, and may be classified into a general operating system and a mobile operating system according to, for example, mobility of the host 102. In addition, the general operating system system in the operating system may be divided into a personal operating system and a corporate operating system according to the user's use environment. For example, the personal operating system is characterized to support a service providing function for the general user. The system includes windows and chrome, and the enterprise operating system is a system specialized to secure and support high performance, such as windows server, linux and unix. It may include. In addition, the mobile operating system in the operating system is a system specialized to support the mobility service providing function and the power saving function of the user, and may include Android, iOS, Windows mobile and the like. . In this case, the host 102 may include a plurality of operating systems, and also executes the operating system to perform an operation with the memory system 110 corresponding to a user request. ) Transmits a plurality of commands corresponding to the user request to the memory system 110, and accordingly, the memory system 110 performs operations corresponding to the commands, that is, operations corresponding to the user request.

In addition, the memory system 110 operates in response to a request from the host 102 and, in particular, stores data accessed by the host 102. In other words, the memory system 110 may be used as a main memory or an auxiliary memory of the host 102. The memory system 110 may be implemented as one of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may include a solid state drive (SSD), an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), and a micro-MMC type multimedia card (MMC). Multi Media Card (SD), Secure Digital (SD) cards in the form of SD, mini-SD, micro-SD, Universal Storage Bus (USB) storage devices, Universal Flash Storage (UFS) devices, Compact Flash (CF) cards, The storage device may be implemented as one of various types of storage devices such as a smart media card, a memory stick, and the like.

In addition, the storage devices for implementing the memory system 110 may include volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), read only memory (ROM), mask ROM (MROM), and programmable PROM (PROM). Non-volatile memory devices such as ROM, erasable ROM (EPROM), electrically erasable ROM (EEPROM), ferromagnetic ROM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and flash memory. Can be implemented.

The memory system 110 includes a memory device 150 that stores data accessed by the host 102, and a controller 130 that controls data storage in the memory device 150.

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to form an SSD. When the memory system 110 is used as an SSD, an operating speed of the host 102 connected to the memory system 110 may be further improved. In addition, the controller 130 and the memory device 150 may be integrated into one semiconductor device to configure a memory card. For example, a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash card (CF) Memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), etc. can do.

In another example, the memory system 110 may include a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, and a web tablet. ), Tablet computer, wireless phone, mobile phone, smart phone, e-book, portable multimedia player, portable game console, navigation (navigation) devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3-dimensional televisions, smart televisions, digital audio recorders recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, data center Make up Storage, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID (radio frequency identification) device, or one of various components constituting the computing system.

Meanwhile, the memory device 150 in the memory system 110 may maintain stored data even when power is not supplied. In particular, the memory device 150 may store data provided from the host 102 through a write operation and read the data. The stored data is provided to the host 102 through the operation. In this case, the memory device 150 may include a plurality of memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 may include a plurality of pages P <0>, P <1>, P <2>, P <3>, P <4>, ...>. It may include. In addition, each of the pages P <0>, P <1>, P <2>, P <3>, P <4>, ...> may include a plurality of memory cells (not shown). It may include. Each of the memory blocks 152, 154, and 156 includes page buffers (not shown) for caching input / output data in page units. In addition, the memory device 150 may include a plurality of planes (not shown) including a plurality of memory blocks 152, 154, and 156, respectively. In addition, the memory device 150 may include a plurality of memory dies (not shown) each including a plurality of planes. In addition, the memory device 150 may be a nonvolatile memory device, for example, a flash memory, and in this case, the flash memory may have a three-dimensional stack structure.

The controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102. For example, the controller 130 provides the data read from the memory device 150 to the host 102, and stores the data provided from the host 102 in the memory device 150. The memory device 150 controls operations of read, write, program, erase, and the like of the memory device 150.

In more detail, the controller 130 includes a host interface HOST INTERFACE 132, a processor 134, a memory interface 142, and a memory 144.

In addition, the host interface 132 processes commands and data of the host 102, and includes a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile (MIPI) It may be configured to communicate with the host 102 via at least one of various interface protocols, such as Industry Processor Interface. Here, the host interface 132 may be driven through firmware called a host interface layer (HIL) as an area for exchanging data with the host 102. have.

In addition, the memory interface 142 may include a memory that performs an interface between the controller 130 and the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102. / Storage interface. Here, the memory interface 142 is a NAND flash controller (NFC) when the memory device 150 is a flash memory, particularly, for example, the memory device 150 is a NAND flash memory. According to the control, a control signal of the memory device 150 is generated and data is processed. The memory interface 142 is an interface for processing commands and data between the controller 130 and the memory device 150, for example, an operation of a NAND flash interface, in particular, data input / output between the controller 130 and the memory device 150. And a data exchange area with the memory device 150, and may be driven through a firmware called a flash interface layer (FIL).

In addition, the memory 144 is an operating memory of the memory system 110 and the controller 130, and stores data for driving the memory system 110 and the controller 130. More specifically, the memory 144 stores data necessary for the controller 130 to control the memory device 150 in response to a request from the host 102. For example, the controller 130 may be configured to provide data read from the memory device 150 to the host 102 and to store data provided from the host 102 in the memory device 150. When controlling the operation of the read, write, program, erase, and the like of 150, necessary data is stored.

Herein, the memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like. In addition, the memory 144 may be included in the controller 130 as shown in FIG. 1. In addition, the memory 144 may exist outside the controller 130 differently from that shown in FIG. 1, and in this case, external volatile data input / output from the controller 130 through a separate memory interface (not shown). It may be implemented in memory.

In addition, as described above, the memory 144 may include data necessary for performing operations such as data write and read between the host 102 and the memory device 150, and data when performing operations such as data write and read. For storing such data, the program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, map buffer / cache, etc. may be included. .

The processor 134 controls the overall operation of the memory system 110, and in particular, controls the program operation or the read operation of the memory device 150 in response to a write request or a read request from the host 102. do. Here, the processor 134 drives a firmware called a flash translation layer (FTL) to control the overall operation of the memory system 110. In addition, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

For example, the controller 130 performs an operation requested by the host 102 in the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU), that is, the host ( The command operation corresponding to the command received from 102 is performed with the memory device 150. Here, the controller 130 performs a foreground operation with a command operation corresponding to a command received from the host 102, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, and an erase operation. An erase operation corresponding to a command (erase command), a parameter set operation corresponding to a set parameter command or a set feature command may be performed using a set command.

In addition, the controller 130 may perform a background operation on the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU). The background operation of the memory device 150 may include copying and storing data stored in an arbitrary memory block into another arbitrary memory block in the memory blocks 152, 154, and 156 of the memory device 150. For example, it may include garbage collection (GC) operation. As such, since the processor 134 may control the garbage collection operation as a background operation of the memory device 150, the garbage collection control unit 196 may be included in the processor 134 as shown in the drawing. In addition, the background operation of the memory device 150 may include swapping between the memory blocks 152, 154, and 156 of the memory device 150 or between data stored in the memory blocks 152, 154 and 156. Processing to include, for example, wear leveling (WL). The background operation of the memory device 150 may include storing map data stored in the controller 130 to the memory blocks 152, 154, and 156 of the memory device 150, for example, a map flush. ) May be included. Also, a background operation of the memory device 150 may include bad management of the memory device 150, for example, a plurality of memory blocks 152, 154, and 156 included in the memory device 150. ) May include a bad block management operation of identifying and processing a bad block.

The processor 134 of the controller 130 may include components (not shown) for performing bad management of the memory device 150. In this case, the component for performing bad management of the memory device 150 may check the bad block in the plurality of memory blocks 152, 154, and 156 included in the memory device 150, and then check the bad block. Perform bad block management for bad processing. Here, in the bad management, when the memory device 150 is a flash memory, for example, a NAND flash memory, a program fail may occur during a data write, for example, a data program due to the characteristics of the NAND. After bad processing of a memory block in which a failure occurs, the program failed data is written into a new memory block, that is, programming.

2 is a diagram illustrating a controller in a memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 2, the controller 130 interoperating with the host 102 and the memory device 150 may include a host interface 132, a flash translation layer (FTL) 40, a memory interface 142, and a memory device 144. ) May be included.

The host interface 132 is for exchanging commands and data transmitted from the host 102. For example, the host interface 132 may sequentially store commands, data, and the like transmitted from the host 102, and then output the command queue 56 and the command queue 56, which may be output according to the stored order. A buffer manager 52 capable of classifying commands, data, etc., or adjusting a processing order, and an event queue 54 for sequentially delivering events for processing commands, data, etc. delivered from the buffer manager 52. can do.

Commands and data from the host 102 may be successively delivered with a plurality of the same characteristics, or may be delivered with a mixture of instructions and data of different characteristics. For example, a plurality of instructions for reading data may be delivered, or read and program instructions may be alternately delivered. The host interface 132 sequentially stores the commands, data, and the like transmitted from the host 102 in the command queue 56 first. Thereafter, the controller 130 may predict what operation the controller 130 performs according to the characteristics of the command, data, and the like transmitted from the host 102, and may determine the processing order or priority of the command, the data, and the like based on this. In addition, depending on characteristics of commands, data, and the like transmitted from the host 102, the buffer manager 52 in the host interface 132 stores the commands, data, and the like in the memory device 144, or a flash translation layer (FTL). You can also decide to forward it to (40). The event queue 54 receives an event that the memory system or the controller 130 needs to execute and process internally according to the command, data, etc. transmitted from the host 102 from the buffer manager 52 and then flashes in the received order. May be passed to the transform layer (FTL) 40.

According to an embodiment, the flash translation layer (FTL) 40 is a host request manager (HRM) 46 for managing events received from the event specification 54, a map data manager for managing map data. (Map Manger (MM), 44), a state manager 42 for performing garbage collection or wear leveling, and a block manager 48 for performing a command on a block in the memory device.

For example, the host request manager (HRM) 46 may use the map data manager (MM, 44) and the block manager 48 to process read and program commands received from the host interface 132 and requests based on events. Can be. The host request manager (HRM) 46 sends a lookup request to the map data manager (MM, 44) to determine the physical address corresponding to the logical address of the forwarded request and a flash read request to the memory interface 142 for the physical address. You can process the read request by sending. The host request manager (HRM) 46, on the other hand, first programs the data to a specific page of the unwritten (no data) memory device by sending a program request to the block manager 48, and then the map data manager (MM, 44). By transmitting a map update request for the program request, the content of the data programmed in the mapping information of the logical-physical address can be updated.

Here, the block manager 48 converts the program request requested by the host request manager (HRM) 46, the map data manager (MM, 44), and the state manager 42 into a program request for the memory device 150 to store the memory. Blocks within the device 150 may be managed. In order to maximize the program or write performance of the memory system 110 (see FIG. 1), the block manager 48 may collect program requests and send flash program requests to the memory interface 142 for multi-plane and one-shot program operations. . In addition, various outstanding flash program requests may be sent to the memory interface 142 to maximize parallelism of the multi-channel and multi-directional flash controllers.

On the other hand, the block manager 48 manages flash blocks according to the number of valid pages, selects and erases blocks without valid pages when free blocks are needed, and includes least valid pages when garbage collection is required. You can select a block. In order for the block manager 48 to have enough free blocks, the state manager 42 may perform garbage collection to collect valid data, move it to an empty block, and delete blocks that contained the moved valid data. When the block manager 48 provides the state manager 42 with information about the block to be deleted, the state manager 42 may first check all the flash pages of the block to be deleted to determine whether each page is valid. . For example, to determine the validity of each page, state manager 42 identifies the logical address recorded in the Out Of Band (OOB) area of each page, and then the physical address and map manager 44 of the page. You can compare the actual addresses that are mapped to the logical addresses obtained from the query request. The state manager 42 may transmit a program request to the block manager 48 for each valid page, and when the program work is completed, the mapping table may be updated by updating the map manager 44.

The map manager 44 manages logical-physical mapping tables and can handle requests such as queries, updates, etc. generated by the host request manager (HRM) 46 and the state manager 42. The map manager 44 may store the entire mapping table in the flash memory, and cache the mapping item according to the capacity of the device 144 in the memory. If a map cache miss occurs while processing the query and update request, the map manager 44 may send a read request to the memory interface 142 to load the mapping table stored in the memory device 150. If the number of dirty cache blocks in map manager 44 exceeds a certain threshold, a program request may be sent to block manager 48 to create a clean cache block and the dirty map table may be stored in memory device 150.

On the other hand, if garbage collection is performed, the host request manager (HRM) 46 may program the latest version of the data for the same logical address of the page and issue an update request simultaneously while the state manager 42 copies a valid page. Can be. The map manager 44 may not perform the mapping table update when the state manager 42 requests the map update while the copy of the valid page is not normally completed. The map manager 44 can perform map update only if the latest map table still points to the old physical address to ensure accuracy.

According to an embodiment, at least one of the block manager 48, the map manager 44, or the state manager 42 described in FIG. 2 may include the garbage collection control unit 196 described in FIG. 3 below.

The memory device 150 may include a single level cell (SLC) memory block and a multi level cell (MLC) according to the number of bits capable of storing or representing a plurality of memory blocks in one memory cell. Cell) memory block, or the like. In this case, the SLC memory block includes a plurality of pages implemented by memory cells that store 1-bit data in one memory cell, and has fast data operation performance and high durability. The MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (for example, two bits or more bits) in one memory cell, and store data larger than the SLC memory block. It can have space, that is, it can be highly integrated. In particular, the memory device 150 is an MLC memory block that includes three MLC memory blocks as well as an MLC memory block including a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell. Triple Level Cell (TLC) memory block comprising a plurality of pages implemented by memory cells capable of storing bit data, multiple implemented by memory cells capable of storing 4-bit data in one memory cell A multi-level cell comprising a quadruple level cell (QLC) memory block containing pages of a plurality of pages implemented by memory cells capable of storing five or more bits of data in one memory cell It may include a cell (multiple level cell) memory block.

Here, in an embodiment of the present disclosure, for convenience of description, the memory device 150 is implemented as a nonvolatile memory such as a flash memory, for example, a NAND flash memory. Phase Change Random Access Memory (RRAM), Resistive Random Access Memory (RRAM), Ferroelectrics Random Access Memory (FRAM), and Spin Injection Magnetic Memory (STT-MRAM): Spin Transfer Torque Magnetic Random Access Memory) may be implemented as any one of memories.

3 is a diagram for describing an example of garbage collection used in a memory system according to an embodiment of the present invention.

Referring to FIG. 3, garbage collection GC may be performed by the memory system itself without a command transmitted from a host. The controller 130 in the memory system reads user data from the plurality of data blocks 40_1 in the memory device 150, stores the user data in the memory 144 disposed in the controller 130, and then frees the data in the memory device 150. User data can be programmed in block 40_2. Here, the plurality of data blocks 40_1 may include blocks for which data can no longer be programmed. In some embodiments, the memory 144 may be disposed outside the controller 130 and interlocked with the controller 130.

In detail, the garbage collection controller 196 included in the controller 130 may select at least one of the plurality of data blocks 40_1 in the memory device 150 as a target block. In addition, the garbage collection control unit 196 searches and extracts valid data in the block selected as the target block, and moves the valid data to the free block 40_2. In this case, data determined to be no longer valid in at least one selected block among the plurality of data blocks 40_1 in the memory device 150 may be discarded (that is, may not be moved to the free block 40_2). ). When valid data stored in the specific block 40_1 in the memory device 150 is moved to the free block 40_2, the controller 130 does not consider the specific block 40_1 to have valid data anymore. Thereafter, when a new data needs to be programmed in a specific block 40_1, all data stored in the block 40_1 may be erased.

According to an embodiment, the controller 130 may use the internal memory 144 to temporarily store valid data selected from garbage collection until it is programmed in the free block 40_2.

For garbage collection, the controller 130 must distinguish between valid and invalid data in the plurality of data blocks 40_1. The information on the valid page count (VPC) corresponding to each data block 40_1 indicates the amount of valid data or valid pages for each data block 40_1 but does not indicate which data or which page is valid. Accordingly, the controller 130 needs to determine which data or which pages are valid using not only the number of valid pages but also operation information including map data. In this case, data to be stored in the free block 40_2 for garbage collection may be easily distinguished, thereby reducing resources (eg, time and power) required for garbage collection.

The plurality of blocks 40_1 and 40_2 in the memory device 150 may store large volume data. According to an embodiment, the controller 130 may divide each block into a plurality of unit blocks in order to more efficiently control and manage the plurality of blocks 40_1 and 40_2 that store a large amount of data. When one block is divided into a plurality of unit blocks, the controller 130 may generate map data (eg, L2P table, P2L table) for each unit block.

According to an embodiment, how many unit blocks are divided into one block may vary. For example, it may be determined to divide one block into several unit blocks based on the structure of the memory device 150, the size of the map data, the location of the map data, and the like. Each block in the memory device 150 may program data in units of a plurality of pages. In this case, the size of data that can be stored in each page may vary according to the structure of the unit cell of each block. When the map data is created in a bitmap format, an area corresponding to one or several times the size unit of the map data may be determined as the size of the unit block.

Data may be sequentially programmed from the first page to the last page in the data block 40_1. When data is programmed in the last page of the block, the block is in a closed state in which new data can no longer be programmed in an open state in which new data can be programmed. According to an embodiment, when a specific block of the data block 40_1 is in a closed state, the garbage collection control unit 196 compares the number of map data corresponding to the data stored in the unit block in the block with the number of valid pages. The validity of the data stored in the block can be determined.

Specifically, when the data block 40_1 in the memory device is in a state in which data can no longer be written without a erase operation (close state), the controller 130 may determine the number of valid pages and the plurality of unit blocks. You can compare the total map data. If the total number of valid pages and map data in a particular block do not match, it may be estimated that unnecessary map data is included in the corresponding block. The controller 130 may check whether map data corresponding to data stored in the block is valid. If there is no longer valid map data, the controller 130 may update the map data by deleting or invalidating the invalid map data.

According to an exemplary embodiment, the garbage collection control unit 196 may determine whether to designate the block as the target block of the garbage collection based on a ratio of the total map data of a plurality of unit blocks in a specific block divided by the number of pages of the corresponding block. The number of pages of the block is a fixed value determined during the design and manufacture of the memory device 150 and may represent the maximum amount of valid data that can be stored in one block. When a particular block is divided into a plurality of unit blocks and map data is generated for each unit block, the sum of the map data of the plurality of unit blocks in the block may indicate an amount of data currently valid for the block. Accordingly, the garbage collection control unit 196 may recognize the amount of valid data in each block based on the ratio of the total map data of the plurality of unit blocks in one block divided by the number of pages of the block. As the above ratio is lower, the garbage collection control unit 196 may first designate the block as a target block of garbage collection. In addition, the garbage collection control unit 196 may determine whether the garbage collection is selected as a target block through whether the aforementioned ratio is within a preset range.

In the above-described embodiment, for garbage collection, the controller 130 must search for valid data in the plurality of data blocks 40_1. In this case, the controller 30 may search for valid data in a limited range of the data block 40_1 instead of searching valid data for all data blocks 40_1 in the memory device 150. In this case, resources (eg, time and power) required to search for data to be stored in the free block 40_2 for garbage collection can be reduced.

The navigation of a valid page relates to garbage collection (GC) operation, and is for managing time of garbage collection through an apparatus and a method for searching for a block to perform garbage collection. Garbage collection involves searching for areas that are no longer available or needing to be used in a dynamically allocated memory area and preparing to program new data by deleting data in that area. The time taken to delete data included in a specific area of the nonvolatile memory device may vary depending on the cell structure or cell characteristics of the nonvolatile memory device. On the other hand, the time required to search for an area to erase in the nonvolatile memory device may vary according to a method and a device for controlling the nonvolatile memory device according to various embodiments.

4 is a diagram illustrating a concept of a super memory block used in a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 4, it can be seen that the components included in the memory device 150 among the components of the memory system 110 according to the exemplary embodiment of the present invention are specifically illustrated.

The memory device 150 may include a plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100, BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110 , BLOCK111, BLOCK112, ..., BLCOK11N).

In addition, the memory device 150 may input / output data through the first memory die DIE0 capable of inputting / outputting data through the zeroth channel CH0 and the first channel CH1. Second memory die DIE1. In this case, the 0th channel CH0 and the first channel CH1 may input / output data in an interleaving manner.

In addition, the first memory die DIE0 may include a plurality of planes PLAE00 respectively corresponding to a plurality of paths WAY0 and WAY1 that may share the 0th channel CH0 and input / output data in an interleaving manner. , PLANE01).

In addition, the second memory die DIE1 may share a plurality of planes PLAN10 respectively corresponding to a plurality of paths WAY2 and WAY3 that may share the first channel CH1 and input / output data in an interleaving manner. , PLANE11).

In addition, the first plane (PLANE00) of the first memory die (DIE0), a plurality of memory blocks (BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100 , BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N, including a predetermined number of memory blocks (BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N).

In addition, the second plane PLANE01 of the first memory die DIE0 includes a plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100. , BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N include a predetermined number of memory blocks BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N.

In addition, the first plane PLANE10 of the second memory die DIE1 may include a plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100. , BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N include a predetermined number of memory blocks (BLOCK100, BLOCK101, BLOCK102, ..., BLCOK10N).

In addition, the second plane PLANE11 of the second memory die DIE1 may include a plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100. , BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N, including a predetermined number of memory blocks BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N.

like this. A plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100, BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N) may be distinguished according to 'physical locations' such as using the same path or the same channel.

For reference, in FIG. 4, two memory dies DIE0 and DIE1 are included in the memory device 150, and two planes PLAN00, PLANE01, PLANE10, and PLANE11 are included in each of the memory dies DIE0 and DIE1. Each plane (PLANE00, PLANE01 / PLANE10, PLANE11) has a predetermined number of memory blocks (BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N / BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N / BLOCK100, BLOCK101, BLOCK102, ..., BLCOK10N / BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N) is illustrated, which is only one embodiment to the last. In practice, depending on the designer's choice, memory device 150 may include more or less than two memory dies, and each memory die may include more or less than two planes. Can be. Of course, the 'scheduled number', which is the number of memory blocks included in each plane, can be adjusted as much as the designer chooses.

Meanwhile, a plurality of memory blocks included in the memory device 150 (BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100, BLOCK101, BLOCK102, ..., The BLCOK10N, BLOCK110, BLOCK111, BLOCK112, ..., BLCOK11N are divided into 'physical locations' such as multiple memory dies (DIE0, DIE1) or multiple planes (PLANE00, PLANE01 / PLANE10, PLANE11). In addition, the controller 130 may use a method of dividing the controller 130 based on the simultaneous selection and operation of a plurality of memory blocks. That is, the controller 130 may group a plurality of memory blocks that have been divided into different dies or different planes at the same time by grouping blocks that can be selected at the same time through a 'physical location' classification method. It can be managed separately. In this case, 'simultaneous selection' may mean 'parallel selection'.

Thus, in the controller 130, a plurality of memory blocks BLOCK000, BLOCK001, BLOCK002, ..., BLCOK00N, BLOCK010, BLOCK011, BLOCK012, ..., BLCOK01N, BLOCK100, BLOCK101, BLOCK102, ..., BLCOK10N, BLOCK110 , BLOCK111, BLOCK112, ..., BLCOK11N) can be divided into super memory blocks and managed according to the designer's choice. Here, three methods will be illustrated.

The first scheme is any one memory in the first plane (PLANE00) of the first memory die (DIE0) of the plurality of memory dies (DIE0, DIE1) included in the memory device 150 in the controller 130 In the block BLOCK000 and the second plane PLAE01, any one memory block BLOCK010 is grouped and managed as one super memory block A1. When the first scheme is applied to the second memory die DIE1 of the plurality of memory dies DIE0 and DIE1 included in the memory device 150, the controller 130 may determine the first of the second memory die DIE1. Any one memory block BLOCK100 in the plane PLAE10 and one memory block BLOCK110 in the second plane PLAE11 may be grouped and managed as one super memory block A2. .

The second scheme is any one included in the first plane PLAE00 of the first memory die DIE0 of the plurality of memory dies DIE0 and DIE1 included in the memory device 150 in the controller 130. A memory block BLOCK002 and an arbitrary memory block BLOCK102 included in the first plane PLANE10 of the second memory die DIE1 are grouped and managed as one super memory block B1. to be. Reapplying the second scheme, the controller 130 is included in the second plane PLANE01 of the first memory die DIE0 of the plurality of memory dies DIE0 and DIE1 included in the memory device 150. One memory block BLOCK012 and one memory block BLOCK112 included in the second plane PLANE11 of the second memory die DIE1 to group one super memory block B2. Can be managed by

The third scheme is any one included in the first plane PLAN00 of the first memory die DIE0 of the plurality of memory dies DIE0 and DIE1 included in the memory device 150 in the controller 130. Memory block (BLOCK001), any one memory block (BLOCK011) included in the second plane (PLANE01) of the first memory die (DIE0), and the first plane of the second memory die (DIE1) One super memory by grouping any one memory block BLOCK101 included in PLANE10 and any one memory block BLOCK111 included in the second plane PLANE11 of the second memory die DIE1. It is managed by block (C).

For reference, simultaneously selectable memory blocks included in a super memory block may be interleaved, for example, channel interleaving, memory die interleaving, memory chip interleaving, or path. The interleaving may be selected substantially at the same time.

<First Embodiment>

5A and 5B illustrate garbage collection for a super memory block in a memory system according to a first embodiment of the present invention.

First, in the first embodiment of the present invention illustrated in FIGS. 5A and 5B, it can be seen that the controller 130 described above with reference to FIG. 4 uses a third method of dividing the super memory blocks.

That is, in FIGS. 5A and 5B, the controller 130 selects one random memory block from each of the four planes PLANE <00, 01, 10, and 11> included in the memory device 150. To a super memory block (SUPER BLOCK <0> or SUPER BLOCK <1>). Therefore, one super memory block SUPER BLOCK <0> or SUPER BLOCK <1> includes four memory blocks.

For example, referring to FIGS. 4 and 5A, the first super memory block SUPER BLOCK <0> may include the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0. The first memory block (BLOCK010) of the second plane (PLANE01) of the first memory die (DIE0), the first memory block (BLOCK100) of the first plane (PLANE10) of the second memory die (DIE1), and The first memory block BLOCK110 of the second plane PLANE11 of the second memory die DIE1 is grouped.

4 and 5B, the second super memory block SUPER BLOCK <1> includes a second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0; The second memory block (BLOCK011) of the second plane (PLANE01) of the first memory die (DIE0), the second memory block (BLOCK101) of the first plane (PLANE10) of the second memory die (DIE1), and The second memory block BLOCK111 of the second plane PLANE11 of the second memory die DIE1 is grouped.

Each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 5A and 5B includes four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. 001, 011, 101, 111>) can be selected in parallel to input / output data in units of pages.

Here, each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 5A and 5B includes four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. 001, 011, 101, 111>) in parallel, it can be assumed that parallel reading is possible only for pages of the same position.

For example, selecting four memory blocks BLOCK <000, 010, 100, 110> included therein in parallel in the first super memory block SUPER BLOCK <0> illustrated in FIG. This means selecting pages having the same location in each of the four memory blocks BLOCK <000, 010, 100, and 110>. That is, in the first super memory block SUPER BLOCK <0> illustrated in FIG. 5A, the first page P <of each of the four memory blocks BLOCK <000, 010, 100, 110> included therein. 0>) at the same time or to select each second page (P <1>) at the same time. This is because the first and second memory blocks among the four memory blocks BLOCK <000, 010, 100, and 110> included therein in the first super memory block SUPER BLOCK <0> illustrated in FIG. 5A. The first page (P <0>) is selected in (BLOCK <000, 010>) and the second page (P <1>) is selected in the third and fourth memory blocks (BLOCK <100, 110>). This means that it is not possible to select pages from different locations at the same time.

Likewise, in the second super memory block SUPER BLOCK <1> illustrated in FIG. 5B, selecting four memory blocks BLOCK <001, 011, 101, and 111> included therein in parallel is 4 This means selecting the same page at the same time in each of the memory blocks BLOCK <001, 011, 101, and 111>. That is, in the second super memory block SUPER BLOCK <1> illustrated through FIG. 5B, the third page P <of each of the four memory blocks BLOCK <001, 011, 101, and 111> included therein. 2>) or simultaneously select each fourth page (P <3>). This is because the first and second memory blocks of the four memory blocks BLOCK <001, 011, 101, and 111> included therein in the second super memory block SUPER BLOCK <1> illustrated in FIG. 5B. The third page (P <2>) is selected at (BLOCK <001, 011>) and the fourth page (P <3>) is selected at the third and fourth memory blocks (BLOCK <101, 111>). This means that it is not possible to select pages from different locations at the same time.

Meanwhile, each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 5A and 5B has four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. Each of the plurality of pages (P <0, 1, 2, ...>) included in each of 001, 011, 101, and 111> independently has a valid page (VAILD PAGE) or an invalid page (INVALID PAGE). Can be.

For example, as illustrated in FIG. 5A, the first super memory block SUPER BLOCK <0> may include the first page P <0> of each of the first to third memory blocks BLOCK <000, 010, 100>. ) May be a valid page (VAILD PAGE), all other pages may be an INVALID PAGE.

In addition, as illustrated in FIG. 5B, the second super memory block SUPER BLOCK <1> may include a first page P <0> of the first memory block BLOCK001 and a second memory block BLOCK011. Only the third page (P <2>) and the second page (P <1>) of the fourth memory block (BLOCK111) are valid pages (VAILD PAGE), and all remaining pages may be invalid pages (INVALID PAGE). .

As such, the first super memory block SUPER BLOCK <0> illustrated in FIG. 5A and the second super memory block SUPER BLOCK <1> illustrated in FIG. 5B each include three valid pages. Able to know.

In addition, four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) included in each of the super memory blocks SUPER BLOCK <0,1> illustrated through FIGS. 5A and 5B for garbage collection. , MEMORY BLOCK <001, 011, 101, and 111> may be selected as victim blocks.

As such, when the first super memory block SUPER BLOCK <0> illustrated in FIG. 5A is selected as a victim block for garbage collection, four memory blocks included in the memory block (MEMORY BLOCK <000, 010, 100, The time required to extract data from the three valid pages included in 110>) may be referred to as the first time required TOTAL <0>. In addition, when the second super memory block (SUPER BLOCK <1>) illustrated in FIG. 5B is selected as a victim block for garbage collection, four memory blocks (MEMORY BLOCK <001, 011, 101, The time required to extract data from the three valid pages included in 111>) may be referred to as a second time duration TOTAL <1>.

At this time, the first time required TOTAL <0> and the second time required TOTAL <1> may be significantly different due to the following reasons.

Specifically, four garbage blocks (MEMORY BLOCK <000, 010, 100, 110>) included therein are selected by selecting the first super memory block (SUPER BLOCK <0>) illustrated in FIG. 5A as a victim block in the garbage collection. In order to extract data from the three valid pages included in), the positions of the three valid pages can be checked.

As a result, the first super memory block (SUPER BLOCK <0>), only the first page (P <0>) of each of the first to third memory blocks (BLOCK <000, 010, 100>) are valid pages (VAILD). PAGE), and all remaining pages are invalid pages (INVALID PAGE).

According to the result of the check, it can be seen that the three valid pages VAILD PAGE included in the first super memory block SUPER BLOCK <0> are identical to each other. That is, it can be seen that one read P <0> _READ should be performed to extract three valid data from three valid pages.

Accordingly, the controller 130 may include the first of each of the four memory blocks BLOCK <000, 010, 100, and 110> included in the first super memory block SUPER BLOCK <0> at the zeroth time point t0. Perform one read (P <0> _READ) for page P <0>. Four page data B000P0_VD, B010P0_VD, B100P0_VD, and B110P0_IVD are cached in four page buffers PB <000, 010, 100, and 110 through one read P <0> _READ. Subsequently, the controller 130 may include three of the four page data B000P0_VD, B010P0_VD, B100P0_VD, and B110P0_IVD that are cached in the page buffers PB <000, 010, 100, and 110> at the first time point t1. Only valid data (VALID DATA: B000P0_VD, B010P0_VD, B100P0_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include one of four page data B000P0_VD, B010P0_VD, B100P0_VD, and B110P0_IVD that are cached in the page buffers PB <000, 010, 100, and 110> at the zeroth time point t0. The invalid data INVALID DATA B110P0_IVD is discarded without being transferred to the internal memory 144 at the first time point t1.

Thus, the controller 130, through one read (P <0> _READ), three valid pages (VAILD PAGE: BLOCK000_P <0>, BLOCK010_P included in the first super memory block SUPER BLOCK <0>). All three valid data (VALID DATA: B000P0_VD, B010P0_VD, and B100P0_VD) stored in <0>, BLOCK110_P <0>) can be extracted.

Here, the time required to perform one read P <0> _READ may be assumed to be a read time tREAD. Also, the time required to transfer one page data (B000P0_VD or B010P0_VD or B100P0_VD) stored in one page buffer (PB <000> or PB <010> or PB <100>) to the internal memory 144 is transmitted. (tTX) can be assumed. Assuming this, the first time required for extracting data by selecting the first super memory block (SUPER BLOCK <0>) as the victim block in garbage collection is '{read time (tREAD)'. * 1} + {transmission time (tTX) * 3} '. For example, assuming that the read time tREAD is 50us and the transfer time tTX is 10us, it is necessary to select the first super memory block SUPER BLOCK <0> as the victim block in the garbage collection and extract the data. The first time duration (TOTAL <0>) will be 80us.

In the garbage collection, the second super memory block SUPER BLOCK <1> illustrated in FIG. 5B is selected as a victim block and four memory blocks included therein (MEMORY BLOCK <001, 011, 101, 111>). In order to extract the data from the three valid pages included in the location of the three valid pages can be identified.

As a result, the second super memory block (SUPER BLOCK <1>) includes the first page (P <0>) of the first memory block (BLOCK001) and the third page (P <) of the second memory block (BLOCK011). 2>), and only the second page P <1> of the fourth memory block BLOCK111 is a valid page (VAILD PAGE), and all remaining pages are invalid pages (INVALID PAGE).

According to the check result, it can be seen that the three valid pages VAILD PAGE included in the second super memory block SUPER BLOCK <1> are not identical to each other. That is, it can be seen that three reads P <0> _READ, P <1> _READ, and P <2> _READ should be performed to extract three valid data from three valid pages.

Accordingly, the controller 130 may include the first of each of the four memory blocks BLOCK <001, 011, 101, and 111> included in the second super memory block SUPER BLOCK <1> at the zeroth time point t0. Perform the first read (P <0> _READ) for page P <0>. Four page data B001P0_VD, B011P0_IVD, B101P0_IVD, and B111P0_IVD are cached in four page buffers PB <001, 011, 101, and 111 through the first read P <0> _READ. Subsequently, the controller 130 includes one of four page data B001P0_VD, B011P0_IVD, B101P0_IVD, and B111P0_IVD cached in the page buffers PB <001, 011, 101, and 111> at the first time point t1. Only valid data (VALID DATA: B001P0_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include three invalid data INVALID DATA: B011P0_IVD among the four page data B001P0_VD, B011P0_IVD, B101P0_IVD, and B111P0_IVD cached in the page buffers PB <001, 011, 101, and 111>. , B101P0_IVD and B111P0_IVD are discarded without being transferred to the internal memory 144.

Thus, the controller 130, through the first read (P <0> _READ), to one valid page (VAILD PAGE: BLOCK001_P <0>) included in the second super memory block (SUPER BLOCK <1>). One stored valid data (VALID DATA: B001P0_VD) can be extracted.

Subsequently, the controller 130 performs a second operation on each of the four memory blocks BLOCK <001, 011, 101, and 111> included in the second super memory block SUPER BLOCK <1> at the second time point t2. Perform a second read (P <1> _READ) for page P <1>. Four page data B001P1_IVD, B011P1_IVD, B101P1_IVD, and B111P1_VD are cached in four page buffers PB <001, 011, 101, and 111 through the second read P <1> _READ. Subsequently, the controller 130 includes one of four page data B001P1_IVD, B011P1_IVD, B101P1_IVD, and B111P1_VD cached in the page buffers PB <001, 011, 101, and 111> at the third time point t3. Only valid data (VALID DATA: B111P1_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include three invalid data INVALID DATA: B001P1_IVD among the four page data B001P1_IVD, B011P1_IVD, B101P1_IVD, and B111P1_VD cached in the page buffers PB <001, 011, 101, and 111>. , B011P1_IVD and B101P1_IVD are discarded without being transferred to the internal memory 144.

Thus, the controller 130, through the second read (P <1> _READ), to one valid page (VAILD PAGE: BLOCK111_P <1>) included in the second super memory block (SUPER BLOCK <1>). One stored valid data (VALID DATA: B111P1_VD) can be extracted.

Subsequently, the controller 130 performs a third operation on each of the four memory blocks BLOCK <001, 011, 101, and 111> included in the second super memory block SUPER BLOCK <1> at the fourth time point t4. Perform a third read (P <2> _READ) for page P <2>. Four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD are cached in four page buffers PB <001, 011, 101, and 111 through the third read P <2> _READ. Subsequently, the controller 130 includes one of four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD cached in the page buffers PB <001, 011, 101, and 111> at the fifth time point t5. Only valid data (VALID DATA: B011P2_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include three invalid data INVALID DATA: B001P2_IVD among the four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD cached in the page buffers PB <001, 011, 101, and 111>. , B101P2_IVD and B111P2_IVD are discarded without being transferred to the internal memory 144.

In this way, the controller 130, through the third read P <2> _READ, writes to one valid page VAILD PAGE: BLOCK011_P <2> included in the second super memory block SUPER BLOCK <1>. One stored valid data (VALID DATA: B011P2_VD) can be extracted.

In summary, the controller 130 stores 3 valid pages (VAILD PAGE: BLOCK001_P <0>, BLOCK011_P <2>, and BLOCK111_P <1>) included in the second super memory block (SUPER BLOCK <1>). It can be seen that three reads P <0> _READ, P <1> _READ, and P <2> _READ are required to extract all valid data (VALID DATA: B001P0_VD, B011P2_VD, and B111P1_VD).

Here, the time required to perform one read P <0> _READ or P <1> _READ or P <2> _READ may be assumed to be a read time tREAD. In addition, a time required for transferring one page data (B001P0_VD or B011P2_VD or B111P1_VD) stored in one page buffer (PB <001> or PB <011> or PB <111>) to the internal memory 144 is transmitted. (tTX) can be assumed. In this case, the time required for extracting data by selecting the second super memory block (SUPER BLOCK <1>) as the victim block in the garbage collection is '{lead time (tREAD) * 3'. } + {Transmission time (tTX) * 3} '. For example, assuming that the read time tREAD is 50us and the transfer time tTX is 10us, the second super memory block SUPER BLOCK <1> is selected as a victim block in the garbage collection to extract data. The second time duration (TOTAL <1>) will be 180us.

In summary, the first super memory block SUPER BLOCK <0> as illustrated in FIG. 5A and the second super memory block SUPER BLOCK <1> as illustrated in FIG. 5B each include three valid pages. In this case, when the victim block for garbage collection is selected based on the number of valid pages, it can be seen that the same condition exists.

However, when each of the super memory blocks SUPER BLOCK <0, 1> illustrated through FIGS. 5A and 5B is selected as a victim block for garbage collection, the first super memory block SUPER BLOCK illustrated in FIG. 5A is selected. The first time required to extract data from <0>) (TOTAL <0>) is 80us, while the second time required to extract data from the second super memory block (SUPER BLOCK <1>) illustrated in FIG. 5B. The time required (TOTAL <1>) is 180us, which is more than doubled.

That is, the controller 130 may perform the first super memory block SUPER BLOCK <0> of the super memory blocks SUPER BLOCK <0, 1> illustrated through FIGS. 5A and 5B in order to effectively perform garbage collection. It is preferable to select as the sacrificial block.

FIG. 6 is a diagram illustrating an operation of selecting a victim block when garbage collection is performed on a super memory block in a memory system according to the first embodiment of the present invention described with reference to FIGS. 5A and 5B. .

Referring to FIG. 6, the memory system 110 according to the first embodiment of the present invention includes a controller 130 and a memory device 150.

The controller 130 may include a garbage collection control unit 196 and a memory 144. Here, since the general operation of the garbage collection control unit 196 has been described with reference to FIG. 3, it will not be described in detail here.

As described with reference to FIG. 4, the memory device 150 includes a plurality of memory blocks MEMORY BLOCK <000, 001, ...>. In addition, the controller 130 may group N memory blocks capable of parallel reading among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 by grouping a plurality of memory blocks according to a set condition. Managed as super memory blocks (SUPER BLOCK <0: N>). At this time, N is a natural number of 2 or more, and it is assumed that N is 4 in FIGS. 5A and 5B. Here, one super memory block SUPER BLOCK <2> in a free state together with the two super memory blocks SUPER BLOCK <0, 1> described with reference to FIGS. 5A and 5B is stored in the memory device ( Assume that it is included in 150). Of course, the matters illustrated in FIG. 6 are merely simplified for the sake of convenience of explanation, and in practice, may be extended to any other form (such as a larger number of super memory blocks are included in the memory device).

In detail, the controller 130 may include the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 for garbage collection through the garbage collection control unit 196 included therein. Predictions (PRE_TOTAL <0, 1>), which calculates the required time when extracting valid data in superblock units, are generated, and the required prediction times (PRE_TOTAL <0, 1>) are generated. It manages as time table 600. FIG.

In addition, the controller 130 controls the number of valid pages VPC <0 of each of the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 through the garbage collection control unit 196. : 1> is counted in superblock units, and the counted valid page counts VPC <0: 1> are managed as the valid page count table 610.

More specifically, the controller 130 may include the plurality of super memory blocks SUPER BLOCK in the valid page count VPC <0: 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>. <0: 1>) The number of valid pages having the same position among the four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <001, 011, 101, 111> grouped in each (DP_CNT <). Calculate the first time (FIRST_TIME <0: 1>) by multiplying the lead prediction time (PRE_tREAD) by subtracting 0: 1>) (FIRST_TIME <0: 1> = (VPC <0: 1>-DP_CNT <0: 1>) * PRE_tREAD).

Also, the controller 130 may multiply the number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPERBLOCK <0: 1> by the transmission prediction time PRE_tTX, and the second time SECOND_TIME. <0: 1>) (SECOND_TIME <0: 1> = VPC <0: 1> * PRE_tTX).

In addition, the controller 130 calculates a value obtained by adding the first time FIRST_TIME <0: 1> and the second time SECOND_TIME <0: 1> (TOTAL <0: 1> = FIRST_TIME <0: 1>). + SECOND_TIME <0: 1>) to generate required prediction times PRE_TOTAL <0, 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>.

For example, referring to FIG. 5 together with FIG. 6 to illustrate, the first super memory block SUPER BLOCK <0> may include the first to third memory blocks BLOCK <000, 010, 100>, respectively. It can be seen that only the first page P <0> is a valid page (VAILD PAGE), and all remaining pages are invalid pages (INVALID PAGE).

Accordingly, the controller 130 may know that the first valid page number VPC <0> included in the first super memory block SUPER BLOCK <0> is three.

In addition, the controller 130 may include all three valid pages included in the first super memory block SUPER BLOCK <0> as the first page P <0>. It can be seen that <0>) is 2. Here, based on the first valid page (BLOCK000 / P <0>), the second and third valid pages (BLOCK010 / P <0>, BLOCK100 / P <0>) are the first valid page (BLOCK000 / P <0>). Same position as P <0>). Therefore, valid pages with the same position in the first super memory block (SUPER BLOCK <0>) include the second and third valid pages (BLOCK010 / P <0>, BLOCK100 / P <0>). The number of first valid pages DP_CNT <0> is two.

Therefore, the first first time FIRST_TIME <0> corresponding to the first super memory block SUPER BLOCK <0> is one read prediction time through a calculation such as '(3 ?? 2) * PRE_tREAD'. It is a time corresponding to (PRE_tREAD). Also, the first second time SECOND_TIME <0> corresponding to the first super memory block SUPER BLOCK <0> corresponds to three transmission prediction times PRE_tTX through the same calculation as '3 * PRE_tTX'. It's time to do it. In conclusion, the first required prediction time PRE_TOTAL <0> corresponding to the first super memory block SUPER BLOCK <0> is the first first time FIRST_TIME <corresponding to one read prediction time PRE_tREAD. 0>) and the first second time (SECOND_TIME <0>) corresponding to three transmission prediction times PRE_tTX.

For example, assuming that the lead prediction time PRE_tREAD is 50us and the transmission prediction time PRE_tTX is 10us, the first required prediction time PRE_TOTAL <0 corresponding to the first super memory block SUPER BLOCK <0> is assumed. >) Will be 80us plus 50us first first time (FIRST_TIME <0>) plus 30us first second time (SECOND_TIME <0>).

Likewise, referring to FIG. 5 together with FIG. 6 for an example, the second super memory block SUPER BLOCK <1> is the first page P <0> of the first memory block BLOCK001. Only the third page (P <2>) of the second memory block (BLOCK011) and the second page (P <1>) of the fourth memory block (BLOCK111) are valid pages (VAILD PAGE), and all remaining pages. It can be seen that they are invalid pages.

Accordingly, the controller 130 may know that the second valid page number VPC <1> included in the second super memory block SUPER BLOCK <1> is three.

In addition, the controller 130 may have different positions of each of the three valid pages included in the second super memory block SUPER BLOCK <1>, and the number of second valid pages having the same position may be the same (DP_CNT <1>). It can be seen that is 0. Here, based on the first valid page (BLOCK001 / P <0>), the second valid page (BLOCK011 / P <3>) and the third valid page (BLOCK111 / P <0>) are the first valid page, respectively. This is a different location than the page (BLOCK000 / P <0>). Also, the second valid page BLOCK011 / P <3> and the third valid page BLOCK111 / P <0> are also different positions. Therefore, there is no valid page having the same position in the second super memory block SUPER BLOCK <1>, whereby the second valid page number DP_CNT <1> becomes zero.

Therefore, the second first time FIRST_TIME <1> corresponding to the second super memory block SUPER BLOCK <1> is three read prediction times through a calculation such as '(3 ?? 0) * PRE_tREAD'. It is a time corresponding to (PRE_tREAD). In addition, the second second time SECOND_TIME <1> corresponding to the second super memory block SUPER BLOCK <1> corresponds to three transmission prediction times PRE_tTX through the same calculation as '3 * PRE_tTX'. It's time to do it. In conclusion, the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> is the second first time FIRST_TIME <corresponding to three read prediction times PRE_tREAD. 1>) and the second second time SECOND_TIME <1> corresponding to the three transmission prediction times PRE_tTX.

For example, assuming that the lead prediction time PRE_tREAD is 50us and the transmission prediction time is 10us, the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> is , The second first time (FIRST_TIME <1>) of 150us and the second second time (SECOND_TIME <1>) of 30us will be 180us.

For reference, the controller 130 may set information about the read prediction time PRE_tREAD and the transfer prediction time PRE_tTX for the memory device 150. That is, the designer may preset the read prediction time PRE_tREAD and the transfer prediction time PRE_tTX for the memory device 150 through a test according to the type or state of the memory device 150.

As described above, the controller 130 predicts the required prediction time PRE_TOTAL <0, 1> for each of the plurality of super memory blocks SUPER BLOCK <0: 1> before performing garbage collection. can do.

In addition, the controller 130 may estimate the required number of the super memory blocks SUPER BLOCK <0: 1> included in the required forecast time table 600 through the branch ratio collection control unit 196 included therein. Selecting a memory block among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 as a victim block for garbage collection by referring to the times PRE_TOTAL <0, 1>. You can decide if you want to.

At this time, the controller 130 refers to the required prediction times PRE_TOTAL <0, 1> for the plurality of super memory blocks SUPER BLOCK <0: 1> included in the required prediction time table 600. There may be two methods, and either method may be selected.

The first method is based on the predicted time of the relatively smallest required time among the predicted times PRE_TOTAL <0, 1> for the plurality of super memory blocks SUPER BLOCK <0: 1> in the controller 130. The memory block including at least one valid page among the N memory blocks grouped in the corresponding super memory block is selected as a victim block.

For example, as described in the foregoing description, the required prediction time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> is 80us, and the requirement for the second super memory block SUPER BLOCK <1>. Since the prediction time PRE_TOTAL <1> is 180us, the required prediction time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> is smaller. Accordingly, the controller 130 includes at least one valid page among four memory blocks MEMORY BLOCK <000, 010, 100, 110> grouped in the first super memory block SUPER BLOCK <0>. Three memory blocks MEMORY BLOCK <000, 010, 100> are selected as victim blocks.

Thus, since three memory blocks (MEMORY BLOCK <000, 010, 100>) included in the first super memory block (SUPER BLOCK <0>) are selected as victim blocks, the first in the section where garbage collection is performed The three valid pages included in the super memory block SUPER BLOCK <0> are transferred to the memory 144 inside the controller 130, and then a third super memory block SUPER BLOCK <2 that is a target block. >) Will be stored.

In the second method, before using the first method described above, the controller 130 checks the number of valid pages of each of the N memory blocks included in each of the plurality of super memory blocks SUPER BLOCK <0: 1>. This is a method of checking the number of super memory blocks whose combined number VPC <0: 1> is equal to or less than the set number. That is, the controller 130 may have one super memory block that is less than or equal to the set number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>. , Do not use the first scheme described above. On the other hand, the controller 130 may have at least two super memory blocks that are less than or equal to the set number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>. Above ', the first method described above is used.

For example, unlike the above description, the number of valid pages VPC <0> of the first super memory block SUPER BLOCK <0> is 5 and the number of valid pages of the second super memory block SUPER BLOCK <1>. (VPC <1>) may be one. In addition, the controller 130 may set the 'set number' to two. In this case, the controller 130 may confirm that one super memory block, that is, the second super memory block SUPER BLOCK <1> has a valid number of pages less than or equal to the 'set number'. Accordingly, the controller 130 does not use the first method described above, but among the N memory blocks included in the second super memory block SUPER BLOCK <1> having a valid number of pages less than or equal to the 'set number'. A memory block including at least one valid page is selected as a victim block.

On the other hand, as in the above description, the number of valid pages VPC <0> of the first super memory block SUPER BLOCK <0> is 3 and the number of valid pages of the second super memory block SUPER BLOCK <1>. (VPC <1>) may also be three. In addition, the controller 130 may set the 'set number' to two. In this case, the controller 130 may determine that two super memory blocks, that is, the first super memory block SUPER BLOCK <0> and the second super memory block SUPER BLOCK <1> are both less than or equal to the 'set number'. It can be confirmed that it has a valid page number of. Accordingly, the controller 130 uses the first method described above to make N memories included in the first super memory block SUPER BLOCK <0> having a relatively smaller required prediction time PRE_TOTAL <0>. A memory block including at least one valid page among the blocks is selected as the victim block.

On the other hand, as described above, the controller 130 generates the required prediction times PRE_TOTAL <0, 1> and generates the required prediction times PRE_TOTAL <0, 1>. I manage it as).

In this case, the controller 130 may update the required prediction times PRE_TOTAL <0, 1> by using any one of the following two methods.

In the first method, the controller 130 may generate a specific memory block in which the number of valid pages is variable among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150. The required prediction time of the super memory block in which a specific memory block is grouped may be updated.

For example, referring to FIG. 4 and FIG. 5A, according to the first foreground operation or the background operation, the number of valid pages of the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0 may be calculated. Can be variable. Subsequently, the number of valid pages of the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0 may vary according to the execution of the second foreground operation or the background operation.

In this case, the controller 130 may respond to the change of the valid page of the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0, thereby causing the corresponding memory block BLOCK000 to be changed. The value of the first required prediction time PRE_TOTAL <0> corresponding to the grouped first super memory block SUPER BLOCK <0> may be predicted again. Subsequently, the controller 130 may group the corresponding memory block BLOCK001 in response to a change in the number of valid pages of the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0. The value of the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> may be predicted again.

In the second method, the controller 130 checks whether there is a specific memory block having a variable number of valid pages among the memory blocks MEMORY BLOCK <000, 001, ...> for each 'set time point'. As a result, when there is a specific memory block having a variable number of valid pages, the required prediction time of the super memory block in which the specific memory block is grouped may be updated.

For example, referring to FIGS. 4 and 5A, at least two foreground operations or background operations consecutive between a first set time point (not shown) and a second set time point (not shown) are performed to perform a first memory die ( The number of valid pages of the first memory block BLOCK000 of the first plane PLANE00 of DIE0 and the number of valid pages of the second memory block BLOCK001 may vary.

In this case, the controller 130 checks whether or not a memory block having a variable number of valid pages among the memory blocks MEMORY BLOCK <000, 001, ...> exists at the second set time point, and confirms that there is. As a result, it can be seen that the number of valid pages of each of the first memory block BLOCK000 and the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0 varies. Accordingly, the controller 130 may include the first super memory block SUPER BLOCK <0> in which the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0 is grouped at the second set time point. Second super memory block (BLOCK001) grouped with the value of the first expected time (PRE_TOTAL <0>) and the second memory block (BLOCK001) of the first plane (PLANE00) of the first memory die (DIE0). The value of the second required prediction time PRE_TOTAL <1> corresponding to SUPER BLOCK <1>) may be simultaneously predicted again.

For reference, the 'set time' may be predefined by the designer, and may be a time point that is repeated each time data of a set size is written or a time point that is repeated every time the execution of a specific operation is completed.

Meanwhile, garbage collection is performed so that all valid pages included in the first super memory block SUPER BLOCK <0> selected as the victim block are transferred to the memory 144 in the controller 130 and then the target block. If it is moved to the third super memory block (SUPER BLOCK <2>), the first super memory block (SUPER BLOCK <0>) will no longer have a valid page. Therefore, the first super memory block (SUPER BLOCK <0>) after garbage collection is an invalid super memory block in addition to the free super memory block through an erase operation. Need not be. However, since the controller 130 generates the first required time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> before performing garbage collection, the controller 130 performs garbage collection. Thereafter, the value may remain in the required prediction time table 600. As such, an unknown abnormal operation may be performed on the first super memory block SUPER BLOCK <0> due to the value of the first predicted time PRE_TOTAL <0> remaining in the required time table 600. have. Therefore, after garbage collection is performed on the first super memory block SUPER BLOCK <0> selected as the victim block, the controller 130 corresponds to the first corresponding to the first super memory block SUPER BLOCK <0>. By setting the first expected time PRE_TOTAL <0> to 'scheduled value', an unknown abnormal operation on the first super memory block SUPER BLOCK <0> is prevented from being performed.

In summary, when a specific super memory block is selected as a victim block and all valid pages inside the target super memory block are moved through garbage collection, the controller 130 performs an unknown wrong operation. The estimated time required for a specific super memory block can be set to 'scheduled value'.

Meanwhile, if the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 is sufficiently large, the probability of garbage collection is not high. That is, in general, garbage collection is an operation performed when the number of free memory blocks included in the memory device 150 decreases below a predetermined number.

Accordingly, in the controller 130 according to the first embodiment of the present invention, the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001,... The above-described required prediction times PRE_TOTAL <0, 1> are generated and managed in a section of 1 number 'or less. Of course, the controller 130 may include a 'second number' in which the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 is greater than the 'first number'. 'It does not generate and manage required forecasting times PRE_TOTAL <0, 1> in the section above.

For reference, the first number may be set differently from the predetermined number for determining a trigger time of a general garbage collection operation. For example, the 'constant number' may be smaller than the 'first number'.

Second Embodiment

7A and 7B illustrate garbage collection for a super memory block in a memory system according to a second embodiment of the present invention.

First, in the second embodiment of the present invention illustrated in FIGS. 7A and 7B, it can be seen that the controller 130 described above with reference to FIG. 4 uses a third method of dividing the super memory blocks.

That is, in FIGS. 7A and 7B, the controller 130 selects one random memory block from each of the four planes PLANE <00, 01, 10, and 11> included in the memory device 150. To a super memory block (SUPER BLOCK <0> or SUPER BLOCK <1>). Therefore, one super memory block SUPER BLOCK <0> or SUPER BLOCK <1> includes four memory blocks.

For example, referring to FIGS. 4 and 7A, the first super memory block SUPER BLOCK <0> may include the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0. The first memory block (BLOCK010) of the second plane (PLANE01) of the first memory die (DIE0), the first memory block (BLOCK100) of the first plane (PLANE10) of the second memory die (DIE1), and The first memory block BLOCK110 of the second plane PLANE11 of the second memory die DIE1 is grouped.

4 and 7B, the second super memory block SUPER BLOCK <1> includes a second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0; The second memory block (BLOCK011) of the second plane (PLANE01) of the first memory die (DIE0), the second memory block (BLOCK101) of the first plane (PLANE10) of the second memory die (DIE1), and The second memory block BLOCK111 of the second plane PLANE11 of the second memory die DIE1 is grouped.

Each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 7A and 7B has four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. 001, 011, 101, 111>) can be selected in parallel to input / output data in units of pages.

Here, each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 7A and 7B has four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. 001, 011, 101, 111>) in parallel, it can be assumed that parallel reads are possible for pages of different positions. Of course, even if parallel reading is possible for pages of different positions, it is possible to select and read only one page at a time in one block.

For example, selecting four memory blocks BLOCK <000, 010, 100, 110> included therein in parallel in the first super memory block SUPER BLOCK <0> illustrated in FIG. This means that one page is selected regardless of the position in each of the memory blocks BLOCK <000, 010, 100, and 110>. That is, the first memory block BLOCK000 of the four memory blocks BLOCK <000, 010, 100, and 110> included therein in the first super memory block SUPER BLOCK <0> illustrated in FIG. 7A. Selects the first page (P <0>), selects the third page (P <2>) in the second memory block (BLOCK010), and selects the third and fourth memory blocks (BLOCK <100, 110>). Respectively means selecting the second page (P <1>). Of course, the first and second memory blocks BLOCK <000, 010> of the four memory blocks BLOCK <000, 010, 100, 110> select two pages, respectively, and the third and fourth memories. In the blocks BLOCK <100, 110>, reading in the same manner as selecting no page is impossible.

Similarly, in the second super memory block SUPER BLOCK <1> illustrated in FIG. 7B, selecting four memory blocks BLOCK <001, 011, 101, 111> included therein in parallel is 4 This means that one page is simultaneously selected regardless of the position in each of the memory blocks BLOCK <001, 011, 101, and 111>. That is, the first memory block BLOCK001 of the four memory blocks BLOCK <001, 011, 101, and 111> included therein in the second super memory block SUPER BLOCK <1> illustrated in FIG. 7B. In this case, the first page P <0> is selected, and in the second to fourth memory blocks BLOCK <011, 101, and 111>, the second page P <1> is selected. Of course, the second and third memory blocks BLOCK <011 and 101> of the four memory blocks BLOCK <001, 011, 101, and 111> respectively select two pages, and the first and fourth memories are selected. In the blocks BLOCK <001, 111>, reading in the same manner as selecting no page is impossible.

Meanwhile, each of the super memory blocks SUPER BLOCK <0, 1> illustrated in FIGS. 7A and 7B has four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <included therein. Each of the plurality of pages (P <0, 1, 2, ...>) included in each of 001, 011, 101, and 111> independently has a valid page (VAILD PAGE) or an invalid page (INVALID PAGE). Can be.

For example, as illustrated in FIG. 7A, the first super memory block SUPER BLOCK <0> may include the first page P <0> of the first memory block BLOCK000 and the second memory block BLOCK010. Only the third page (P <2>) and the second page (P <1>) of each of the third and fourth memory blocks (BLOCK <100, 110>) are valid pages (VAILD PAGE), and all remaining pages It may be an invalid page.

In addition, as illustrated in FIG. 7B, the second super memory block SUPER BLOCK <1> may include the first page P <0> of the first memory block BLOCK001 and the second memory block BLOCK011. Only the second and third pages (P <1, 2>) and the second page (P <1>) of the fourth memory block (BLOCK111) are valid pages (VAILD PAGE), and all remaining pages are invalid pages (INVALID). PAGE).

As such, the first super memory block SUPER BLOCK <0> illustrated in FIG. 7A and the second super memory block SUPER BLOCK <1> illustrated in FIG. 7B may each include four valid pages. Able to know.

In addition, four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) included in each of the super memory blocks SUPER BLOCK <0, 1> illustrated through FIGS. 7A and 7B for garbage collection. , MEMORY BLOCK <001, 011, 101, and 111> may be selected as victim blocks.

As such, when the first super memory block SUPER BLOCK <0> illustrated in FIG. 7A is selected as the victim block for garbage collection, four memory blocks included in the memory block (MEMORY BLOCK <000, 010, 100, The time required to extract data from four valid pages included in 110>) may be referred to as the first time TOTAL <0>. In addition, when the second super memory block (SUPER BLOCK <1>) illustrated in FIG. 7B is selected as a victim block for garbage collection, four memory blocks (MEMORY BLOCK <001, 011, 101, The time required to extract data from the four valid pages included in 111>) may be referred to as the second time required TOTAL <1>.

At this time, the first time required TOTAL <0> and the second time required TOTAL <1> may be significantly different due to the following reasons.

Specifically, four garbage blocks included in the garbage collection are selected by selecting the first super memory block SUPER BLOCK <0> illustrated in FIG. 7A as a victim block in the garbage collection. In order to extract data from the four valid pages included in), the positions of the four valid pages can be checked.

As a result, the first super memory block (SUPER BLOCK <0>) includes the first page (P <0>) of the first memory block (BLOCK000) and the third page (P <) of the second memory block (BLOCK010). 2>), and only the second page (P <1>) of each of the third and fourth memory blocks (BLOCK <100, 110>) is a valid page (VAILD PAGE), and all remaining pages are invalid pages (INVALID PAGE). It can be seen that.

According to the check result, it can be seen that the four valid pages VAILD PAGE included in the first super memory block SUPER BLOCK <0> have different positions and the same positions. In addition, it can be seen that each of the four memory blocks MEMORY BLOCK <000, 010, 100, 110> included in the first super memory block SUPER BLOCK <0> includes one valid page. That is, the largest number of valid pages of each of the four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) included in the first super memory block SUPER BLOCK <0> is 1. have. This means that one read FIRST_READ must be performed to extract four valid data from four valid pages included in the first super memory block SUPER BLOCK <0>.

Accordingly, the controller 130 and the first page (P <0>) of the first memory block (BLOCK000) included in the first super memory block (SUPER BLOCK <0>) at the 0th time point t0, One read for each third page (P <2>) of the first memory block (BLOCK010) and the second page (P <1>) of each of the third and fourth memory blocks (BLOCK <100, 110>). FIRST_READ). Four page data B000P0_VD, B010P2_VD, B100P1_VD, and B110P1_VD are cached in four page buffers PB <000, 010, 100, and 110 through one read FIRST_READ. Subsequently, the controller 130 is valid for all four page data B000P0_VD, B010P2_VD, B100P1_VD, and B110P1_VD cached in the page buffers PB <000, 010, 100, and 110> at the first time point t1. Since the data is VALID DATA, all four page data B000P0_VD, B010P2_VD, B100P1_VD, and B110P1_VD are transferred to the internal memory 144 (DATA TRANSFER).

Thus, the controller 130, through one read (FIRST_READ), four valid pages (VAILD PAGE: BLOCK000_P <0>, BLOCK010_P <2>, included in the first super memory block (SUPER BLOCK <0>), All four valid data (VALID DATA: B000P0_VD, B010P2_VD, B100P1_VD, B110P1_VD) stored in BLOCK100_P <1> and BLOCK110_P <1> can be extracted.

Here, the time required to perform one read FIRST_READ may be assumed to be a read time tREAD. In addition, one page data (B000P0_VD or B010P2_VD or B100P1_VD or B110P1_VD) stored in one page buffer (PB <000> or PB <010> or PB <100> or PB <110>) is stored in the internal memory 144. The time required for transmission may be assumed to be a transmission time tTX. Assuming this, the first time required for extracting data by selecting the first super memory block (SUPER BLOCK <0>) as the victim block in garbage collection is '{read time (tREAD)'. * 1} + {transmission time (tTX) * 4} '. For example, assuming that the read time tREAD is 50us and the transfer time tTX is 10us, it is necessary to select the first super memory block SUPER BLOCK <0> as the victim block in the garbage collection and extract the data. The first time duration (TOTAL <0>) will be 90us.

In the garbage collection, the second super memory block SUPER BLOCK <1> illustrated in FIG. 7B is selected as a victim block and four memory blocks included therein (MEMORY BLOCK <001, 011, 101, 111>). In order to extract data from the four valid pages included in, the positions of the four valid pages may be checked.

As a result, the second super memory block (SUPER BLOCK <1>) has the first page (P <0>) of the first memory block (BLOCK001) and the second and third pages of the second memory block (BLOCK011). Notice that (P <1, 2>), and only the second page (P <1>) of the fourth memory block (BLOCK111) are valid pages (VAILD PAGE), and all remaining pages are invalid pages (INVALID PAGE). have.

According to the result of the check, it can be seen that the four valid pages VAILD PAGE included in the second super memory block SUPER BLOCK <1> have different positions and the same positions. In addition, the first and fourth memory blocks BLOCK <001, 111> of the four memory blocks (MEMORY BLOCK <001, 011, 101, 111>) included in the second super memory block (SUPER BLOCK <1>). Note that each one includes one valid page, the second memory block BLOCK011 includes two valid pages, and the third memory block BLOCK101 does not include the valid pages. That is, the largest number of valid pages of each of the four memory blocks MEMORY BLOCK <001, 011, 101, and 111> included in the second super memory block SUPER BLOCK <1> is 2. have. This means that two reads FIRST_READ and SECOND_READ must be performed to extract four valid data from four valid pages included in the second super memory block SUPER BLOCK <1>.

Accordingly, the controller 130 and the first page P <0> of the first memory block BLOCK001 included in the second super memory block SUPER BLOCK <1> at the zeroth time point t0 are separated from each other. The first read FIRST_READ is performed on the second page P <1> of each of the first to fourth memory blocks BLOCK <011, 101, and 111>. Four page data B001P0_VD, B011P1_VD, B101P1_IVD, and B111P1_VD are cached in four page buffers PB <001, 011, 101, and 111 through the first read FIRST_READ. Subsequently, the controller 130 may output three of the four page data B001P0_VD, B011P1_VD, B101P1_IVD, and B111P1_VD cached to the page buffers PB <001, 011, 101, and 111> at the first time point t1. Only valid data (VALID DATA: B001P0_VD, B011P1_VD, B111P1_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include one invalid data INVALID DATA: B101P1_IVD among four page data B001P0_VD, B011P1_VD, B101P1_IVD, and B111P1_VD cached in the page buffers PB <001, 011, 101, and 111>. ) Is discarded without being transferred to the internal memory 144.

Thus, the controller 130, through the first read (FIRST_READ), three valid pages (VAILD PAGE: BLOCK001_P <0>, BLOCK011_P <1>, included in the second super memory block (SUPER BLOCK <1>), Three valid data (VALID DATA: B001P0_VD, B011P1_VD, and B111P1_VD) stored in BLOCK111_P <1> may be extracted.

Subsequently, the controller 130 performs a third operation on each of the four memory blocks BLOCK <001, 011, 101, and 111> included in the second super memory block SUPER BLOCK <1> at the second time point t2. Perform a second read (SECOND_READ) for page P <2>. Four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD are cached in four page buffers PB <001, 011, 101, and 111> through the second read SECOND_READ. Subsequently, the controller 130 includes one of four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD cached in the page buffers PB <001, 011, 101, and 111> at the third time point t3. Only valid data (VALID DATA: B011P2_VD) is selected and transferred to the internal memory 144 (DATA TRANSFER). Of course, the controller 130 may include three invalid data INVALID DATA: B001P2_IVD among the four page data B001P2_IVD, B011P2_VD, B101P2_IVD, and B111P2_IVD cached in the page buffers PB <001, 011, 101, and 111>. , B101P2_IVD and B111P2_IVD are discarded without being transferred to the internal memory 144.

In this way, the controller 130, through the second read (SECOND_READ), one valid page stored in one valid page (VAILD PAGE: BLOCK011_P <2>) included in the second super memory block (SUPER BLOCK <1>). You can extract the data (VALID DATA: B011P2_VD).

In summary, the controller 130 may include four valid pages (VAILD PAGE: BLOCK001_P <0>, BLOCK011_P <1>, BLOCK011_P <2>, and BLOCK111_P <1 included in the second super memory block SUPER BLOCK <1>). It can be seen that two reads (FIRST_READ, SECOND_READ) are required to extract all four valid data (VALID DATA: B001P0_VD, B011P1_VD, B011P2_VD, B111P1_VD) stored in the>).

Here, the time required to perform one read FIRST_READ or SECOND_READ may be assumed to be a read time tREAD. In addition, one page data (B001P0_VD or B011P1_VD or B011P2_VD or B111P1_VD) stored in one page buffer (PB <001> or PB <011> or PB <101> or PB <111>) is stored in the internal memory 144. The time required for transmission may be assumed to be a transmission time tTX. Assuming this, the second time required to extract data by selecting the second super memory block (SUPER BLOCK <1>) as the victim block in garbage collection is '{read time (tREAD)'. * 2} + {transmission time (tTX) * 4} '. For example, assuming that the read time tREAD is 50us and the transfer time tTX is 10us, the second super memory block SUPER BLOCK <1> is selected as a victim block in the garbage collection to extract data. The second time duration (TOTAL <1>) will be 140us.

In summary, the first super memory block SUPER BLOCK <0> as illustrated in FIG. 7A and the second super memory block SUPER BLOCK <1> as illustrated in FIG. 7B each have four valid pages. In this case, when the victim block for garbage collection is selected based on the number of valid pages, it can be seen that the same condition exists.

However, when each of the super memory blocks SUPER BLOCK <0, 1> illustrated through FIGS. 7A and 7B is selected as a victim block for garbage collection, the first super memory block SUPER BLOCK illustrated in FIG. 7A is selected. The first time required to extract data from <0>) (TOTAL <0>) is 90us, while the second time required to extract data from the second super memory block (SUPER BLOCK <1>) illustrated in FIG. 7B. The time required (TOTAL <1>) is 140us, which shows a big difference.

That is, the controller 130 may perform the first super memory block SUPER BLOCK <0> of the super memory blocks SUPER BLOCK <0, 1> illustrated through FIGS. 7A and 7B to effectively perform garbage collection. It is preferable to select as the sacrificial block.

FIG. 8 is a diagram illustrating an operation of selecting a victim block when garbage collection is performed on a super memory block in the memory system according to the second embodiment of the present invention described with reference to FIGS. 7A and 7B. .

Referring to FIG. 8, the memory system 110 according to the second embodiment of the present invention includes a controller 130 and a memory device 150.

The controller 130 may include a garbage collection control unit 196 and a memory 144. Here, since the general operation of the garbage collection control unit 196 has been described with reference to FIG. 3, it will not be described in detail here.

As described with reference to FIG. 4, the memory device 150 includes a plurality of memory blocks MEMORY BLOCK <000, 001, ...>. In addition, the controller 130 may group N memory blocks capable of parallel reading among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 by grouping a plurality of memory blocks according to a set condition. Managed as super memory blocks (SUPER BLOCK <0: N>). At this time, N is a natural number of 2 or more, and it is assumed that N is 4 in FIGS. 7A and 7B. Here, together with the two super memory blocks SUPER BLOCK <0, 1> described with reference to FIGS. 7A and 7B, one super memory block SUPER BLOCK <2> in a free state is stored in the memory device ( Assume that it is included in 150). Of course, the matters illustrated in FIG. 8 are merely simplified for the sake of convenience of explanation, and in fact, may be extended to any other form (such as a larger number of super memory blocks are included in the memory device).

In detail, the controller 130 may include the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 for garbage collection through the garbage collection control unit 196 included therein. Predictions (PRE_TOTAL <0, 1>), which calculates the required time when extracting valid data in superblock units, are generated, and the required prediction times (PRE_TOTAL <0, 1>) are generated. It manages as time table 600. FIG.

In addition, the controller 130 controls the number of valid pages VPC <0 of each of the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 through the garbage collection control unit 196. : 1> is counted in superblock units, and the counted valid page counts VPC <0: 1> are managed as the valid page count table 610.

More specifically, the controller 130 may include four memory blocks BLOCK <000, 010, 100, 110>, and BLOCK <grouped in each of the plurality of super memory blocks SUPER BLOCK <0: 1>. 001, 011, 101, and 111) calculates the first time (FIRST_TIME <0: 1>) by multiplying the largest number (MB_CNT <0: 1>) of the number of valid pages by the read prediction time (PRE_tREAD) (FIRST_TIME) <0: 1> = MB_CNT <0: 1> * PRE_tREAD.

Also, the controller 130 may multiply the number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPERBLOCK <0: 1> by the transmission prediction time PRE_tTX, and the second time SECOND_TIME. <0: 1>) (SECOND_TIME <0: 1> = VPC <0: 1> * PRE_tTX).

In addition, the controller 130 calculates a value obtained by adding the first time FIRST_TIME <0: 1> and the second time SECOND_TIME <0: 1> (TOTAL <0: 1> = FIRST_TIME <0: 1>). + SECOND_TIME <0: 1>) to generate required prediction times PRE_TOTAL <0, 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>.

For example, referring to FIG. 7 together with FIG. 8 to illustrate, the first super memory block SUPER BLOCK <0> may include the first page P <0> of the first memory block BLOCK000, Only the third page (P <2>) of the second memory block (BLOCK010) and the second page (P <1>) of each of the third and fourth memory blocks (BLOCK <100, 110>) are valid pages (VAILD). PAGE), and all remaining pages are invalid pages (INVALID PAGE).

Accordingly, the controller 130 may know that the first valid page number VPC <0> included in the first super memory block SUPER BLOCK <0> is four.

In addition, the controller 130 may include one valid page for each of the four memory blocks BLOCK <000, 010, 100, and 110> grouped in the first super memory block SUPER BLOCK <0>. It can be seen that. That is, the largest number of valid pages (MB_CNT <0>) of each of the four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) included in the first super memory block SUPER BLOCK <0>. It can be seen that is 1.

Therefore, the first first time FIRST_TIME <0> corresponding to the first super memory block SUPER BLOCK <0> corresponds to one read prediction time PRE_tREAD through a calculation such as '1 * PRE_tREAD'. It's time to do it. Also, the first second time SECOND_TIME <0> corresponding to the first super memory block SUPER BLOCK <0> corresponds to four transmission prediction times PRE_tTX through a calculation such as '4 * PRE_tTX'. It's time to do it. In conclusion, the first required prediction time PRE_TOTAL <0> corresponding to the first super memory block SUPER BLOCK <0> is the first first time FIRST_TIME <corresponding to one read prediction time PRE_tREAD. 0>) and the first second time (SECOND_TIME <0>) corresponding to four transmission prediction times PRE_tTX.

For example, assuming that the lead prediction time PRE_tREAD is 50us and the transmission prediction time PRE_tTX is 10us, the first required prediction time PRE_TOTAL <0 corresponding to the first super memory block SUPER BLOCK <0> is assumed. >) Will be 90us plus 50us first first time (FIRST_TIME <0>) plus 40us first second time (SECOND_TIME <0>).

Similarly, referring to FIG. 7B together with FIG. 8 for an example, the second super memory block SUPER BLOCK <1> is the first page P <0> of the first memory block BLOCK001. Only the second and third pages (P <1, 2>) of the second memory block (BLOCK011) and the second page (P <1>) of the fourth memory block (BLOCK111) are valid pages (VAILD PAGE). It can be seen that all the remaining pages are invalid pages (INVALID PAGE).

Accordingly, the controller 130 may know that the second valid page number VPC <1> included in the second super memory block SUPER BLOCK <1> is four.

In addition, the controller 130 may include the first and fourth memory blocks (MEMORY BLOCK <001, 011, 101, 111>) included in the second super memory block SUPER BLOCK <1>. BLOCK <001, 111>) each contains one valid page, the second memory block (BLOCK011) contains two valid pages, and the third memory block (BLOCK101) does not contain valid pages. Can be. That is, the largest number (MB_CNT <1>) of the number of valid pages of each of the four memory blocks (MEMORY BLOCK <001, 011, 101, 111>) included in the second super memory block (SUPER BLOCK <1>). It can be seen that is 2.

Therefore, the second first time FIRST_TIME <1> corresponding to the second super memory block SUPER BLOCK <1> corresponds to two read prediction times PRE_tREAD through a calculation such as '2 * PRE_tREAD'. It's time to do it. In addition, the second second time SECOND_TIME <1> corresponding to the second super memory block SUPER BLOCK <1> corresponds to four transmission prediction times PRE_tTX through a calculation such as '4 * PRE_tTX'. It's time to do it. In conclusion, the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> is the second first time FIRST_TIME <corresponding to the two read prediction times PRE_tREAD. 1>) and the second second time SECOND_TIME <1> corresponding to four transmission prediction times PRE_tTX.

For example, assuming that the lead prediction time PRE_tREAD is 50us and the transmission prediction time is 10us, the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> is , The second first time of 100us (FIRST_TIME <1>) and the second second time of 40us (SECOND_TIME <1>) will be 140us.

For reference, the controller 130 may set information about the read prediction time PRE_tREAD and the transfer prediction time PRE_tTX for the memory device 150. That is, the designer may preset the read prediction time PRE_tREAD and the transfer prediction time PRE_tTX for the memory device 150 through a test according to the type or state of the memory device 150.

As described above, the controller 130 predicts the required prediction time PRE_TOTAL <0, 1> for each of the plurality of super memory blocks SUPER BLOCK <0: 1> before performing garbage collection. can do.

In addition, the controller 130 may estimate the required number of the super memory blocks SUPER BLOCK <0: 1> included in the required forecast time table 600 through the branch ratio collection control unit 196 included therein. Selecting a memory block among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 as a victim block for garbage collection by referring to the times PRE_TOTAL <0, 1>. You can decide if you want to.

At this time, the controller 130 refers to the required prediction times PRE_TOTAL <0, 1> for the plurality of super memory blocks SUPER BLOCK <0: 1> included in the required prediction time table 600. There may be two methods, and either method may be selected.

The first method is based on the predicted time of the relatively smallest required time among the predicted times PRE_TOTAL <0, 1> for the plurality of super memory blocks SUPER BLOCK <0: 1> in the controller 130. The memory block including at least one valid page among the N memory blocks grouped in the corresponding super memory block is selected as a victim block.

For example, as in the above description, the required prediction time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> is 90us, and the requirement for the second super memory block SUPER BLOCK <1>. Since the prediction time PRE_TOTAL <1> is 140us, the required prediction time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> is smaller. Accordingly, the controller 130 includes at least one valid page among four memory blocks MEMORY BLOCK <000, 010, 100, 110> grouped in the first super memory block SUPER BLOCK <0>. Four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) are selected as victim blocks.

In this way, since four memory blocks (MEMORY BLOCK <000, 010, 100, 110>) included in the first super memory block (SUPER BLOCK <0>) are selected as victim blocks, the garbage collection is performed. Four valid pages included in the first super memory block (SUPER BLOCK <0>) are transferred to the memory 144 in the controller 130, and then a third super memory block (SUPER BLOCK), which is a target block. <2>).

In the second method, before using the first method described above, the controller 130 checks the number of valid pages of each of the N memory blocks included in each of the plurality of super memory blocks SUPER BLOCK <0: 1>. This is a method of checking the number of super memory blocks whose combined number VPC <0: 1> is equal to or less than the set number. That is, the controller 130 may have one super memory block that is less than or equal to the set number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>. , Do not use the first scheme described above. On the other hand, the controller 130 may have at least two super memory blocks that are less than or equal to the set number of valid pages VPC <0: 1> of each of the plurality of super memory blocks SUPER BLOCK <0: 1>. Above ', the first method described above is used.

For example, unlike the above description, the number of valid pages VPC <0> of the first super memory block SUPER BLOCK <0> is 5 and the number of valid pages of the second super memory block SUPER BLOCK <1>. (VPC <1>) may be one. In addition, the controller 130 may set the 'set number' to two. In this case, the controller 130 may confirm that one super memory block, that is, the second super memory block SUPER BLOCK <1> has a valid number of pages less than or equal to the 'set number'. Accordingly, the controller 130 does not use the first method described above, but among the N memory blocks included in the second super memory block SUPER BLOCK <1> having a valid number of pages less than or equal to the 'set number'. A memory block including at least one valid page is selected as a victim block.

On the other hand, as in the above description, the number of valid pages VPC <0> of the first super memory block SUPER BLOCK <0> is 4 and the number of valid pages of the second super memory block SUPER BLOCK <1>. (VPC <1>) may also be four. In addition, the controller 130 may set the 'set number' to two. In this case, the controller 130 may determine that two super memory blocks, that is, the first super memory block SUPER BLOCK <0> and the second super memory block SUPER BLOCK <1> are both less than or equal to the 'set number'. It can be confirmed that it has a valid page number of. Accordingly, the controller 130 uses the first method described above to make N memories included in the first super memory block SUPER BLOCK <0> having a relatively smaller required prediction time PRE_TOTAL <0>. A memory block including at least one valid page among the blocks is selected as the victim block.

On the other hand, as described above, the controller 130 generates the required prediction times PRE_TOTAL <0, 1> and generates the required prediction times PRE_TOTAL <0, 1>. I manage it as).

In this case, the controller 130 may update the required prediction times PRE_TOTAL <0, 1> by using any one of the following two methods.

In the first method, the controller 130 may generate a specific memory block in which the number of valid pages is variable among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150. The required prediction time of the super memory block in which a specific memory block is grouped may be updated.

For example, referring to FIG. 4 and FIG. 7A, according to the first foreground operation or the background operation, the number of valid pages of the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0 may be calculated. Can be variable. Subsequently, the number of valid pages of the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0 may vary according to the execution of the second foreground operation or the background operation.

In this case, the controller 130 may respond to the change of the valid page of the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0, thereby causing the corresponding memory block BLOCK000 to be changed. The value of the first required prediction time PRE_TOTAL <0> corresponding to the grouped first super memory block SUPER BLOCK <0> may be predicted again. Subsequently, the controller 130 may group the corresponding memory block BLOCK001 in response to a change in the number of valid pages of the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0. The value of the second required prediction time PRE_TOTAL <1> corresponding to the second super memory block SUPER BLOCK <1> may be predicted again.

In the second method, the controller 130 checks whether there is a specific memory block having a variable number of valid pages among the memory blocks MEMORY BLOCK <000, 001, ...> for each 'set time point'. As a result, when there is a specific memory block having a variable number of valid pages, the required prediction time of the super memory block in which the specific memory block is grouped may be updated.

For example, referring to FIGS. 4 and 7A, at least two foreground operations or background operations consecutive between a first set time point (not shown) and a second set time point (not shown) may be performed to perform a first memory die ( The number of valid pages of the first memory block BLOCK000 of the first plane PLANE00 of DIE0 and the number of valid pages of the second memory block BLOCK001 may vary.

In this case, the controller 130 checks whether or not a memory block having a variable number of valid pages among the memory blocks MEMORY BLOCK <000, 001, ...> exists at the second set time point, and confirms that there is. As a result, it can be seen that the number of valid pages of each of the first memory block BLOCK000 and the second memory block BLOCK001 of the first plane PLANE00 of the first memory die DIE0 varies. Accordingly, the controller 130 may include the first super memory block SUPER BLOCK <0> in which the first memory block BLOCK000 of the first plane PLANE00 of the first memory die DIE0 is grouped at the second set time point. Second super memory block (BLOCK001) grouped with the value of the first expected time (PRE_TOTAL <0>) and the second memory block (BLOCK001) of the first plane (PLANE00) of the first memory die (DIE0). The value of the second required prediction time PRE_TOTAL <1> corresponding to SUPER BLOCK <1>) may be simultaneously predicted again.

For reference, the 'set time' may be predefined by the designer, and may be a time point that is repeated each time data of a set size is written or a time point that is repeated every time the execution of a specific operation is completed.

Meanwhile, garbage collection is performed so that all valid pages included in the first super memory block SUPER BLOCK <0> selected as the victim block are transferred to the memory 144 in the controller 130 and then the target block. If it is moved to the third super memory block (SUPER BLOCK <2>), the first super memory block (SUPER BLOCK <0>) will no longer have a valid page. Therefore, the first super memory block (SUPER BLOCK <0>) after garbage collection is an invalid super memory block in addition to the free super memory block through an erase operation. Need not be. However, since the controller 130 generates the first required time PRE_TOTAL <0> for the first super memory block SUPER BLOCK <0> before performing garbage collection, the controller 130 performs garbage collection. Thereafter, the value may remain in the required prediction time table 600. As such, an unknown abnormal operation may be performed on the first super memory block SUPER BLOCK <0> due to the value of the first predicted time PRE_TOTAL <0> remaining in the required time table 600. have. Therefore, after garbage collection is performed on the first super memory block SUPER BLOCK <0> selected as the victim block, the controller 130 corresponds to the first corresponding to the first super memory block SUPER BLOCK <0>. By setting the first expected time PRE_TOTAL <0> to 'scheduled value', an unknown abnormal operation on the first super memory block SUPER BLOCK <0> is prevented from being performed.

In summary, when a specific super memory block is selected as a victim block and all valid pages inside the target super memory block are moved through garbage collection, the controller 130 performs an unknown wrong operation. The estimated time required for a specific super memory block can be set to 'scheduled value'.

Meanwhile, if the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 is sufficiently large, the probability of garbage collection is not high. That is, in general, garbage collection is an operation performed when the number of free memory blocks included in the memory device 150 decreases below a predetermined number.

Accordingly, in the controller 130 according to the second exemplary embodiment, the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001,... The above-described required prediction times PRE_TOTAL <0, 1> are generated and managed in a section of 1 number 'or less. Of course, the controller 130 may include a 'second number' in which the number of free memory blocks among the memory blocks MEMORY BLOCK <000, 001, ...> included in the memory device 150 is greater than the 'first number'. 'It does not generate and manage required forecasting times PRE_TOTAL <0, 1> in the section above.

For reference, the first number may be set differently from the predetermined number for determining a trigger time of a general garbage collection operation. For example, the 'constant number' may be smaller than the 'first number'.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

Claims (20)

A plurality of pages each including a plurality of memory cells, a plurality of blocks each including the pages, a plurality of planes each including the blocks, A non-volatile memory device including a plurality of dies each including the planes, and page buffers for caching data output from the blocks in units of pages;
N times of parallel blocks among the blocks can be grouped according to a set condition to be managed as a plurality of superblocks, and a time required for extracting valid data from the blocks for garbage collection. The controller generates prediction time required by the superblock unit, and selects a victim block for the garbage collection among the blocks by referring to the required prediction time.
Wherein N is a natural number of two or more.
The method of claim 1,
The controller,
When parallel reading is possible only for pages of the same position in each of the N blocks grouped in the first superblock among the superblocks, grouping the first superblock into a first superblock in which the total number of valid pages of each of the N blocks is added together. A first time obtained by multiplying a lead prediction time by a number obtained by subtracting the number of valid pages having the same position in the N blocks, and a second time obtained by multiplying the transmission prediction time by the first number, and then the first time and the Generating a required prediction time corresponding to the first superblock by adding a second time, generating the required prediction times by applying a method of generating a required prediction time applied to the first super block to each of the superblocks,
The read prediction time is a time for predicting that it will take to cache the data of the blocks in the page buffers.
The transmission prediction time is a time for predicting that it takes to transmit data cached in the page buffers to the controller.
The method of claim 1,
The controller,
When parallel reading is possible for pages at different positions in each of the N blocks grouped in the second superblock among the superblocks, a third value obtained by multiplying the lead prediction time by the largest number of valid pages of each of the N blocks After calculating the fourth time obtained by multiplying the transmission prediction time by the sum of the time and the number of valid pages of each of the N blocks, the required time corresponding to the second superblock is added by adding the third time and the fourth time. Generating time, generating the required prediction time by applying the method of generating the required prediction time applied to the second superblock to each of the superblocks,
The read prediction time is a time for predicting that it will take to cache the data of the blocks in the page buffers.
The transmission prediction time is a time for predicting that it takes to transmit data cached in the page buffers to the controller.
The method of claim 1,
The controller,
Each time a block having a variable number of valid pages occurs among the blocks, the memory system re-predicts a value of a required prediction time corresponding to a superblock in which the variable number of valid pages is grouped.
The method of claim 1,
The controller,
Check whether there is a variable variable number of valid pages among the blocks at each set time point, and if there is a result of the check, re-predict the required predicted time value corresponding to the superblock in which the variable number of valid pages is grouped. Memory system to operate on.
The method of claim 1,
The controller,
And selecting a block including at least one valid page from among N blocks grouped in a superblock corresponding to a required prediction time having a relatively small value among the required prediction times as the victim block.
The method of claim 1,
The controller,
A superblock having a number equal to or less than a set number of all the effective pages of each of the N blocks grouped in each of the superblocks,
In case of one, N blocks grouped in one selected superblock are selected as the victim blocks,
In the case of at least two or more, at least one or more valid pages of N blocks grouped in a superblock corresponding to a relatively smallest value among at least two or more required predictive time values corresponding to at least two or more superblocks. Selecting a block as the victim block.
The method of claim 1,
The controller,
When N blocks grouped in a third superblock among the superblocks are selected as the victim blocks and all valid data is moved to a target block through the garbage collection, the corresponding blocks correspond to the third superblock. Memory system that sets the required forecast time to a predetermined value.
The method of claim 1,
The controller,
The number of free blocks of the blocks,
Generating and managing the required prediction times in a section less than or equal to a first number;
The memory system does not manage the required prediction times in a section greater than or equal to the second number greater than the first number.
The method of claim 1,
A first die of the dies is connected to a first channel, a second die of the dies is connected to a second channel, and the planes included in the first die share the first channel. Are connected to a plurality of first paths, and the planes included in the second die are connected to a plurality of second paths sharing the second channel,
The controller,
Grouping a first block included in a first plane of the first die and a second block included in a second plane of the first die, and a first included in a third plane of the second die. Grouping the third block and the fourth block included in the fourth plane of the second die in the set condition, or
Grouping a first block included in a first plane of the first die and a third block included in a third plane of the second die, and a first contained in the second plane of the first die. Grouping the second block and the fourth block included in the fourth plane of the second die in the set condition, or
A first block included in a first plane of the first die, a second block included in a second plane of the first die, a third block included in a third plane of the second die, and the first block Grouping the fourth block included in the fourth plane of the two die into the set condition.
A plurality of pages each including a plurality of memory cells, a plurality of blocks each including the pages, a plurality of planes each including the blocks, And a nonvolatile memory device including a plurality of dies each including the planes, and page buffers for caching data output from the blocks in units of pages. In the operation method,
Grouping N blocks capable of parallel reading among the blocks according to a set condition and managing the plurality of blocks as a plurality of superblocks;
A generation step of generating prediction time required by calculating a necessary time required to extract valid data from the blocks for garbage collection in a superblock unit; And
Selecting a victim block for the garbage collection among the blocks by referring to the required prediction times;
Including, N is a natural number of two or more operating method of the memory system.
The method of claim 11,
When parallel reading is possible only for pages of the same position in each of N blocks grouped in a first superblock among the superblocks, the generating step may include:
The lead prediction time is obtained by subtracting the number of valid pages having the same position in the N blocks grouped in the first superblock from the first number of the total number of valid pages of the N blocks grouped in the first superblock. Calculating a multiplied first time;
Calculating a second time obtained by multiplying the first number by a transmission prediction time;
Generating a required prediction time corresponding to the first super block by adding the first time and the second time; And
Generating the required prediction times by applying the method of generating the required prediction time applied to the first superblock to each of the superblocks,
The read prediction time is a time for predicting that it will take to cache data of the blocks in the page buffers, and the transmission prediction time is a time for predicting that it will take to transmit the data cached in the page buffers to the controller. Operation method of in-memory system.
The method of claim 11,
When parallel reads are possible for pages at different positions in each of N blocks grouped in a second superblock among the superblocks, the generating step may include:
Calculating a third time obtained by multiplying a lead prediction time by a largest number of valid pages of each of the N blocks grouped in the second superblock;
Calculating a fourth time obtained by multiplying a transmission prediction time by a sum of the total number of valid pages of each of the N blocks grouped in the second superblock;
Generating a required prediction time corresponding to the second superblock by adding the third time and the fourth time; And
Generating the required prediction times by applying the method of generating the required prediction time applied to the second superblock to each of the superblocks,
The read prediction time is a time for predicting that it will take to cache data of the blocks in the page buffers, and the transmission prediction time is a time for predicting that it will take to transmit the data cached in the page buffers to the controller. Operation method of in-memory system.
The method of claim 11,
Each time a block having a variable number of valid pages occurs among the blocks, the method further includes predicting and calculating a value of a required prediction time corresponding to the superblock in which the variable number of valid pages is grouped. How to operate.
The method of claim 11,
Check whether there is a variable variable number of valid pages among the blocks at each set time point, and if there is a result of the check, re-predict the required predicted time value corresponding to the superblock in which the variable number of valid pages is grouped. And operating the memory system.
The method of claim 11,
The selection step,
Selecting a victim block including at least one valid page from among N blocks grouped in a superblock corresponding to a required prediction time having a relatively small value among the required prediction times as the victim block; How it works.
The method of claim 11,
The selection step,
When there is one superblock whose total number of valid pages of each of the N blocks grouped in each of the superblocks is equal to or less than a set number, selecting N blocks grouped into the selected superblock as the victim blocks ; And
In the case where at least two or more superblocks having the sum of the number of valid pages of each of the N blocks grouped to each of the superblocks are less than or equal to a set number, at least two or more required prediction times corresponding to at least two or more superblocks are determined. Selecting a block including at least one or more valid pages among N blocks grouped in a superblock corresponding to a relatively small value among values as the victim block.
The method of claim 11,
When N blocks grouped to a third superblock among the superblocks are selected as the victim blocks and all valid data is moved to a target block through the garbage collection, the corresponding blocks correspond to the third superblock. And setting the required prediction time to a predetermined value.
The method of claim 11,
The generating step,
Generating and managing the required prediction times in a section in which the number of free blocks among the blocks is less than or equal to a first number; And
And managing the required prediction times in a section in which a number of free blocks among the blocks is greater than or equal to a second number greater than the first number.
The method of claim 11,
A first die of the dies is connected to a first channel, a second die of the dies is connected to a second channel, and the planes included in the first die share the first channel. Are connected to a plurality of first paths, and the planes included in the second die are connected to a plurality of second paths sharing the second channel,
The set condition is,
Grouping a first block included in a first plane of the first die and a second block included in a second plane of the first die, and a first included in a third plane of the second die. Grouping three blocks and a fourth block included in the fourth plane of the second die, or
Grouping a first block included in a first plane of the first die and a third block included in a third plane of the second die, and a first contained in the second plane of the first die. Grouping two blocks and a fourth block included in the fourth plane of the second die, or
A first block included in a first plane of the first die, a second block included in a second plane of the first die, a third block included in a third plane of the second die, and the first block Grouping the fourth block included in the fourth plane of the two die.

Images