KR20190114701A - Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices - Google Patents

Abstract

Provided is a semiconductor memory device including a memory cell array and a repair control circuit. The memory cell array includes a plurality of memory blocks and at least one redundancy block. The repair control circuit responds to an access column address for accessing the memory cell array and repairs a first fail cell of a first memory block among the memory blocks to a first normal cell of the first memory block. The first fail cell and the first normal cell have different column selection line addresses. Accordingly, the semiconductor memory device may use a repair resource with almost maximum efficiency.

Description

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

The present invention relates to a memory device, and more particularly, to a semiconductor memory device, a memory system, and a method of operating a semiconductor memory device.

The semiconductor chip is made through a semiconductor manufacturing process, and then tested by test equipment in a wafer, die, or package state. Through the test, the defective part or the defective chip is selected, and if some memory cells are defective, repair is performed to rescue the semiconductor chip. As semiconductor chips such as DRAM continue to be finely processed, the possibility of errors in the manufacturing process is increasing. In addition, an error may occur during chip operation even if it is not detected in the initial test stage.

One object of the present invention is to provide a semiconductor memory device capable of efficiently utilizing redundancy resources.

One object of the present invention is to provide a memory system that can efficiently use redundancy resources.

One object of the present invention is to provide a method of operating a semiconductor memory device that can efficiently use redundancy resources.

A semiconductor memory device according to embodiments of the present invention for achieving the above object includes a memory cell array and a repair control circuit. The memory cell array includes a plurality of memory blocks and at least one redundancy block. The repair control circuit repairs a repair control circuit for repairing a first fail cell of a first memory block among the memory blocks to a first normal cell of the first memory block in response to an access column address for accessing the memory cell array. Include. The first fail cell and the first normal cell have different column select line addresses.

Memory system according to embodiments of the present invention for achieving the above object includes at least one semiconductor memory device and a memory controller. The memory controller controls the at least one semiconductor memory device. The at least one semiconductor memory device includes a memory cell array and a repair control circuit. The memory cell array includes a plurality of memory blocks and at least one redundancy block. The repair control circuit repairs a repair control circuit for repairing a first fail cell of a first memory block among the memory blocks to a first normal cell of the first memory block in response to an access column address for accessing the memory cell array. Include. The first fail cell and the first normal cell have different column select line addresses.

In a method of operating a semiconductor memory device including a memory cell array including a plurality of memory blocks and at least one redundancy block according to embodiments of the present invention for achieving the above object, It is determined whether an access column address and a first column address designating a first bit line connected to a first fail cell of a first memory block among the memory blocks are not the same, and the access column address and the first column address are determined to be the same. If is equal to, repair the first fail cell to at least one first normal cell of the first memory block. The first fail cell and the first normal cell have different column select line addresses.

According to embodiments of the present invention, in the repair control circuit of the semiconductor memory device, the repair control circuit repairs a fail cell of at least one memory block to at least one normal cell of the same memory block at least once, and the repaired normal The cell may be repaired by the redundancy cell of the redundancy block. Therefore, the semiconductor memory device can use the redundancy resources of the redundancy block with almost maximum efficiency.

1 is a block diagram illustrating a memory system according to example embodiments.
FIG. 2A is a block diagram illustrating an example of a semiconductor memory device in the memory system of FIG. 1, according to example embodiments.
2B illustrates a portion of the semiconductor memory device of FIG. 2A in accordance with embodiments of the present invention.
3 illustrates a portion of the semiconductor memory device of FIG. 2A in accordance with embodiments of the present invention.
4A is a block diagram illustrating a configuration of a first unit repair controller in the semiconductor memory device of FIG. 3, according to example embodiments.
FIG. 4B illustrates a configuration of a column select line driver in the first unit repair controller of FIG. 4A according to embodiments of the present disclosure.
FIG. 5 is a block diagram illustrating a configuration of a redundancy repair controller in the semiconductor memory device of FIG. 3 according to example embodiments. FIG.
6A illustrates a repair operation performed in the semiconductor memory device of FIG. 3.
6B illustrates another example of a repair operation performed in the semiconductor memory device of FIG. 2B.
6C illustrates data input / output during the repair operation of FIG. 6A.
FIG. 6D illustrates data input / output during the repair operation of FIG. 6B.
FIG. 7 illustrates an address storage table in the first unit repair controller of FIG. 4.
FIG. 8 is a diagram for explaining an address storage table of FIG. 7.
9A to 9C illustrate a method of replacing a fail cell of a memory block with a normal cell of the same memory block and replacing a normal cell with a redundancy cell.
10 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.
FIG. 11 is a block diagram illustrating another example of a semiconductor memory device in the memory system of FIG. 1 according to example embodiments. FIG.
FIG. 12 illustrates a first bank array in the semiconductor memory device of FIG. 12 according to example embodiments. FIG.
FIG. 13 illustrates a repair control circuit that may be included in each of the bank column decoders in the semiconductor memory device of FIG. 12, according to example embodiments.
FIG. 14 illustrates a fail address storage circuit in the repair control circuit of FIG. 13.
FIG. 15 illustrates a portion of the semiconductor memory device of FIG. 11.
16A illustrates a repair operation performed in the semiconductor memory device of FIG. 15.
FIG. 16B is an example illustrating another configuration of the first bank array in FIG. 15.
FIG. 17 illustrates an address storage table in the repair control circuit of FIG. 13.
18 illustrates a method of operating a semiconductor memory device according to example embodiments.
19 is an exemplary block diagram illustrating a semiconductor memory device according to example embodiments.
20 is a block diagram illustrating an example in which the semiconductor memory device of FIG. 19 is applied to a 3D chip structure according to example embodiments.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a memory system according to example embodiments.

Referring to FIG. 1, the memory system 20 may include a memory controller 100 and at least one semiconductor memory device 200.

The memory controller 100 controls overall operations of the memory system 20 and controls overall data exchange between an external host and the semiconductor memory device 200. For example, the memory controller 100 controls the semiconductor memory device 200 at the request of the host to write data or to read data. In addition, the memory controller 100 applies operation commands for controlling the semiconductor memory device 200 to control the operation of the semiconductor memory device 200.

According to an embodiment, the semiconductor memory device 200 may be a dynamic random access (DRAM) having dynamic memory cells, a double data rate 4 (DRAM4) synchronous DRAM (DDR4) or a low power DDR4 (LPDDR4) SDRAM, or an LPDDR5 SDRAM. have.

The memory controller 100 may transmit a clock signal CLK, a command CMD, and an address ADDR to the semiconductor memory device 200, and exchange data DQ with the semiconductor memory device 200.

The semiconductor memory device 200 may include a memory cell array 300, a control logic circuit 210, and a repair control circuit 400. The data DQ may be stored in the memory cell array 300. The memory cell array 300 may include a plurality of memory blocks and at least one redundancy block.

The control logic circuit 210 controls access to the memory cell array 300 based on the command CMD and the address ADDR, and the repair control circuit 400 controls the plurality of memory blocks based on the address ADDR. The fail cell of at least one of the memory blocks may be repaired with a normal cell of the same memory block, and the normal cell may be repaired with a redundancy cell of the redundancy block to use the redundancy resources of the redundancy block at almost maximum efficiency.

That is, the repair control circuit 400 not only repairs fail cells of the memory block to redundancy cells, but repairs the fail cell of the memory block to another normal cell of the same memory block at least once, and replaces the other normal cell to the redundancy cell. Because of the repair, the repair resources of the redundancy block can be used with almost maximum efficiency.

FIG. 2A is a block diagram illustrating an example of a semiconductor memory device in the memory system of FIG. 1, according to example embodiments.

Referring to FIG. 2A, the semiconductor memory device 200a may include a control logic circuit 210a, an address buffer 251, a repair control circuit 400a, a row decoder 261, an input / output gating circuit 290a, and a data input / output buffer ( 296 and a memory cell array 301.

The control logic circuit 210a receives the command CMD and the access address ADDR. The control logic circuit 210a controls the operation of the semiconductor memory device 200a based on the command CMD and the access address ADDR. The control logic circuit 210a may control the row decoder 261, the input / output gating circuit 290a, and the repair control circuit 400a based on the command CMD and the access address ADDR.

The address buffer 251 provides the row address RADDR of the access address ADDR to the row decoder 261, and the column address CADD to the repair control circuit 400a. The repair control circuit 400a repairs at least one fail cell of the memory cell array 301 to a normal cell of the same memory block at least once based on a comparison between the column address CADD and the fail column address stored therein. The normal cell may be repaired by the redundancy cell of the redundancy block of the memory cell array 301.

The row decoder 261 is connected to the memory cell array 301 through word lines WLs, and the input / output gating circuit 290a is connected to the memory cell array 301 through bit lines BTLs. The data input / output buffer 296 may exchange data DQ with the memory controller 100 through the input / output gating circuit 290a.

2B illustrates a portion of the semiconductor memory device of FIG. 2A in accordance with embodiments of the present invention.

2B illustrates a memory cell array 301, an input / output gating circuit 290a, a data input / output buffer 296, and a repair control circuit 400a.

Referring to FIG. 2B, the memory cell array 301 may include a normal cell array NCA and a redundancy cell array RCA, and the normal cell array NCA may include a plurality of memory blocks MB0 to MB3. The redundancy cell array RCA may include at least one redundancy block RMB. The normal cell array NCA may include memory cells MC connected to word lines WLs and bit lines BTLs, and the redundancy block RMB includes word lines WL and redundancy bit lines. It may include a redundancy cell (RMC) connected to the (RBTL).

The input / output gating circuit 290a may include a plurality of input / output circuits 291a to 291e and a plurality of column select circuits 293a to 293e, and the column select circuits 293a to 293e include the input / output circuits 291a. ~ 291e may be connected to the corresponding memory blocks MB0 to MB3 and the redundancy block RMB. Each of the column select circuits 293a to 293e may include a plurality of column select transistors 294a to 294d, and each of the column select transistors 294a to 294d may be each of the column select line signals CSLa to CSLe. In response, each of the column select transistors 294a to 294d may be connected to a plurality of bit lines or bit lines of the corresponding memory block. The input / output circuits 291a to 291e may be connected to the data input / output buffer 296 through the data lines GIO.

Although not shown, a column select line signal CSLb is applied to the column select circuit 293b, a column select line signal CSLc is applied to the column select circuit 293c, and a column selector is applied to the column select circuit 293d. The line signal CSLd may be applied, and the column select line signal CSLe may be applied to the column select circuit 293e.

The repair control circuit 400a may provide the column select line signals CSLa to CSLe to each of the column select circuits 293a to 293e based on the column address CADDR. The column address CADDR is provided in the address buffer 251 of FIG. 2A and is an address that designates one bit line without considering whether a fail cell exists in the memory blocks MB0 to MB3. Each of the column select line signals CSLa to CSLd is a signal for simultaneously selecting bit lines corresponding to each of the memory blocks MB0 to MB3 based on the column address CADDR. Accordingly, data in burst length units may be simultaneously input and output in the semiconductor memory device 200a by the column select line signals CSLa to CSLd.

3 illustrates a portion of the semiconductor memory device of FIG. 2A in accordance with embodiments of the present invention.

3 illustrates a memory cell array 301, an input / output gating circuit 290a, a repair control circuit 400a, and a data input / output buffer 296. In comparison with FIG. 2B, the configuration of the repair control circuit 400a is illustrated in more detail in FIG. 3. Therefore, in FIG. 3, the structure of the repair control circuit 400a is mainly described.

Referring to FIG. 3, the memory cell array 301 may include a normal cell array NCA and a redundancy cell array RCA, and the normal cell array NCA may include a plurality of memory blocks MB0 to MB3. The redundancy cell array RCA may include at least one redundancy block RMB.

Each of the memory blocks MB0 to MB3 may include a plurality of memory cells connected to word lines and bit lines, and the redundancy block RMB includes a plurality of redundancy connected to word lines and redundancy bit lines. It may include cells.

The repair control circuit 400a may include a plurality of unit repair controllers 401a to 40d and a redundancy repair controller 401e, and the unit repair controllers 401a to 40d and the redundancy repair controller 401e may be memory blocks. To MBMB to MB3 and the redundancy block RMB. The repair control circuit 400a may be included in a column decoder (not shown) of the semiconductor memory device 200a.

The input / output circuits 291a to 291e correspond to the memory blocks MB0 to MB3 and the redundancy block RMB and the data input / output buffer 296 in response to the first control signal CTL1 from the control logic circuit 210a of FIG. 2A. Control the connections between The column select circuits 293a to 293e may connect the input / output circuits 291a to 291e to corresponding memory blocks MB0 to MB3 and the redundancy block RMB.

The unit repair controllers 401a to 401d and the redundancy repair controller 401e receive the column address CADD in common and respond to the corresponding memory blocks MB0 to MB3 and the redundancy block in response to the change in the column address CADDR. The column select line signals CSLa to CSLe applied to the RMB may be provided to the corresponding column select circuits 293a to 293e.

When the memory blocks MB0 to MB3 do not include a fail cell, the input / output circuit 291e cuts off the connection to the redundancy block RMB in response to the first control signal CTL1, and the input / output circuits 291a ~ 291d transfers the data DQ from the memory blocks MB0 to MB3 to the data input / output buffer 296 through the column select circuits 293a to 293d, or the data from the data input / output buffer 296. DQ) may be transferred to the memory blocks MB0 to MB3. In this case, bit lines or bit lines of the same position are selected in each of the memory blocks MB0 to MB3 by the column select line signals CSLa to CSLd applied to the memory blocks MB0 to MB3. Data in burst length units of the apparatus 200a may be input / output through the data input / output buffer 296.

When at least one memory block of the memory blocks MB0 to MB3 includes at least one fail cell, the input / output circuit 291e is redundancy through the column select circuit 293e in response to the first control signal CTL1. The repair operation on the at least one fail cell may be performed by being connected to the block RMB.

For example, when the memory blocks MB0, MB2, and MB3 each include at least one fail cell on at least one bit line selected by CSL0, the memory block MB0 may be referred to by reference numeral 511. Likewise, the fail cell can be repaired as a normal cell of the memory block MB0 by activating CSL3 at the activation timing of CSL0. That is, the CSL3 may be activated at the activation timing of the CSL0 to connect the column select transistor 294c to the memory block MB0 and the input / output circuit 291a instead of the column select transistor 294a. In addition, the normal cell of the memory block MB0 may be repaired into the redundancy cell of the redundancy block RMB, as indicated by reference numeral 512 at the activation timing of the CSL3. It is assumed that the memory block MB1 does not include a fail cell. That is, the repair control circuit 400a selects the CSL3 that selects the second bit line to which the first normal cell to repair the first fail cell is connected, instead of the CSL0 to select the first bit line to which the first fail cell is connected. The activation may repair the first fail cell to the first normal cell.

In the memory block MB2, as shown by reference numeral 513, the fail cell may be repaired to the normal cell of the memory block MB2 by activating CSL2 at the activation timing of CSL0. In addition, the normal cell of the memory block MB1 may be repaired into a corresponding redundancy cell of the redundancy block RMB, as indicated by reference numeral 514 at the activation timing of the CSL2. In the memory block MB3, as shown by reference numeral 515, the normal cell of the memory block MB3 may be repaired into a corresponding redundancy cell of the redundancy block RMB at the activation timing of the CSL0.

4A is a block diagram illustrating a configuration of a first unit repair controller in the semiconductor memory device of FIG. 3, according to example embodiments.

Referring to FIG. 4A, the first unit repair controller 401a includes a table pointer 405, an address storage table 420, a column address comparator 430, a selection circuit 440, and a column select line driver 450. can do.

The table pointer 405 generates a table pointing signal TPS that is toggled in response to the sequentially changing column address CADD. At least one source column address SRCA and at least one destination column address DSCA corresponding thereto are stored in the address storage table 420 as fuse information.

The column address comparator 430 compares the access column address CADD with the source column address SRCA output from the address storage table 420, and outputs a match signal MTH1 indicating the result of the comparison. The selection circuit 440 selects one of the destination column address DSCA and the access column address CADDr output from the address storage table 420 in response to the match signal MTH1 and outputs it to the target column address CA. . The column select line driver 450 outputs a column select line signal CSLa for selecting (activating) a bit line corresponding to the target column address CA.

For example, when the access column address CADDR and the source column address SRCA do not match, the selection circuit 440 may convert the access column address CADDR into the target column address CA in response to the match signal MTH1. Can be output as For example, when the access column address CADDR and the source column address SRCA match, the selection circuit 440 sets the destination column address DSCA as the target column address CA in response to the match signal MTH1. You can print Therefore, a column address of a bit line connected to at least one fail cell of the memory block MB0 is stored as fuse information in the address storage table 420 as a source column address SRCA, and replaces the fail cell. When the column address of the bit line connected to the normal cell of MB0 is stored as fuse information as the destination column address DSCA, the fail cell of the memory block MB0 may be repaired as a normal cell. The normal cell may also be repaired into a redundancy cell of the redundancy block (RMC).

In an embodiment, the selection circuit 440 performs an exclusive OR operation on the upper part bits of the access column address CADDR and the bits of the destination column address DSCA in response to the match signal MTH1. It can be configured as an address change circuit. That is, the address change circuit has an access column address CADD when the access column address CADD is composed of 6 bits and the destination column address DSCA is composed of 3 bits, when the match signal MTH1 is at a high level. The CADDR may perform bit-by-bit XOR operations on the upper 3 bits and the destination column address DSCA, and output the bits to the target column address CA.

In FIG. 3, the configuration of each of the unit repair controllers 401b, 401c, and 401d may be substantially the same as that of the first unit repair controller 401a of FIG. 4A.

FIG. 4B illustrates a configuration of a column select line driver in the first unit repair controller of FIG. 4A according to embodiments of the present disclosure.

Referring to FIG. 4B, the column select line driver 450 may include driving transistors 451, 452, 453, and 454, inverters 455 and 456, and a NAND gate 457.

The NAND gate 457 performs a NAND operation on the target column address CA and the active master signal PCSLE. The driving transistor 451 includes a source connected to the power supply voltage VDD, a gate receiving the output of the inverter 457, and a source connected to the first node NO1. The driving transistor 452 includes a drain connected to the first node NO1, a gate to which the inactive master signal PCSLD is applied, and a source connected to the driving transistor 453. The driving transistor 453 has a drain connected to the driving transistor 452, a gate connected to the output of the inverter 457, and a source connected to the ground voltage VSS.

The inverter 455 inverts the voltage level of the first node NO1 and outputs it to the second node NO2, and the inverter 456 inverts the voltage level of the second node NO2 so that the column select line signal CSLa is inverted. ) The driving transistor 454 includes a drain connected to the first node NO1, a gate connected to the second node NO2, and a source connected to the ground voltage VSS.

When the target column address CA is applied at the high level and the active master signal PCSLE is applied at the high level, the output of the NAND gate 457 is at the low level. Accordingly, the driving transistors 451 are turned on and the driving transistor 453 is turned off. Accordingly, the first node NO1 is at the high level, the driving transistor 454 is turned off, and the inverter 456 outputs the high level column select line signal CSLa.

When the active master signal PCSLE goes low and the inactive master signal PCSLD goes high, the driving transistor 451 is turned off, and the driving transistors 452 and 453 are turned on. Therefore, the inverter 456 outputs a low level column select line signal CSLa. The active master signal PCSLE and the inactive master signal PCSLD may be provided in a pre decoder provided in the column decoder including the repair control circuit 400a or the repair control circuit 400a. The predecoder may control the logic levels of the active master signal PCSLE and the inactive master signal PCSLD with reference to column selection line information of the fuse circuit 480 included in the redundancy repair controller 401d. Accordingly, the repair control circuit 400a of FIG. 3 controls the active master signal PCSLE and the inactive master signal PCSLD to select a first normal cell instead of a first fail cell, and a first redundancy instead of the first normal cell. You can select a cell.

FIG. 5 is a block diagram illustrating a configuration of a redundancy repair controller in the semiconductor memory device of FIG. 3 according to example embodiments. FIG.

Referring to FIG. 5, the redundancy repair controller 401e may include a table pointer 460, a fuse circuit 480, and a redundancy column select line driver 470.

The table pointer 460 generates a table pointing signal TPS that is toggled in response to the sequentially changing column address CADD. The fuse circuit 480 stores column select line information related to each of the redundancy bit lines of the redundancy block RMC. That is, in the fuse circuit 480, information of the memory blocks MB3, MB2, and MB0 to be repaired at the time of activation of each of CSL0, CSL2, and CSL3 is stored as fuse information.

The redundancy column select line driver 470 refers to column select line information of the fuse circuit 480 and selects at least some of the redundancy bit lines in response to the table pointing signal TPS. Outputs

Accordingly, referring to FIGS. 3 to 5, the repair control circuit 400a repairs the first fail cell to the first normal cell of the same memory block using at least two fuse information, and repairs the first normal cell of the redundancy block. Repair to the first redundancy cell.

6A illustrates a repair operation performed in the semiconductor memory device of FIG. 3.

In FIG. 6A, it is assumed that the repair condition of the memory cell array 301 is the same as the reference numeral 521. The repair condition of the memory cell array 301 may be determined in consideration of the location of the fail cell of each of the memory blocks MB0 to MB3. That is, the semiconductor memory device 200a determines a repair condition such that the redundancy resources of the redundancy block RMB for repairing the fail cell or the normal cell of the memory blocks MB0, MB3, and MB3 including the fail cell do not overlap each other. Can support burst operation.

3 to 6A, when the CSL0 operation 522 of the memory blocks MB0 to MB3 is designated by the access column address CADD, the memory block MB0 corresponds to CSL3 instead of a fail cell. The first normal cell is selected (that is, the column select transistor 294d is activated instead of the column select transistor 294a in the memory block MB0), and the normal cell corresponding to CSL0 is selected in the memory block MB1. In the memory block MB2, the first normal cell corresponding to the CSL2 is selected, and in the memory block MB3, the redundancy cell corresponding to the CSL0 of the redundancy block RMB is selected instead of the fail cell. That is, in the CSL0 operation, a repair operation of replacing a fail cell with a corresponding first nomel cell in each of the memory blocks MB0 and MB2 is performed.

When the CSL1 operation 523 of the memory blocks MB0 to MB3 is designated by the access column address CADD, the normal cell corresponding to the CSL1 is selected from each of the memory blocks MB0 to MB3. When the CSL2 operation 524 of the memory blocks MB0 to MB3 is designated by the access column address CADD, the normal cell corresponding to the CSL2 is selected from each of the memory blocks MB0, MB1, and MB3, and the memory In block MB2, instead of selecting a memory cell corresponding to CSL2, a redundancy cell corresponding to CSL2 of the redundancy block RMB is selected.

When the CSL3 operation 525 of the memory blocks MB0 to MB3 is specified by the access column address CADD, a normal cell corresponding to CSL3 is selected from each of the memory blocks MB1, MB2, and MB3, and the memory In block MB0, instead of selecting a memory cell corresponding to CSL3, a redundancy cell corresponding to CSL3 of the redundancy block RMB is selected to perform a repair operation on the first normal cell.

6B illustrates another example of a repair operation performed in the semiconductor memory device of FIG. 2B.

2B and 6B, the repair condition 521a of the memory cell array 301 repairs a fail cell associated with CSL1 to the first normal cell associated with CSL3 in the memory block MB0 and performs a memory block (511a). The first normal cell of MB0 is repaired to the second normal cell of another memory block MB1 (512a), and the second normal cell is repaired to the first redundancy cell of the redundancy block RMB (513a, 514a, and 515a). That is, the repair control circuit 400a repairs the fail cell of the first memory block MB0 to the first normal cell of the first memory block MB0, and repairs the first normal cell to the second of the second memory block MB1. Repair with a normal cell and repair the second normal cell with a first redundancy cell. The first normal cell, the second normal cell, and the first redundancy cell may have the same column select line address.

When the CSL0 operation 526 of the memory blocks MB0 to MB3 and the redundancy block RMB is designated by the access column address CADD, in each of the memory blocks MB0 to MB3, the normal cell corresponding to the CSL0 is selected. Is selected. When the CSL1 operation 527 of the memory blocks MB0 to MB3 and the redundancy block RMB is designated by the access column address CADD, in the memory block MB0, the first normal corresponding to the CSL3 instead of the fail cell. A cell is selected, and a normal cell corresponding to CSL1 is selected in each of the memory blocks MB1 to MB3.

When the CSL3 operation 528 of the memory blocks MB0 to MB3 and the redundancy block RMB is designated by the access column address CADD, the memory block MB0 may replace the memory block MB1 instead of the first normal cell. The second normal cell corresponding to CSL3 is selected, the normal cell corresponding to CSL3 is selected in the memory block MB2, the normal cell corresponding to CSL3 is selected in the memory block MB3, and the redundancy block RMB Also, the first redundancy cell corresponding to CSL3 is selected. Accordingly, the semiconductor memory device 200a may efficiently use the redundancy resources of the redundancy block RMB while supporting data input / output in units of burst length.

6C illustrates data input / output during the repair operation of FIG. 6A.

Referring to FIG. 6C, when the repair condition of the memory cell array 301 is the same as that of FIG. 6A, the column selection circuits 293a to 293e and the selection circuits 2916 to 2919 and 2915 included in the input / output gating circuit 290a may be used. It can be seen that data selected in the memory blocks MB0 to MB3 and the redundancy block RMB are provided to the data input / output buffer 296 in units of burst lengths BL0 to BL3. That is, the selection circuit 2911 can select the output of one of the column selection circuits 293a and 293e, and the selection circuit 2912 can select the output of one of the column selection circuits 293b and 293e, The selection circuit 2913 may select the output of one of the column selection circuits 293c and 293e, and the selection circuit 2914 may select the output of one of the column selection circuits 293d and 293e.

In the CSL0 operation, the selection circuit 2911 selects data output from the memory block MB0 based on the signals {0, 0, 0, 1} output from the selection circuit 2915, and the selection circuit 2912 uses the memory block. It is understood that the data output from the MB1 is selected, the selection circuit 2913 selects the data output from the memory block MB2, and the selection circuit 2914 selects the data output from the redundancy block RMB. Can

FIG. 6D illustrates data input / output during the repair operation of FIG. 6B.

Referring to FIG. 6D, when the repair condition of the memory cell array 301 is the same as that of FIG. 6B, the column selection circuits 293a to 293e and the selection circuits 2916 to 2919 and 2915 included in the input / output gating circuit 290a are used. It can be seen that data selected in the memory blocks MB0 to MB3 and the redundancy block RMB are provided to the data input / output buffer 296 in units of burst lengths BL0 to BL3. In other words. The selector circuit 2916 can select the output of one of the adjacent column selector circuits 293a and 293b and the selector circuit 2919 can select the output of one of the adjacent column selector circuits 293d and 293e. have.

Referring to FIG. 6D, as described with reference to FIG. 6B, in the CSL3 operation, the selection circuit 2916 may output the selection circuit 2916 from the memory block MB1 by the signals {1, 1, 1, 1) output from the selection circuit 2915. The data to be output is selected, the selection circuit 2917 selects the data output from the memory block MB2, the selection circuit 2918 selects the data output from the memory block MB3, and the selection circuit 2919 is selected. It can be seen that selects the data output from the redundancy block (RMB).

FIG. 7 illustrates an address storage table in the first unit repair controller of FIG. 4.

Referring to FIG. 7, the address storage table 420 stores a first storage unit 421 storing a source column address SRCA to be repaired and a destination column address DSCA to replace the source column address SRCA. The second storage unit 423 and the sensing unit 425 may be included. The address storage table 420 may be configured as an anti-fuse array or content addressable memory (CAM). The sensing unit 425 may output a source column address SRCA and a destination column address DSCA provided in the address storage table 420 in response to the table pointing signal TPS. In FIG. 7, the address storage table 420 stores the first column address CADDR1 associated with CSL0 and the fourth column address CADDR4 associated with CSL3 as the source column address SRCA, and the second column address DSCA as the destination column address DSCA. The fourth column address CADDR4 replacing the first column address CADDR1 and the fourth redundancy column address RCADDR4 replacing the fourth column address CADDR4 are stored.

FIG. 8 is a diagram for explaining an address storage table of FIG. 7.

Referring to FIG. 8, the address storage table 420 may be configured as an anti-fuse array including a plurality of anti-fuses 422. The anti-fuse 422 has an electrical characteristic opposite to that of the fuse device and is a resistive fuse device having a high resistance value in the unprogrammed state while having a low resistance value in the programmed state. The address storage table 420 may selectively program the antifuses 422 to store the source column address SRCA and the destination column address DSCA.

The sensing unit 425 may include first and second sub-sensing units 4251 and 4252 connected to the first and second storage units 421 and 425, respectively. 4251 and 4252 may be formed of NMOS transistors 426. Accordingly, the sensing unit 425a may provide the source column address SRCA to the column address comparator 430 and the destination column address DSCA to the selection circuit 440 in response to the table pointing signal TPS.

9A to 9C illustrate a method of replacing a fail cell of a memory block with a normal cell of the same memory block and replacing a normal cell with a redundancy cell.

In FIGS. 9A to 9C, the memory block MB0 includes memory cells connected to word lines WL1 to WLu and bit lines BTL1 to BTLv, and the redundancy block RMB includes word lines WL1 to. WLu) and redundancy memory cells connected to the redundancy bit lines RBTL1 to RBTLv.

9A illustrates replacement (repair) between bit lines. For example, when a failure occurs in the memory cell connected to the word line WL1 and the bit line BTL1 in the memory block MB0, the bit line BTL1 is replaced with the bit line BTL4, and the bit line BTL3 is replaced. ) Can be replaced with the redundancy bit line RBTL4.

9B illustrates the substitution between portions of bit lines (segments of bit lines). At least one memory cell of one bit line may be divided into two or more segments. For example, when a failure occurs in the memory cell connected to the word line WL1 and the bit line BTL1 in the memory block MB0, the segment of the bit line BTL1 including the memory cell in which the failure occurs is divided into a bit line ( A segment of the bit line BTL4 may be replaced with a segment of the redundancy bit line RBTL4.

Fig. 9C illustrates the substitution between memory cells. For example, when a failure occurs in the memory cell connected to the word line WL1 and the bit line BTL1 in the memory block MB0, the defective memory cell is replaced with a memory cell connected to the bit line BTL4. The memory cell connected to the bit line BTL4 may be replaced with the memory cell connected to the redundancy bit line RBTL4.

10 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

2A through 10, in a method of operating a semiconductor memory device including a memory cell array including a plurality of memory blocks and at least one redundancy blocks, a first fail of a first memory block of the plurality of memory blocks is performed. The cell is repaired as the first normal cell of the first memory block (S100). Before repairing the first fail cell of the first memory block to the first normal cell of the first memory block, it is determined whether the access column address is the same as the first column address of the first bit line to which the first fail cell is connected. Can be. As a result of the determination, if the access column address is the same as the first column address (source column address), the repair may be performed.

Here, the first fail cell and the first normal cell of the first memory block have different column select line addresses. That is, the first fail cell and the first normal cell of the first memory block are connected to bit lines selected by different column select line (CSL) signals. In addition, the first fail cell and the first normal cell of the first memory block may be connected to the same input / output circuit. The first normal cell of the first memory block is repaired to the first redundancy cell of the redundancy block (S200). Here, the first normal cell and the first redundancy cell may have the same column select line address. In addition, the first normal cell and the first redundancy cell may be connected to different input / output circuits.

FIG. 11 is a block diagram illustrating another example of a semiconductor memory device in the memory system of FIG. 1 according to example embodiments. FIG.

Referring to FIG. 11, the semiconductor memory device 200b may include a control logic circuit 210, an address register 220, a bank control logic 230, a refresh counter 245, a row address multiplexer 240, and a column address latch ( 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier 285, an input / output gating circuit 290, and a data input / output buffer 295.

In an embodiment, the semiconductor memory device 200b may further include an error correction code (ECC) engine 280.

The memory cell array 300 may include first to eighth bank arrays 310 to 380. In addition, the row decoder 260 may include first to eighth bank row decoders 260a to 260h connected to the first to eighth bank arrays 310 to 380, respectively. First to eighth bank column decoders 270a to 270h connected to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifier unit 285 includes first to eighth bank arrays. First to eighth bank sense amplifiers 285a to 285h respectively connected to the first and second banks 310 to 380. First to eighth bank arrays 310 to 380, first to eighth bank sense amplifiers 285a to 285h, first to eighth bank column decoders 270a to 270h, and first to eighth banks The row decoders 260a to 260h may configure the first to eighth banks, respectively. Each of the first through eighth bank arrays 310 ˜ 380 is formed at a point where a plurality of word lines WL, a plurality of bit lines BL, word lines WL, and bit lines BTL cross each other. It may include a plurality of memory cells (MC) formed.

The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address RADDR, and a column address CADDR from the memory controller 100. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address RADDR to the row address multiplexer 240, and provides the received column address CADDR. The column address latch 250 may be provided.

The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to a bank address BANK_ADDR of the first to eighth bank row decoders 260a to 260h is activated, and the first to eighth bank column decoders 270a are activated. The bank column decoder corresponding to the bank address BANK_ADDR may be activated.

The row address multiplexer 240 may receive the row address RADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address RADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h, respectively.

The bank row decoder activated by the bank control logic 230 among the first to eighth bank row decoders 260a to 260h decodes the row address RA output from the row address multiplexer 240 to the row address. The corresponding word line can be activated. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address. In addition, the activated bank row decoder may activate the spare word line corresponding to the spare row address SRA output from the repair control circuit 400 at the same time as activating the word line corresponding to the row address.

The column address latch 250 may receive the column address CADDR from the address register 220 and temporarily store the received column address CADDR. In addition, the column address latch 250 may gradually increase the received column address CADDR in the burst mode. The column address latch 250 may apply the temporarily stored or incrementally increased column address CADD to the first to eighth bank column decoders 270a to 270h, respectively.

The bank column decoder activated by the bank control logic 230 among the first to eighth bank column decoders 270a to 270h corresponds to the bank address BANK_ADDR and the column address CADDR through the input / output gating circuit 290. Can activate a sense amplifier. In addition, the activated bank column decoder may include a repair control circuit, wherein the repair control circuit repairs a fail cell of at least one memory block of a corresponding bank array to a first normal cell of the same memory block, and the first normal. The cell may be repaired into the first redundancy cell of the redundancy block.

Each of the input / output gating circuits of the input / output gating circuit block 290, together with the circuits for gating the input / output data, is used to store data output from the input data mask logic and the first to eighth bank arrays 310 to 380. Write drivers may be used to write data to the read data latches and the first to eighth bank arrays 310 to 380.

Data to be read in one bank array of the first to eighth bank arrays 310 to 380 may be sensed by a sense amplifier corresponding to the one bank array, and stored in the read data latches. Data stored in the read data latches may be provided to the memory controller 100 through a data input / output buffer 295. Data DQ to be written to one of the first to eighth bank arrays 310 to 380 may be written to the one bank array through the write drivers.

When the semiconductor memory device 200b includes the ECC engine 280, the ECC engine 280 performs ECC encoding on data to be written, provides a codeword to the input / output gating circuit 290, and reads the codeword. ECC decoding may be performed on the to provide the error corrected data to the data input / output buffer 280.

The data input / output buffer 295 provides the data DQ to the ECC engine 280 based on the clock signal CLK provided from the memory controller 100 in the write operation and from the ECC engine 280 in the read operation. The data may be provided to the memory controller 100.

The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate control signals for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 for decoding a command CMD received from the memory controller 100 and a mode register 212 for setting an operation mode of the semiconductor memory device 200. Can be.

For example, the command decoder 211 may generate the control signals corresponding to the command CMD by decoding the write enable signal, the row address strobe signal, the column address strobe signal, the chip select signal, and the like. For example, the control logic circuit 210 may provide the first control signal CTL1 to the input / output gating circuit 290 and the second control signal CTL2 to the ECC engine 280.

FIG. 12 illustrates a first bank array in the semiconductor memory device of FIG. 12 according to example embodiments. FIG.

Referring to FIG. 12, the first bank array 310 may include a normal cell array NCA and a redundancy cell array RCA. The normal cell array NCA includes word lines WL1 to WLm, m is an integer of 2 or more, a plurality of bit lines BTL1 to BTLn, n is an integer of 2 or more, and word lines WL1 to WLm and a bit. It includes a plurality of memory cells MCs disposed at intersections between the lines BTL1 to BTLn. The redundancy cell array RCA includes word lines WL1 to WLm and a plurality of redundancy cells RMCs connected to the redundancy bit lines BTL1 to BTLt.

FIG. 13 illustrates a repair control circuit that may be included in each of the bank column decoders in the semiconductor memory device of FIG. 12, according to example embodiments.

Referring to FIG. 13, the repair control circuit 400b may include an address comparison circuit 405 and a unit repair controller 402.

The address comparison circuit 405 compares the address information of at least one fail cell generated in the memory cell array 300 with the row address RADDR, and outputs a row match signal RM based on the result of the comparison. Can be. The address comparison circuit 405 may include an address storage circuit 410 and a row address comparator 415.

The address storage circuit 410 stores the row address information FRAI and the column address information FCAI of at least one fail cell generated in the normal cell array. The fail address storage table 410 may be configured of nonvolatile memory elements to store location information of the fail cell. For example, the fail address storage table 410 may be configured as an anti-fuse (AF) or a fuse to store location information of the fail cell. Location information of the fail cell stored in the fail address storage table 410 may be updated.

For example, location information of fail cells additionally generated due to continuous use of the semiconductor memory device 200b may be updated in the fail address storage table 410. In addition, location information of additional fail cells generated after the package of the semiconductor memory device 200b may also be updated in the fail address storage table 410. The location information of the fail cell may be obtained by testing whether a fail bit is generated in the semiconductor memory device 200b. The test may be performed before the package of the semiconductor memory device 200b, that is, at the wafer level, or after the package of the semiconductor memory device 200b. That is, post package repair (PPR) may be possible through the repair control circuit 400.

The location information of the fail cell may be row address information FRAI of the fail cell and / or column address information FCAI of the fail cell.

The row address comparator 415 stores the row address information FRAI provided from the fail address storage table 410. The row address comparator 415 may be provided with the row address information FRAI at the same time as the driving of the semiconductor memory device 200, or may be provided after a predetermined time from the driving of the semiconductor memory device 200b. The row address comparator 400 receives the row address RADDR of the access address ADDR, compares the row address RADDR and the row address information FRAI, and compares the row address RADDR and the row address information FRAI. If is matched, the row match signal RM is output.

The unit repair controller 402a includes a table pointer 405, an address storage table 420b, a column address comparator 430, an end gate 435, a selection circuit 440, and a column select line driver 450.

The fail address storage table 430 sequentially stores column address information FCAI of fail cells and column address information of first normal cells for repairing the fail cells as a source column address SRCA, and the second normal. Column address information of cells and column address information of second normal cells for repairing the first normal cells may be sequentially stored as a destination column address (DSCA). The table pointer 405 applies a table pointing signal TPS, which is toggled in response to the sequentially converted access column address CADD, to the address storage table 420b, and the address storage table 420b receives the table pointing signal ( In response to the TPS, the source column address SRCA and the destination column address DSCA corresponding to the source column address SRCA may be output.

The column address comparator 430 compares the access column address CADD with the source column address SRCA output from the address storage table 420b, and outputs a first match signal MTH1 indicating the result of the comparison. The AND gate 435 performs an AND operation on the low match signal RM and the first match signal MTH1 to output the second match signal MTH2. The selection circuit 440 selects one of the destination column address DSCA and the access column address CADDR output from the address storage table 420b in response to the second match signal MTH2 to the target column address CA. Output The column select line driver 450 outputs a column select line signal CSLa for selecting (activating) a bit line corresponding to the target column address CA.

For example, when the row match signal RM is low level or the access column address CADDR and the source column address SRCA do not match, the selection circuit 440 accesses in response to the second match signal MTH2. The column address CADD may be output as the target column address CA. For example, when the row match signal RM is at a high level and the access column address CADDR and the source column address SRCA match, the selection circuit 440 responds to the second match signal MTH2 with the destination column. The address DSCA can be output as the target column address CA.

FIG. 14 illustrates a fail address storage circuit in the repair control circuit of FIG. 13.

Referring to FIG. 14, the fail address storage table 410 may include an anti-fuse array 411, a controller 412, a detector 413, and a register 414.

The anti-fuse array 411 may include p * q antifuses AF that are connected to intersections of p rows and q columns, respectively. The antifuse array 411 includes p word lines AWL1 to AWLp for accessing antifuses arranged in the p rows, and q columns to transfer information read from the antifuses AF. Q bit lines ABL1 to ABLq correspondingly disposed.

The controller 412 programs the location information of the fail cells in the antifuse array 411 or reads the location information of the fail cells from the antifuse array 411. The detector 413 may detect / amplify and output location information of the fail cells provided from the antifuse array 411. The register unit 414 may temporarily store location information of fail cells provided from the detector 413. The register unit 414 outputs row address information FRAI and column address information FCAI of fail cells to the row address comparator 420 and the address storage table 420b, respectively.

FIG. 15 illustrates a portion of the semiconductor memory device of FIG. 11.

In FIG. 15, a first bank array 310, an input / output gating circuit 290, a column decoder 270a, and a data input / output buffer 295 are illustrated.

Referring to FIG. 15, the first bank array 310 may include a normal cell array NCA and a redundancy cell array RCA. The normal cell array NCA may include a plurality of memory blocks MB0 to MB15, 311, 312, and 313, and the redundancy cell array RCA may include at least one redundancy block 314. The memory blocks 311, 312, and 313 are blocks that determine a memory capacity of the semiconductor memory device 200. The redundancy block 314 is a block for redundancy repair.

Each of the memory blocks 311, 312, 313 includes a plurality of memory cells arranged in rows and columns, and the redundancy block 314 also includes a plurality of redundancy cells arranged in rows and columns.

The input / output gating circuit 290 may include a plurality of input / output circuits 292a to 292d and a plurality of column select circuits 296a to 296d, and the column select circuits 296a to 296d may be memory input / output circuits ( 292a to 292d may be connected to the corresponding memory blocks 311, 312, and 313 and the redundancy block 314. Each of the column select circuits 296a to 296d may include a plurality of column select transistors 297a to 297h, and each of the column select transistors 297a to 297h may be each of the column select line signals CSLa to CSLg. In response, each of the column select transistors 297a to 297h may be connected to a plurality of bit lines or bit lines of the corresponding memory block. The input / output circuits 292a to 292d may be connected to the data input / output buffer 295 through data lines (not shown). For example, when the column select line signal applied to the column select transistor 297a is activated, a bit connected to the column select transistor 297a in each of the memory blocks 311, 312, and 313 and the redundancy block 314. Line (s) may be selected at the same time. For example, when the column select line signal applied to the column select transistor 297h is activated, a bit connected to the column select transistor 297h in each of the memory blocks 311, 312, and 313 and the redundancy block 314. Line (s) may be selected at the same time.

The column decoder 270a may include a predecoder (not shown), a plurality of unit repair controllers 402a to 402c, and a redundancy repair controller 402e. The predecoder is decoded by decoding a column address CADDR. The column address may be provided to the repair controllers 402a to 402c and the redundancy repair controller 402e in common.

The unit repair controllers 402a to 402c and the redundancy repair controller 402e receive a column address CADD or a decoded column address in common and correspond to a memory corresponding to a change in the column address CADD or the decoded column address. The column select line signals CSLa to CSLg applied to the blocks MB0 to MB3 and the redundancy block 314 may be provided to the corresponding column select circuits 296a to 296d.

The repair control circuit 400b repairs at least one fail cell of the memory blocks 311 to 313 to a first normal cell of the same memory block, repairs the first normal cell to a second normal cell of the same memory block. The second normal cell may be repaired as the first redundancy cell of the redundancy block 314 so that the redundancy resource of the redundancy block 314 of the semiconductor memory device 200b may be used at the maximum efficiency.

16A illustrates a repair operation performed in the semiconductor memory device of FIG. 15.

Referring to FIG. 16A, in the memory block 311, the repair condition 541 of the first bank array 310a repairs the fail cell associated with CSL0 to the first normal cell associated with CSL3, and the first normal cell Repair 532 to a second normal cell associated with CSL7, and repair the second normal cell 533 to the corresponding redundancy cell of redundancy block 314. In addition, the memory block 313 repairs the fail cell associated with the CSL0 to the corresponding redundancy cell of the redundancy block 314.

When the CSL0 operation 542 of the memory blocks 311 to 314 is designated by the access column address CADDr, the first normal cell corresponding to the CSL3 is selected in the memory block 311 instead of the fail cell, and the memory is selected. In block 312, a normal cell corresponding to CSL0 is selected, and in memory block 313, a redundancy cell corresponding to CSL0 of the redundancy block 314 is selected instead of a fail cell.

When the CSL3 operation 543 of the memory blocks 311 to 314 is designated by the access column address CADD, the second normal cell corresponding to the CSL7 is selected in the memory block 311 instead of the first normal cell. In the memory block 312, the normal cell corresponding to the CSL3 is selected, and in the memory block 313, the normal cell corresponding to the CSL3 is selected.

When the CSL7 operation 544 of the memory blocks 311 to 314 is designated by the access column address CADD, in the memory block 311, the redundancy of the redundancy block 314 corresponding to the CSL7 is used instead of the third normal cell. The cell is selected, the normal cell corresponding to CSL7 is selected in the memory block 312, and the normal cell corresponding to CSL7 is selected in the memory block 313.

FIG. 16B is an example illustrating another configuration of the first bank array in FIG. 15.

In FIG. 16A, each of the memory blocks MB0 to MB15 and the redundancy block RMB1 in the first bank array 310a has the same size. In FIG. 16B, the memory blocks MB0 to MB3 in the first bank array 310b are the same. Each size is larger than the size of the redundancy block RMB2. That is, the size of each of the memory blocks MB0 to MB15 is twice the size of the redundancy block RMB2.

In FIG. 16B, each of the memory blocks MB0 to MB3 may include an upper block CSL0 to CSL3 and a lower block CSL4 to CSL7 according to the most significant bit of the access column address. If the arrangement of the fail cells is as shown in FIG. 16B, the most significant bit of the access column address is d'ont cared to repair a fail cell or a normal cell of the memory blocks MB0, MB1, and MB1 including the fail cell. The repair condition may be determined so that the redundancy resources of the redundancy block RMB2 do not overlap each other, thereby supporting the burst operation of the semiconductor memory device 200b.

That is, the fuse information FI_MB1 is set so that the normal cell corresponding to CSL5 is selected instead of CSL4 in the memory block MB1, and the fuse information is selected such that the normal cell corresponding to CSL2 is selected instead of CSL0 in the memory block MB2. Set (FI_MB2). Also, in each of the memory blocks MB0 to MB3, when CSL0 and CSL4 are designated, a redundancy cell corresponding to CSL0 may be selected in the redundancy block RMB2. To this end, the fuse circuit 480b may store fuse information as shown.

FIG. 17 illustrates an address storage table in the repair control circuit of FIG. 13.

Referring to FIG. 17, the address storage table 420b stores a first storage unit 421b which stores a source column address SRCA to be repaired, and a destination column address DSCA to replace the source column address SRCA. The second storage unit 423b and the sensing unit 425b may be included. The address storage table 420b may be configured as an anti-fuse array or content addressable memory (CAM). The sensing unit 425b may output the source column address SRCA and the destination column address DSCA provided in the address storage table 420b in response to the table pointing signal TPS. In FIG. 17, as the source column address SRCA, the address storage table 420b includes a first column address CADD1 associated with CSL0, a fourth column address CADD4 associated with CSL3, and an eighth column address CADD4 associated with CSL7. A fourth column address CADDR4 for storing and replacing the first column address CADDR1 as a destination column address DSCA, an eighth column address CADD4 for replacing the fourth column address CADDR4, and an eighth column address; The eighth redundancy column address RCADDR8 that replaces the CADDR4 is stored.

18 illustrates a method of operating a semiconductor memory device according to example embodiments.

11 to 18, in a method of operating a semiconductor memory device 200b including a memory cell array 300 including a plurality of memory blocks and at least one redundancy blocks, a first of a plurality of memory blocks may be used. The first fail cell of the memory block is repaired to the first normal cell of the first memory block (S310). The first normal cell is repaired as the second normal cell of the first memory block (S330). Here, the first fail cell, the first normal cell, and the second normal cell of the first memory block have different column select line addresses. That is, the first fail cell, the first normal cell, and the second normal cell of the first memory block are connected to bit lines selected by different CSLs. In addition, the first fail cell, the first normal cell, and the second normal cell of the first memory block may be connected to the same input / output circuit.

The second normal cell of the first memory block is repaired to the first redundancy cell of the redundancy block (S350). Here, the second normal cell and the first redundancy cell may have the same column select line address. In addition, the second normal cell and the first redundancy cell may be connected to different input / output circuits.

19 is an exemplary block diagram illustrating a semiconductor memory device according to example embodiments.

Referring to FIG. 19, the semiconductor memory device 600 may include a first group die 610 and a second group die 620 to provide an analysis and rescue function of soft data fail in a stacked chip structure. have.

The first group die 610 may be formed of at least one buffer die. The second group die 620 is stacked on top of the first group die 610 and includes a plurality of memory dies 620-1, 620-2, which communicate data through a plurality of through silicon via (TSV) lines. ..., 620-p).

At least one of the plurality of memory dies 620-1, 620-2,..., 620-p generates a first type ECC using transmission data transmitted to the first group die 610. Engine 622 may be included. Here, since the first type ECC engine 622 is a circuit installed in the memory die, the first type ECC engine 622 may be referred to as a cell core ECC engine.

The buffer die 610 is a second type ECC engine that generates error corrected data by correcting a transmission error using transmission parity bits when a transmission error occurs in transmission data received through the plurality of TSV lines. 612). Here, the second type ECC engine 612 may be referred to as a via ECC engine because it is a circuit for correcting a failure of a transmission path. The buffer die 610 may also include a repair control circuit 614, and the repair control circuit 614 may be implemented with the repair control circuit 400b of FIG. 13.

The semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that communicates the data and control signals through the TSV lines. The TSV lines may also be referred to as silicon through electrodes.

The first type ECC engine 622 may also perform error correction on data output from the memory die 620-p before transmission data is transmitted.

The data TSV line group 632 formed in one memory die 620-p may be composed of a plurality of TSV lines L1 to Lp, and the parity TSV line group 634 may include a plurality of TSV lines ( L10 to Lq). The TSV lines L1 to Lp of the data TSV line group 632 and the TSV lines L10 to Lq of the parity TSV line group 634 are formed of a plurality of memory dies 620-1 to 620 -p. It may be connected to the corresponding micro bumps (MCB) formed between.

At least one of the plurality of memory dies 620-1 to 620 -p may have DRAM cells including one access transistor and one storage capacitor.

The semiconductor memory device 600 may have a 3D chip structure or a 2.5D chip structure to communicate with the memory controller through the data bus B10. The buffer die 610 may be connected to a memory controller through the data bus B10.

The first type ECC engine 622, which is a cell core ECC engine, outputs transmission data through the data TSV line group 632. In addition, the first type ECC engine 622 outputs transmission parity bits via the parity TSV line group 634. The output transmission data may be data error corrected by the first type ECC engine 632.

The second type ECC engine 612 checks whether a transmission error has occurred in the transmission data received through the data TSV line group 632 using the transmission parity bits received through the parity TSV line group 634. . If a transmission error occurs, the second type ECC engine 612 corrects the transmission error for the transmission data using the transmission parity bits. When the number of bits of the transmission error cannot be corrected, the second type ECC circuit 612 may output information indicating the occurrence of a data error.

20 is a block diagram illustrating an example in which the semiconductor memory device of FIG. 19 is applied to a 3D chip structure according to example embodiments.

20 illustrates a 3D chip structure 700 directly connecting a host and an HBM without interposing an interposer layer.

Referring to FIG. 20, a host die 720, which may be an SoC, a CPG, or a GPU, is disposed on the PCB 710 through flip chip bumps FB. Memory dies D11 to D14 for forming the HBM 620 structure are stacked on the host die 720. In FIG. 20, the buffer die 610 or the logic die of FIG. 19 is omitted, but may be disposed between the memory die D11 and the host die 720. In order to implement the HBM 620 structure, TSV lines called silicon through electrodes are formed in the memory dies D11 to D14. TSV lines may be electrically connected to micro bumps (MCBs) formed between memory dies.

The present invention can be applied to a system using semiconductor memory devices.

Although described above with reference to the embodiments of the present invention, those skilled in the art various modifications and changes to the present invention without departing from the spirit and scope of the invention described in the claims below I will understand.

Claims (20)

A memory cell array including a plurality of memory blocks and at least one redundancy block; And
A repair control circuit for repairing a first fail cell of a first memory block of the memory blocks to a first normal cell of the first memory block in response to an access column address for accessing the memory cell array;
And the first fail cell and the first normal cell have different column select line addresses. The method of claim 1,
And the repair control circuit repairs the first normal cell to a first redundancy cell of the redundancy block. The method of claim 2,
And the first normal cell and the first redundancy cell have the same column select line address. The method of claim 2,
And a plurality of input / output circuits corresponding to the plurality of memory blocks and the redundancy block.
The first fail cell and the first normal cell are connected to the same input / output circuit among the plurality of input / output circuits, and the first normal cell and the redundancy cell are different input / output circuits among the plurality of input / output circuits. Semiconductor memory devices respectively connected to the semiconductor memory devices. The method of claim 2,
The repair control circuit performs a repair on the first fail cell and a repair on the first normal cell by using at least two pieces of fuse information. 3. The repair control circuit of claim 2, wherein the repair control circuit
A plurality of unit repair controllers corresponding to the plurality of memory blocks and the redundancy block and a redundancy repair controller,
A first unit repair controller corresponding to the first memory block among the plurality of unit repair controllers may be
An address storage table in which the column address of the first fail cell and the column address of the first normal cell are respectively stored as a source column address and a destination column address;
A column address comparator that compares the access column address with the source column address and outputs a match signal;
A selection circuit for selecting one of the destination column address and the access column address in response to the match signal and outputting the selected column to a target column address; And
And a column select line driver configured to output a column select line signal for selecting a bit line corresponding to the target column address. The method of claim 6,
The column address of the first normal cell and the column address of the first redundancy cell are respectively stored in the address storage table as the source column address and the destination column address, respectively.
The first unit repair controller
And a table pointer for applying a table pointing signal toggled in response to the access column address to the address storage table. The redundancy repair controller of claim 6, wherein the redundancy repair controller corresponding to the redundancy block comprises:
A table pointer for providing a table pointing signal toggled in response to the change of the access column address;
A fuse circuit for storing column select line information associated with each of the redundancy bit lines of the redundancy block; And
And a redundancy column select line driver for referring to the column select line information and outputting a redundancy column select line signal for selecting at least some of the redundancy bit lines in response to the table pointing signal. 3. The repair control circuit of claim 2, wherein the repair control circuit
A plurality of unit repair controllers corresponding to the plurality of memory blocks and the redundancy block and a redundancy repair controller,
A first unit repair controller corresponding to the first memory block among the plurality of unit repair controllers may be
An address storage table in which the column address of the first fail cell and the column address of the first normal cell are respectively stored as a source column address and a destination column address;
A column address comparator that compares the access column address with the source column address and outputs a match signal;
An address change circuit configured to perform a bitwise exclusive OR operation on the bits of the destination column address and some upper bits of the access column address in response to the match signal, and output the result to a target column address; And
And a column select line driver configured to output a column select line signal for selecting a bit line corresponding to the target column address. The method of claim 1,
The memory cell array comprises a plurality of bank arrays,
Each of the plurality of bank arrays includes the plurality of memory blocks and the redundancy block,
The size of each of the plurality of memory blocks is equal to or larger than the size of the redundancy block,
The repair control circuit is included in each of a plurality of column decoders corresponding to each of the plurality of bank arrays. The method of claim 1,
And the repair control circuit repairs the first normal cell to a second normal cell of the first memory block, and repairs the second normal cell to a first redundancy cell of the redundancy block. The method of claim 11,
The first normal cell and the second normal cell have different column select line addresses, and the second normal cell and the first redundancy cell have the same column select line address. 12. The repair control circuit of claim 11, wherein the repair control circuit is
A plurality of unit repair controllers corresponding to the plurality of memory blocks and the redundancy block and a redundancy repair controller,
A first unit repair controller corresponding to the first memory block among the plurality of unit repair controllers may be
The column address of the first fail cell, the column address of the first normal cell, and the column address of the second normal cell are sequentially stored as a source column address, the column address of the first normal cell, and the second normal cell. An address storage table in which the column address of and the column address of the first redundancy cell are sequentially stored as a destination column address;
A column address comparator comparing the access column address with the source column address and outputting a first match signal;
The row match signal and the first match signal indicating that the row address and the access row address of the word line to which the first fail cell, the first normal cell, the second normal cell, and the first redundancy cell are connected are coincident. An AND gate for performing an AND operation to output a second match signal;
A selection circuit for selecting one of the destination column address and the access column address in response to the second match signal and outputting the selected column to a target column address; And
And a column select line driver configured to output a column select line signal for selecting a bit line corresponding to the target column address. The method of claim 13,
And a plurality of input / output circuits corresponding to the plurality of memory blocks and the redundancy block.
The first fail cell, the first normal cell, and the second normal cell are connected to the same input / output circuit among the plurality of input / output circuits, and the second normal cell and the redundancy cell are the plurality of input / output circuits. The semiconductor memory device is connected to different input and output circuits, respectively. The method of claim 11,
The memory cell array comprises a plurality of bank arrays,
Each of the plurality of bank arrays includes the plurality of memory blocks and the redundancy block,
The repair control circuit is included in each of a plurality of column decoders corresponding to each of the plurality of bank arrays. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises:
A first group die having at least one buffer die; And
A second group die stacked on top of the first group die and having a plurality of memory dies for communicating data through a plurality of through lines,
Each of the plurality of memory dies comprises a plurality of dynamic memory cells;
And the at least one buffer die comprises the repair control circuit. At least one semiconductor memory device; And
A memory controller controlling the at least one semiconductor memory device;
The at least one semiconductor memory device
A memory cell array including a plurality of memory blocks and at least one redundancy block; And
A repair control circuit for repairing a first fail cell of a first memory block of the memory blocks to a first normal cell of the first memory block in response to an access column address for accessing the memory cell array;
And the first fail cell and the first normal cell have different column select line addresses. The method of claim 17,
The repair control circuit repairs the first normal cell to a second normal cell of the first memory block, repairs the second normal cell to a first redundancy cell of the redundancy block,
And the first normal cell and the second normal cell have different column select line addresses, and the second normal cell and the first redundancy cell have the same column select line address. A method of operating a semiconductor memory device including a memory cell array including a plurality of memory blocks and at least one redundancy block, the method comprising:
Determining whether an access column address for accessing the memory cell array and a first column address designating a first bit line connected to a first fail cell of a first memory block among the memory blocks are not the same; And
If the access column address and the first column address are the same, repairing the first fail cell to at least one first normal cell of the first memory block;
And the first fail cell and the first normal cell have different column select line addresses. The method of claim 19,
Repairing the first fail cell to the first normal cell swaps the first column address specifying the first bit line with a second column address specifying a second bit line to which the second normal cell is connected. Performed,
The method is
Repairing the first normal cell to a first redundancy cell of the redundancy block.

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