KR20190102998A - Data storage device and operating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and, more specifically, to a controller, a data storage device, and an operating method thereof. According to an embodiment of the present invention, the controller for controlling a nonvolatile memory device comprises: a read count table including a plurality of read count data, wherein each read count data includes a read count for one data storage region; a read count address table including a read count address which is an address of a memory region having the read count data stored therein; a flash conversion layer for managing the read count table and the read count address table while controlling an operation of a data storage device; and a flash interface layer for updating the read count on the basis of the read count address when a read operation for a plurality of data storage regions is operated while controlling a data communication between the flash conversion layer and the nonvolatile memory device.

Description

Controller, Data Storage Device and How It Works {DATA STORAGE DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to a semiconductor device, and more particularly to a controller, a data storage device and a method of operating the same.

Recently, the paradigm of the computer environment has been shifted to ubiquitous computing that enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like is increasing rapidly. Such portable electronic devices generally use a data storage device using a memory device. Data storage devices are used to store data used in portable electronic devices.

The data storage device using the memory device has the advantage of having no mechanical driving part, which is excellent in stability and durability, and the information access speed is very fast and the power consumption is low. Data storage devices having this advantage include universal serial bus (USB) memory devices, memory cards with various interfaces, universal flash storage (UFS) devices, and solid state drives.

One embodiment of the present invention is to provide a technique for a data storage device to maintain the independence of a flash translation layer and a flash interface layer.

According to one embodiment of the present invention, a controller for controlling a nonvolatile memory device includes a plurality of read count data, each read count data including a read count for one data storage area, and a read count. A read count address table including a read count address, which is an address of a memory area in which data is stored, and a flash translation layer and a flash change layer and a nonvolatile memory that control operations of the data storage device and manage the read count table and the read count address table. The apparatus may include a flash interface layer that controls data communication between devices, and updates a read count based on a read count address when a read operation occurs for a plurality of data storage areas.

According to an embodiment of the present invention, in order to control an operation of a nonvolatile memory device, in a method of operating a controller including a flash translation layer and a flash interface layer, a plurality of flash interface layers are included in the nonvolatile memory device. The read count address (hereinafter, referred to as “th”) is an address of a memory area in which read count data (hereinafter, “first read count data”) including read counts of a first data storage area in which a read operation is performed is performed. 1 read count address') to the flash translation layer, the flash translation layer sending a first read count address to the flash interface layer in response to a request of the flash translation layer, and the flash interface layer from the flash translation layer. A first read count based on the received first read count address By looking up the memory area the data is stored, it is possible to include a step of updating the read count with a first lead-count data.

According to an embodiment of the present invention, the data storage device may maintain the independence of the flash translation layer and the flash interface layer.

1 is a diagram illustrating a configuration of a data storage device according to an embodiment of the present invention.
FIG. 2 is a diagram showing the configuration of the memory of FIG. 1; FIG.
3 is a diagram for explaining a data storage area according to one embodiment of the present invention;
4 is a view for explaining the operation of the data storage device according to an embodiment of the present invention.
5 is a view for explaining the operation of the data storage device according to an embodiment of the present invention;
6 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present invention.
7 is a diagram illustrating a configuration of the controller of FIG. 6.
8 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present invention.
9 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present invention.
10 is a diagram illustrating a network system including a data storage device according to an embodiment of the present invention.
11 is a block diagram illustrating a nonvolatile memory device included in a data storage device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a data storage device 10 according to an embodiment of the present invention.

Referring to FIG. 1, the data storage device 10 according to the present embodiment may be implemented in a host device 20 such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, an in-vehicle infotainment system, and the like. Data that is accessed by The data storage device 10 may be called a memory system.

The data storage device 10 may be manufactured as any one of various types of storage devices according to an interface protocol connected with the host device 20. For example, the data storage device 10 may be a solid state drive (SSD), MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro- Secure digital cards in the form of SD, universal storage bus (USB) storage devices, universal flash storage (UFS) devices, storage devices in the form of personal computer memory card international association (PCMCIA) cards, and peripheral component interconnection (PCI) cards Any type of storage device, such as a storage device in the form of a PCI-E (PCI-express) card, a compact flash (CF) card, a smart media card, a memory stick, etc. It can be composed of one.

The data storage device 10 may be manufactured in any one of various types of package types. For example, the data storage device 10 may include a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), and a wafer (WFP). It can be manufactured in any one of a variety of package types such as -level fabricated package (WSP), wafer-level stack package (WSP).

The data storage device 10 may include a nonvolatile memory device 100 and a controller 200.

The nonvolatile memory device 100 may operate as a storage medium of the data storage device 10. The nonvolatile memory device 100 may include a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, and a tunneling magneto-resistive depending on a memory cell. , Magnetic random access memory (MRAM) using TMR films, phase change random access memory (PRAM) using chalcogenide alloys, and resistive RAM using transition metal oxide It may be configured with any one of various types of nonvolatile memory devices such as (resistive random access memory, ReRAM).

In FIG. 1, the data storage device 10 includes one nonvolatile memory device 100, but for convenience of description, the data storage device 10 may include a plurality of nonvolatile memory devices. The present invention may be equally applied to the data storage device 10 including a plurality of nonvolatile memory devices.

The nonvolatile memory device 100 includes a memory cell array (not shown) having a plurality of memory cells respectively disposed in regions where a plurality of bit lines (not shown) and a plurality of word lines (not shown) intersect. Not). The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of pages.

For example, each memory cell of the memory cell array is a single level cell (SLC) that stores one bit of data, and a multi level cell (MLC) that can store two or more bits of data. Can be. The multi-level cell (MLC) may store two bits of data, three bits of data, four bits of data, and the like. In general, a memory cell storing two bits of data is called a multi-level cell (MLC), and a memory cell storing three bits of data is called a triple level cell (TLC). The memory cell to store is called a quadruple level cell (QLC). However, in the present embodiment, for convenience of description, a memory cell storing two to four bits of data will be collectively referred to as a multi-level cell (MLC).

The memory cell array 110 may include at least one of a single level cell SLC and a multi level cell MLC. In addition, the memory cell array 110 may include memory cells having a two-dimensional horizontal structure, or may include memory cells having a three-dimensional vertical structure.

The controller 200 may control overall operations of the data storage device 10 by driving firmware or software loaded in the memory 230. The controller 200 may decode and drive an instruction or algorithm in the form of code such as firmware or software. The controller 200 may be implemented in hardware, or a combination of hardware and software.

The controller 200 may include a host interface 210, a processor 220, a memory 230, and a memory interface 240. Although not shown in FIG. 1, the controller 200 generates parity by encoding write data provided from the host device by error correction code (ECC), and reads the read data read from the nonvolatile memory device 100. The ECC engine may further include an error correction code (ECC) decoding using a parity.

The host interface 210 may interface between the host device 20 and the data storage device 10 in response to the protocol of the host device 20. For example, the host interface 210 may include a universal serial bus (USB), universal flash storage (UFS), multimedia card (MMC), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), and small computer (SCSI). The host device 20 may communicate with any one of a system interface (SAS), serial attached SCSI (SAS), peripheral component interconnection (PCI), and PCI express (PCI-E) protocol.

The processor 220 may be configured of a micro control unit (MCU) and a central processing unit (CPU). The processor 220 may process a request transmitted from the host device 20. In order to process the request sent from the host device 20, the processor 220 drives an instruction or algorithm in the form of code loaded into the memory 230, that is, firmware, and the host interface 210, the memory. Internal function blocks such as the 230 and the memory interface 240 and the nonvolatile memory device 100 may be controlled.

The processor 220 generates control signals for controlling the operation of the nonvolatile memory device 100 based on requests transmitted from the host device 20, and generates the generated control signals through the memory interface 240. It may be provided to the memory device 100.

Memory 230 may be comprised of random access memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory 230 may store firmware driven by the processor 220. In addition, the memory 230 may store data necessary for driving the firmware, for example, metadata. That is, the memory 230 may operate as a working memory of the processor 220.

The memory 230 may include a data buffer for temporarily storing write data to be transmitted from the host device 20 to the nonvolatile memory device 100 or read data to be transmitted from the nonvolatile memory device 100 to the host device 20 ( data buffer). That is, the memory 230 may operate as a buffer memory.

The memory interface 240 controls data communication between the controller 200 and the nonvolatile memory device 100, and specifically controls the nonvolatile memory device 100 under the control of the processor 220. The memory interface 240 may also be called a memory controller. The memory interface 240 may provide control signals to the nonvolatile memory device 100. The control signals may include a command, an address, an operation control signal, and the like for controlling the nonvolatile memory device 100. The memory interface 240 may provide data stored in the data buffer to the nonvolatile memory device 100 or store data transmitted from the nonvolatile memory device 100 in the data buffer.

In addition, the memory interface 240 may execute a flash interface layer (FIL), which is firmware for controlling data communication between the controller 200 and the nonvolatile memory device 100.

2 is a diagram illustrating the memory 230 of FIG. 1.

Referring to FIG. 2, the memory 230 according to the present embodiment queues a command corresponding to a request provided from the first region R1 and the host device 20 in which a flash translation layer (FTL) is stored. The second region R2 used as the command queue CMDQ may be included. However, the memory 230 may be used as a write data buffer in which write data is temporarily stored in addition to the regions shown in FIG. 2, and as a read data buffer in which read data is temporarily stored. It will be apparent to those skilled in the art that there may be included areas used for various purposes, such as areas to be used and areas to be used as map cache buffers where map data is cached.

When the nonvolatile memory device 100 is configured as a flash memory device, the processor 220 controls a unique operation of the nonvolatile memory device 100 and provides a flash translation layer to provide device compatibility to the host device 20. You can run software called (FTL). By driving the flash translation layer (FTL), the host device 20 may recognize and use the data storage device 10 as a general storage device such as a hard disk.

The flash translation layer FTL stored in the first region R1 of the memory 230 may include modules for performing various functions and metadata required for driving each module. The flash translation layer FTL may be stored in a system area (not shown) of the nonvolatile memory device 100, and from the system area of the nonvolatile memory device 100 when the data storage device 10 is powered on. The data may be read and loaded in the first region R1 of the memory 230.

3 is a diagram for describing a data storage area included in a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, the nonvolatile memory device 100 may include a plurality of dies 310a and 310b sharing a channel connected to the controller 200, and each die may be connected to a channel. A plurality of planes 312a and 312b sharing a way 311 may be included, and each plane may include a plurality of pages. Here, the page may mean a storage area of a minimum unit for reading or writing data. In addition, a plurality of page units in which erase operations are collectively performed are called blocks, and a plurality of block units managed as one is called a super block. Accordingly, the data storage area in the nonvolatile memory device may mean a die, a plane, a super block, a block, a page, or the like. However, unless otherwise stated, the data storage area means a page. .

4 is a diagram for describing an operation of a data storage device according to an exemplary embodiment.

Referring to FIG. 4, the flash interface layer 410 requests a read count address. As a specific example, if the flash interface layer 410 determines whether to perform a read operation and reads data stored in a first data storage area among a plurality of data storage areas included in the nonvolatile memory device 100, A read count address (hereinafter, referred to as 'first') that is an address of the memory area 231 in which read count data (hereinafter, 'first read count data') including read counts of a first data storage area in which a read operation is performed is stored Read count address') may be requested to the flash translation layer 430.

In an embodiment, the read counter data may refer to data including a read count in each of the plurality of data storage areas included in the nonvolatile memory device 100. The read counter data may further include an index such as an address of the data storage area.

In one embodiment, the plurality of read count data may form a read counter table. At this time, the read counter data and the read counter table are managed by the flash translation layer 430.

In one embodiment, read count data and read counter tables may be stored in memory 230. For example, the controller 200 may receive read count data from the nonvolatile memory device 100 and cache the received read count data in the memory 230.

In one embodiment, the flash interface layer 410 may send a request to the flash translation layer 430 that includes an index of the data storage area in which the read operation was performed.

The flash translation layer 430 sends the read count address. As a specific example, when there is a read count address request from the flash interface layer 410, the flash translation layer 430 queries the read count address table, and the first read that is a read count address corresponding to the request of the flash interface layer 410. The count address may be sent to the flash interface layer 410.

In an embodiment, the read count address table may include read count address information that is an address of the memory area 231 in which the plurality of read count data are stored.

In one embodiment, the read count address may be mapped to an index of the data storage area. For example, the flash translation layer 430 inquires the read count address corresponding to the index based on the index of the data storage area included in the request of the flash interface layer 410. 410 may be transmitted.

The flash interface layer 410 updates the read count. As a specific example, the flash interface layer 410 may receive a read count address from the flash translation layer 430. The flash interface layer 410 may access the memory area 231 in which read counter data is stored based on the received read count address. In this case, the flash interface layer 410 may update the read count included in the read count data stored in the accessed memory area 231. That is, the flash interface layer 410 may update the read count of the data storage area in which the read operation is performed based on the address of the memory area 231 in which the read count address is stored. This is because although the read count data is information managed by the flash translation layer 430, the flash interface layer 410 reads in a variable reference manner instead of an address reference based on an address of a memory area in which read count data is stored. Since the count data can be accessed, the independence between the flash translation layer 430 and the flash interface layer 410 layer is violated. Accordingly, the present invention seeks to maintain independence between the flash translation layer 430 and the flash interface layer 410 by limiting the access of the flash interface layer 410 to the read count data to an address reference scheme. For example, when the read count address RCA 1 is received from the flash translation layer 430, the flash interface layer 410 may update the read count 1.

5 is a flowchart of a method of operating a data storage device according to an exemplary embodiment.

Referring to FIG. 5, in operation S510, the processor 220 receives a read count table stored in the nonvolatile memory device 100 from the nonvolatile memory device 100, and caches the received read count table in the memory 230. Can be stored.

In step S520, a read operation is performed. In detail, the data storage device 10 may perform a read operation on at least one of the plurality of data storage areas included in the nonvolatile memory device 100 to perform garbage collection, a read command of a host, and the like. . In this case, the nonvolatile memory device 100 may inform the flash interface layer 410 of whether to perform a read operation including an index of a data storage region in which the read operation is performed.

In step S530, a read count address is requested. The flash interface layer 410 may determine whether a read operation is performed on the data storage area. When the flash interface layer 410 determines that a read operation is performed on the data storage area, the read count address, which is an address of the memory area 231, in which the read count data including the read count of the data storage area in which the read operation is performed is stored, is read. To the flash translation layer 430. In this case, the flash translation layer 430 may query the read count address table and transmit the read count address requested from the flash interface layer 410 to the flash interface layer 410.

In step S540, the read count is updated. As a specific example, the read interface address may be received from the flash translation layer 430 by the flash interface layer 410. The flash interface layer 410 may access the memory area 231 in which read count data is stored based on the received read count address. The flash interface layer 410 may update the read counter included in the read count data stored in the accessed memory area 231.

In step S550, the read counter is monitored. As a specific example, the flash translation layer 430 may monitor whether the data having a read count value equal to or greater than a predetermined threshold number of read count data included in the read count table. In this case, the flash translation layer 430 may determine whether to perform a read reclaim operation on a data storage area having a read count value greater than or equal to a threshold number.

In one embodiment, if the read count value is less than the threshold number of times, the flash translation layer 430 may perform step S520 again.

In step S560, read reclaim is performed. As a specific example, the flash translation layer 430 may control the nonvolatile memory device 100 to perform read reclaim for a data storage area having a read count greater than or equal to a threshold number of times.

6 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 6, the data processing system 2000 may include a host device 2100 and a solid state drive 2200 (hereinafter, referred to as an SSD).

The SSD 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260. .

The controller 2210 may control overall operations of the SSD 2200.

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223n. In addition, the buffer memory device 2220 may temporarily store data read from the nonvolatile memory devices 2231 to 223n. Data temporarily stored in the buffer memory device 2220 may be transmitted to the host device 2100 or the nonvolatile memory devices 2231 to 223n under the control of the controller 2210.

The nonvolatile memory devices 2231 to 223n may be used as a storage medium of the SSD 2200. Each of the nonvolatile memory devices 2231 to 223n may be connected to the controller 2210 through a plurality of channels CH1 to CHn. One or more nonvolatile memory devices may be connected to one channel. Nonvolatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 2240 may provide the power PWR input through the power connector 2260 to the inside of the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power supply 2241 may supply power so that the SSD 2200 may be normally terminated when a sudden power off occurs. The auxiliary power supply 2241 may include large capacity capacitors capable of charging the power PWR.

The controller 2210 may exchange a signal SGL with the host device 2100 through the signal connector 2250. Here, the signal SGL may include a command, an address, data, and the like. The signal connector 2250 may be configured with various types of connectors according to the interface method of the host device 2100 and the SSD 2200.

FIG. 7 is a diagram illustrating a configuration of the controller of FIG. 6. Referring to FIG. 7, the controller 2210 includes a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215. can do.

The host interface unit 2211 may interface the host device 2100 and the SSD 2200 according to the protocol of the host device 2100. For example, the host interface unit 2211 may include a secure digital, a universal serial bus (USB), a multi-media card (MMC), an embedded MMC (eMMC), a personal computer memory card international association (PCMCIA), Parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), universal flash (UFS) communication) with the host device 2100 through any one of the protocols. In addition, the host interface unit 2211 may perform a disk emulation function that enables the host device 2100 to recognize the SSD 2200 as a general data storage device, for example, a hard disk drive (HDD). Can be.

The control unit 2212 may analyze and process the signal SGL input from the host device 2100. The control unit 2212 may control the operation of the internal functional blocks according to firmware or software for driving the SSD 2200. The random access memory 2213 can be used as an operating memory for driving such firmware or software.

The error correction code (ECC) unit 2214 may generate parity data of data to be transmitted to the nonvolatile memory devices 2231 to 223n. The generated parity data may be stored in the nonvolatile memory devices 2231 to 223n together with the data. The error correction code (ECC) unit 2214 may detect an error of data read from the nonvolatile memory devices 2231 to 223n based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit 2214 may correct the detected error.

The memory interface unit 2215 may provide control signals such as a command and an address to the nonvolatile memory devices 2231 to 223n under the control of the control unit 2212. The memory interface unit 2215 may exchange data with the nonvolatile memory devices 2231 to 223n under the control of the control unit 2212. For example, the memory interface unit 2215 may provide data stored in the buffer memory device 2220 to the nonvolatile memory devices 2231 to 223n or buffer data read from the nonvolatile memory devices 2231 to 223n. It may be provided to the memory device 2220.

8 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. Referring to FIG. 8, the data processing system 3000 may include a host device 3100 and a data storage device 3200.

The host device 3100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 3100 may include internal functional blocks for performing a function of the host device.

The host device 3100 may include a connection terminal 3110 such as a socket, a slot, or a connector. The data storage device 3200 may be mounted on the connection terminal 3110.

The data storage device 3200 may be configured in the form of a substrate such as a printed circuit board. The data storage device 3200 may be called a memory module or a memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, nonvolatile memory devices 3231 to 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250. .

The controller 3210 may control overall operations of the data storage device 3200. The controller 3210 may be configured in the same manner as the controller 2210 illustrated in FIG. 7.

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 to 3232. In addition, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3231 to 3232. The data temporarily stored in the buffer memory device 3220 may be transmitted to the host device 3100 or the nonvolatile memory devices 3231 to 3232 under the control of the controller 3210.

The nonvolatile memory devices 3231 to 3232 may be used as a storage medium of the data storage device 3200.

The PMIC 3240 may provide power input through the connection terminal 3250 to the data storage device 3200. The PMIC 3240 may manage power of the data storage device 3200 under the control of the controller 3210.

The connection terminal 3250 may be connected to the connection terminal 3110 of the host device. Signals such as commands, addresses, data, and the like may be transferred between the host device 3100 and the data storage device 3200 through the access terminal 3250. The access terminal 3250 may be configured in various forms according to the interface method of the host device 3100 and the data storage device 3200. The connection terminal 3250 may be disposed on either side of the data storage device 3200.

9 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. Referring to FIG. 9, the data processing system 4000 may include a host device 4100 and a data storage device 4200.

The host device 4100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 4100 may include internal functional blocks for performing a function of the host device.

The data storage device 4200 may be configured in the form of a surface mount package. The data storage device 4200 may be mounted to the host device 4100 through a solder ball 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a nonvolatile memory device 4230.

The controller 4210 may control overall operations of the data storage device 4200. The controller 4210 may be configured in the same manner as the controller 2210 illustrated in FIG. 7.

The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. In addition, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory devices 4230. Data temporarily stored in the buffer memory device 4220 may be transmitted to the host device 4100 or the nonvolatile memory device 4230 under the control of the controller 4210.

The nonvolatile memory device 4230 may be used as a storage medium of the data storage device 4200.

10 is a diagram illustrating a network system 5000 including a data storage device according to an embodiment of the present invention. Referring to FIG. 10, the network system 5000 may include a server system 5300 and a plurality of client systems 5410 to 5430 connected through the network 5500.

The server system 5300 may service data in response to a request of the plurality of client systems 5410 to 5430. For example, the server system 5300 may store data provided from the plurality of client systems 5410 to 5430. As another example, the server system 5300 may provide data to the plurality of client systems 5410-5430.

The server system 5300 may include a host device 5100 and a data storage device 5200. The data storage device 5200 may include a data storage device 10 of FIG. 1, a data storage device 2200 of FIG. 6, a data storage device 3200 of FIG. 8, and a data storage device 4200 of FIG. 9. have.

11 is a block diagram illustrating a nonvolatile memory device included in a data storage device according to an embodiment of the present invention. Referring to FIG. 11, the nonvolatile memory device 100 includes a memory cell array 110, a row decoder 120, a column decoder 130, a data read / write block 140, a voltage generator 150, and control logic. 160 may be included.

The memory cell array 110 may include memory cells MC arranged in regions where word lines WL1 to WLm and bit lines BL1 to BLn cross each other.

The row decoder 120 may be connected to the memory cell array 110 through the word lines WL1 ˜WLm. The row decoder 120 may operate under the control of the control logic 160. The row decoder 120 may decode an address provided from an external device (not shown). The row decoder 120 may select and drive word lines WL1 ˜WLm based on the decoding result. In exemplary embodiments, the row decoder 120 may provide a word line voltage provided from the voltage generator 150 to the word lines WL1 ˜WLm.

The data read / write block 140 may be connected to the memory cell array 110 through bit lines BL1 to BLn. The data read / write block 140 may include read / write circuits RW1 to RWn corresponding to each of the bit lines BL1 to BLn. The data read / write block 140 may operate under the control of the control logic 160. The data read / write block 140 may operate as a write driver or as a sense amplifier depending on the mode of operation. For example, the data read / write block 140 may operate as a write driver that stores data provided from an external device in the memory cell array 110 during a write operation. As another example, the data read / write block 140 may operate as a sense amplifier that reads data from the memory cell array 110 during a read operation.

The column decoder 130 may operate under the control of the control logic 160. The column decoder 130 may decode an address provided from an external device. The column decoder 130 may read / write circuits RW1 to RWn and data I / O lines (or data I / O) of the data read / write block 140 corresponding to each of the bit lines BL1 to BLn based on the decoding result. Buffer).

The voltage generator 150 may generate a voltage used for internal operation of the nonvolatile memory device 100. Voltages generated by the voltage generator 150 may be applied to the memory cells of the memory cell array 110. For example, the program voltage generated during the program operation may be applied to the word lines of the memory cells in which the program operation is to be performed. As another example, the erase voltage generated during the erase operation may be applied to the well-region of the memory cells in which the erase operation is to be performed. As another example, the read voltage generated during the read operation may be applied to the word lines of the memory cells in which the read operation is performed.

The control logic 160 may control overall operations of the nonvolatile memory device 100 based on a control signal provided from an external device. For example, the control logic 160 may control operations of the nonvolatile memory device 100, such as read, write, and erase operations of the nonvolatile memory device 100.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above are exemplary in all respects and are not intended to be limiting. You must understand. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

10: data storage device 100: nonvolatile memory device
200: controller 210: host interface
220: processor 230: memory
240: memory interface

Claims (13)

A controller for controlling a nonvolatile memory device,
A read count table including a plurality of read count data, each read count data including read counts for one data storage area;
A read count address table including a read count address which is an address of a memory area in which the read count data is stored;
A flash translation layer that controls an operation of a data storage device and manages the read count table and the read count address table; And
A flash interface layer that controls data communication between the flash change layer and a nonvolatile memory device, and updates the read count based on the read count address when a read operation of the plurality of data storage areas occurs.
Controller comprising. The method of claim 1,
The flash interface layer,
When a read operation occurs in the first data storage area, the flash conversion of the read count address (hereinafter referred to as 'first read count address') of the read count data (hereinafter, referred to as first read count data) for the first data storage area is performed. Request to the tier,
And when the first read count address is received from the flash changed layer, inquiring a memory area corresponding to the first read count address, and updating a read count included in the first read count data. The method of claim 2,
The flash conversion layer,
When the first read count address request is received from the flash interface layer,
And the flash interface layer transmits the first read count address included in the read count address table. The method of claim 1,
A memory for storing at least one of the read count table, read count address table, flash translation layer and flash interface layer;
A processor executing the flash translation layer and
A host interface executing the flash interface layer
Controller comprising a. The method of claim 1,
The data storage area,
And any one of a data page, a memory block, a plane, and a die. The method of claim 1,
The read count data is,
And the index of the read count and the data storage area corresponding to the read count. The method of claim 1,
The flash conversion layer,
And control the nonvolatile memory device to perform a read reclaim operation on a data storage area corresponding to read counter data including a read count of a threshold number or more. A method of operating a controller including a flash translation layer and a flash interface layer to control an operation of a nonvolatile memory device,
In the flash interface layer, read count data (hereinafter referred to as 'first read count data') including read counts of a first data storage area in which a read operation is performed is performed among a plurality of data storage areas included in the nonvolatile memory device. Requesting the flash conversion layer for a read count address (hereinafter referred to as a 'first read count address') that is an address of a stored memory area;
Sending, by the flash translation layer, the first read count address to the flash interface layer at the request of the flash translation layer; And
The flash interface layer queries the memory area in which the first read count data is stored based on the first read count address received from the flash translation layer to update the read count included in the first read count data. step
Controller operation method comprising a. The method of claim 8,
And identifying, by the flash interface layer, occurrence of a read operation for the first data storage area. The method of claim 8,
The transmitting of the first read count address to the flash interface layer may include:
When the first read count address request is received from the flash interface layer, a read count address table of a plurality of read count data corresponding to the plurality of data storage areas is queried, and the first read count address is referred to as the flash interface. Controller operation method, characterized in that the transmission to the layer. The method of claim 8,
The data storage area,
Any one of a data page, a memory block, a plane, and a die. The method of claim 8,
The read count data is,
And an index of the read count and a data storage area corresponding to the read count. The method of claim 1,
And controlling, by the flash translation layer, the nonvolatile memory device to perform a read reclaim operation on a data storage area corresponding to read counter data including a read count of a threshold number of times or more.

Images