KR20190014984A - Display device and sensing method for sensing bonding resistance thereof - Google Patents

Abstract

The present invention relates to a display device capable of checking whether the bonding is bad by sensing bonding resistance of a driving circuit unit using a driving IC with a sensing unit, and a method for sensing bonding resistance thereof. According to one embodiment of the present invention, the method comprises the following steps. An input voltage is supplied to a bonding resistance sensing path. Next, the input voltage goes by way of the bonding resistance sensing path and generates a voltage reflecting bonding resistance of a plurality of bonding pads at a sensing node between the bonding resistance sensing path and reference resistance. Next, an ADC embedded in the driving IC receives the voltage reflecting the bonding resistance from the sensing node, converts the voltage into sensing data, and output the sensing data. Then, it is determined whether the bonding of the driving circuit unit is bad using the sensing data.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of sensing a bonding resistance thereof,

The present invention relates to a display device capable of sensing a bonding resistance of a driving circuit portion using a driving circuit having a sensing portion, and a bonding resistance sensing method for the same.

2. Description of the Related Art Recently, display devices using digital data to display images include liquid crystal displays (LCDs) using liquid crystals, organic light emitting diodes (OLED) displays using organic light emitting diodes, And an electrophoretic display (EPD).

The display device includes a panel for displaying an image, a drive circuit for driving the panel, and a timing controller for controlling the drive circuit. The driving circuit is provided in the form of COF (Chip On Film) in which ICs (Integrated Circuits) are individually mounted on a circuit film.

Through the bonding process, one pad portion of each COF is bonded and connected to the pad portion of the panel through an ACF (Anisotropic Conductive Film), and the other pad portion is bonded to and connected to the pad portion of the PCB (Printed Circuit Board) through the ACF. After the bonding process, the bonding resistance of each COF is measured through the inspection process to check whether the bonding of the COF is bad or not.

To this end, a bonding pad used for measuring a bonding resistance is provided on the panel, the PCB, and each COF, and a test pad connected to the bonding pad for bonding resistance measurement is provided on the PCB. In the conventional bonding resistance measuring method, a resistance measuring device is connected to a test pad to measure a bonding resistance of the bonding pad, and it is determined whether or not the bonding is bad according to the measurement result.

However, in the conventional bonding resistance measuring method, since the bonding resistance of each COF is individually measured by using the resistance measuring device, the inspection time of the bonding resistance is increased to increase the process tact time, .

In addition, the conventional bonding resistance measuring method has a problem that it is impossible to apply a bonding method unless the display device is decapsulated after the product is shipped, and it is difficult to confirm the progressive connection failure of the driving circuit which is generated by increasing the bonding resistance progressively .

The present invention provides a display device and a bonding resistance sensing method thereof that can confirm whether or not a bonding defect is caused by sensing a bonding resistance of a driving circuit portion using a driving IC having a sensing portion.

A display device according to an embodiment includes a driving IC mounted on a circuit film, a driving circuit portion bonded between the panel and the PCB, a first bonding portion bonding and connecting the PCB and the circuit film, And a bonding resistance sensing path in which a plurality of bonding pads located in a second bonding section for bonding and connecting the film are connected in series. When the driving IC is in the first sensing mode, the driving IC senses a signal reflecting the characteristics of each sub-pixel through the panel, and outputs the first sensing data through the ADC. The driving IC senses a signal reflecting a bonding resistance of a plurality of bonding pads through a bonding resistance sensing path and outputs second sensing data through the ADC when the sensing mode is the second sensing mode.

The timing controller controls the driving IC to operate in the first and second sensing modes, and determines whether or not the bonding of the driving circuit unit is defective by using the second sensing data, and outputs the result.

The driving circuit further includes a reference resistor connected in series between the bonding resistance sensing path and the ground and a switch connecting the sensing node between the bonding resistance sensing path and the reference resistor and the input terminal of the ADC when the sensing mode is in the second sensing mode.

A bonding resistance sensing path according to one embodiment includes a first bonding pad connected in series with a supply line of the input voltage and bonded between the PCB and the circuit film, a second bonding pad connected in series with the first bonding pad, A third bonding pad connected in series with the second bonding pad and arranged in parallel with the second bonding pad, the third bonding pad being bonded between the panel and the circuit film, and a second bonding pad connected in series with the third bonding pad, A fourth bonding pad disposed in parallel with the pad and bonded between the PCB and the circuit film, a fourth bonding pad connected in series with the fourth bonding pad and disposed in parallel with the fourth bonding pad, Pad. Each of the first through fifth bonding pads includes a pair of pads bonded to and connected to the circuit film and the PCB or the panel by the anisotropic conductive film.

The first and second bonding pads are connected in series through a first connection line provided on the circuit film. The second and third bonding pads are connected in series through a second connection line provided on the panel. The third and fourth bonding pads are serially connected to the circuit film through a third connection line arranged in parallel with the first connection line. The fourth and fifth bonding pads are connected in series through a fourth connection line provided on the PCB. The bonding resistance sensing path further includes a fifth connection line which is provided on the circuit film and connects the fifth bonding pad and the input terminal of the driving IC.

The driving circuit portion further includes a plurality of power wiring lines for supplying a driving voltage from the PCB to the panel through the circuit film, and the fourth and fifth bonding pads are spaced apart from each other with a plurality of power wiring lines interposed therebetween. The fifth bonding pad may be disposed at one side of the circuit film or at a central portion of the circuit film adjacent to the plurality of power supply wirings. The bonding resistance sensing path may be disposed on one side of the driving circuit portion or on both sides of the driving circuit portion.

According to an embodiment of the present invention, there is provided a method of sensing a bonding resistance of a display device, the method comprising: supplying an input voltage to the bonding resistance sensing path; sensing an input voltage at a sensing node between the bonding resistance sensing path and the reference resistance via a bonding resistance sensing path; A step of generating a voltage reflecting a bonding resistance of a plurality of bonding pads, converting the sensing resistor to a sensing voltage, receiving a voltage reflecting the bonding resistance from the sensing node, And judging whether or not the bonding of the circuit part is defective.

In one embodiment of the present invention, the bonding resistance of the driving circuit portion can be sensed by using the ADC incorporated in the driving IC, and it is possible to easily check whether the bonding of the driving circuit portion is bad or not by using the sensing result, .

In one embodiment of the present invention, since the inspection time for inspecting the bonding resistance after the bonding process of the driving circuit portion can be reduced, the process tact time can be reduced and the measurement error can be reduced.

Since the advance bonding failure can be detected by sensing the bonding resistance of the driving circuit portion by using the ADC incorporated in the driving IC even after shipment of the product according to the embodiment of the present invention, .

1 is a block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention.
2 is a view illustrating a bonding structure of a driving circuit portion in a display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram illustrating a bonding resistance sensing unit according to an embodiment of the present invention.
4 is a view illustrating various ways of sensing a bonding resistance of a driving circuit according to an exemplary embodiment of the present invention.
5 is an equivalent circuit diagram showing a part of a pixel circuit and a driving circuit according to an embodiment of the present invention.
6 is a flowchart illustrating a bonding resistance sensing method of an OLED display according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an IC package for bonding resistance sensing according to an embodiment of the present invention.

Referring to FIG. 1, an OLED display according to an embodiment includes a panel 100, a gate driver 200, a data driver 300, a timing controller 400, a memory 500, a power source 600, and the like. do.

The panel 100 displays an image through a pixel array in which sub-pixels SP are arranged in a matrix form. The basic pixel can be composed of at least three subpixels capable of white representation by color mixing among white (W), red (R), green (G) and blue (B) subpixels. For example, the basic pixel may be subpixels of R / G / B combination, subpixels of W / R / G combination, subpixels of B / W / R combination, subpixels of G / Or a combination of W / R / G / B combinations of subpixels.

The power supply unit 600 generates various driving voltages required for the display controller and the timing controller 400, the gate driver 200, the data driver 300, the panel 100, and the like using the input voltage and outputs the generated driving voltages. For example, the power supply unit 600 may include a driving voltage of a digital circuit supplied to the data driver 300 and the timing controller 400, a driving voltage of an analog circuit supplied to the data driver 300, (Gate high voltage) and a gate-off voltage (gate low voltage) to be supplied to the gate electrode of the transistor. The power supply unit 600 generates a plurality of driving voltages EVDD and EVSS and a reference voltage required for driving the panel 100 and supplies the generated driving voltages EVDD and EVSS to the panel 100 through the data driver 300.

The timing controller 400 receives image data and basic timing control signals from an external system. The system may be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet or a mobile phone. The basic timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 sets the driving timings of the data driver 300 and the gate driver 200 using the basic timing control signals supplied from the outside and the timing setting information (start timing, pulse width, etc.) stored in the internal registers And generates and supplies data control signals and gate control signals to be controlled.

The timing controller 400 compensates the image data to be supplied to each subpixel SP using the compensation value stored in the memory 500 and supplies the compensated image data to the data driver 300. [ The timing controller 400 may further perform various image processing for degradation compensation of OLED elements, power consumption reduction, and the like.

The timing controller 400 receives the sensing command from the system and controls the display device to operate in a pixel sensing mode for sensing the characteristics of each subpixel or controls the data driver 300 to perform bonding resistance sensing Mode can be controlled.

When the pixel sensing command is supplied from the system, the timing controller 400 can control the gate driver 200, the data driver 300, the panel 100, etc. to operate in the pixel sensing mode. The timing controller 400 senses the characteristics (Vth of the driving TFT, mobility, Vth of the OLED, etc.) of each subpixel of the panel 100 through the data driver 300, Lt; RTI ID = 0.0 > subpixel < / RTI >

When the bonding resistance sensing command is supplied from the system, the timing controller 400 can control the data driver 300 to operate in the bonding resistance sensing mode, and a description thereof will be described later.

The gate driver 200 receives a gate control signal from the timing controller 400 and drives a plurality of gate lines of the panel 100. The gate driver 200 supplies a pulse of the gate-on voltage to the corresponding gate line in the driving period of each gate line, and supplies a gate-off voltage in the non-driving period. The gate driver 200 may be disposed on both sides of the panel 100 and the gate signal may be simultaneously supplied from both sides of each gate line to reduce the delay of the gate signal.

 The gate driver 200 includes a plurality of gate ICs (Integrated Circuits) connected to one side or both sides of the panel 100 to divide and drive the gate lines. The gate ICs are individually mounted on the circuit film and are provided in the form of TCP (Tape Carrier Package), COF (Chip On Film), and bonded to the panel 100 through an ACF (Tape Automatic Bonding) Can be connected. Alternatively, the gate driver 200 may be formed in a GIP (Gate In Panel) type which is formed directly in the non-display area of the substrate together with the TFT array of the pixel array of the panel 100 and embedded in the panel 100. [

The data driver 300 converts the pixel data supplied from the timing controller 400 into an analog data voltage and supplies the data voltage to the panel 100 using the data control signal supplied from the timing controller 400. [ The data driver 300 converts the digital data into the analog data voltage using the gradation-specific gamma voltage supplied from the gamma voltage generator.

The data driver 300 may operate in a pixel sensing mode and a bonding resistance sensing mode under the control of the timing controller 400.

The data driver 300 converts the sensing data supplied from the timing controller 400 into a sensing data voltage and supplies the data voltage to each sub pixel through a data line, Thereby driving each sub-pixel. The data driver 300 senses the pixel current representing the driving characteristics (Vth of the driving TFT, mobility, Vth of the OLED, etc.) of the driven subpixel SP as a voltage through the reference line, Converter to provide the timing data to the timing controller 400. The timing controller 400 updates the compensation value of each subpixel stored in the memory 500 using the sensing result supplied from the data driver 300.

The data driver 300 includes a plurality of data ICs 350 (FIG. 2) connected to one side or both sides of the panel 100 to divide and drive the data lines. 2, each of the data ICs 350 is individually mounted on the circuit film 360 and is provided as a driving circuit portion 370 of TCP or COF type. Each driving circuit portion 370 is connected to the panel 100 and the PCB 700 by a TAB method.

The data driver 300 or the respective data ICs 350 may be configured such that the input voltage Vin is applied to the bonding resistance sensing path 10 of the driving circuit portion 370 in the bonding resistance sensing mode under the control of the timing controller 400 The voltage reflecting the bonding resistance is supplied to the timing controller 400 via the ADC, and the voltage is converted into sensing data and supplied to the timing controller 400. The bonding resistance sensing path 10 of each driving circuit unit 370 includes a plurality of bonding pads 12 and 13 to which the driving circuit unit 370 and the PCB 700 are bonded, a driving circuit unit 370, A plurality of bonded bonding pads 11, 14, and 15 are connected in series. The bonding resistance sensing path 10 may be provided on one side of the driving circuit unit 370 or on both sides of the driving circuit unit 370.

Since the bonding state of the driving circuit portion 370 is the best in the center bonding state and the bonding state in the both side portions is relatively poor, bonding of the bonding resistive sensing path 10, which is located on one side or both sides of the driving circuit portion 370, By sensing the resistance, it is possible to judge whether or not the driving circuit 370 is defective in bonding.

The timing controller 400 determines whether or not the respective driving circuit portions 370 are defective in bonding by using the sensing data supplied from the respective data ICs 350. The timing controller 400 outputs the determination result of the bonding failure to the outside so that the operator can repair the bonding failure of each driving circuit unit 370 when the bonding is defective. If the voltage sensing value of the bonding resistor is less than the preset reference value, the timing controller 400 determines that the bonding resistance is increased because the bonding resistance is increased. If the voltage sensing value of the bonding resistor is higher than the reference value, .

FIG. 2 is a schematic view showing a bonding structure of each driving circuit unit 370 according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram showing a bonding resistance sensing apparatus of each driving circuit unit 370.

2, in each driving circuit portion 370 including the data IC 350 mounted on the circuit film 360, the first bonding portion 362 may be a whole or a part of the bonding portion 710 of the PCB 700 It is bonded by ACF in some areas. The plurality of bonding pads located in the first bonding portion 362 are individually connected to the plurality of bonding pads located in the bonding portion 710 of the PCB 700 through the conductive particles included in the ACF.

The second bonding portion 364 facing the first bonding portion 362 in the first direction Y in the driving circuit portion 370 is electrically connected to the bonding portion 110 of the panel 100 by ACF Bonding. The plurality of bonding pads located in the second bonding portion 364 are individually connected to the plurality of bonding pads located in the bonding portion 110 of the panel 100 through the conductive particles included in the ACF.

The bonding resistance sensing path 10 of each driving circuit portion 370 includes a first bonding pad 11 bonded between the circuit film 360 and the PCB 700 and a second bonding pad 11 between the circuit film 360 and the panel 100 Second and third bonding pads 12 and 13 bonded together and fourth and fifth bonding pads 11, 14 and 15 bonded between the circuit film 360 and the PCB 700 are connected in series, .

The first bonding pad 11 receives the input voltage Vin from the power supply unit 600. The first bonding pad 11 and the second bonding pad 12 are connected in series through a connection line 21 provided in the circuit film 360. [ The second and third bonding pads 12 and 13 are connected in series through a connection line 22 provided in the panel 100. [ The third and fourth bonding pads 13 and 14 are connected in series through a connection line 23 provided on the circuit film 360. [ The fourth and fifth bonding pads 14 and 15 are connected in series through a connection line 24 provided on the PCB 700. The fifth bonding pad 15 is connected in series with the input terminal of the data IC 350 through a connection line 25 provided in the circuit film 360.

Referring to FIG. 2, the first bonding pad 11 includes a pair of pads 11-1 and 11-2 provided on the PCB 700 and the circuit film 360, facing each other, Structure. The fourth bonding pad 14 adjacent to the first bonding pad 11 also has a pair of pads 14-1 and 14-2 provided on the PCB 700 and the circuit film 360 facing each other, And a connected structure. The second bonding pad 15 also has a structure in which a pair of pads respectively provided on the PCB 700 and the circuit film 360 are bonded and connected by the ACF. Likewise, each of the second and third bonding pads 12 and 13 has a structure in which each pair of pads provided on the panel 100 and the circuit film 360 are bonded and connected by ACF.

3, the first to fifth bonding pads 11 to 15 may be represented by a series structure of first to fifth bonding resistors R1 to R5 connected to a supply line of the input voltage Vin . The sum R2 + R3 of the second and third bonding resistors R2 and R3 corresponding to the second and third bonding pads 12 and 13 is equal to the sum of the bonding resistance between the driver circuit portion 370 and the PCB 700 Ra). The sum (R1 + R4 + R5) of the first, fourth and fifth bonding resistors R1, R4 and R5 corresponding to the first, fourth and fifth bonding pads 11, And a bonding resistance Rb between the panel 100 and the panel 100. [ The bonding resistance sensing path 10 is a structure in which a bonding resistor Ra between the driving circuit portion 370 and the PCB 700 and a bonding resistor Rb between the driving circuit portion 370 and the panel 100 are connected in series .

A reference resistor Rf is connected in series between the series structure of the first to fifth bonding resistors R1 to R5 and the ground GND and a sensing node Rf between the fifth bonding resistor R5 and the reference resistor Rf Ns are connected to the input terminal of the ADC 310 via the switch SW. The reference resistor Rf and the switch SW are embedded in the data IC 350 together with the ADC 310. [ The reference resistor Rf may be located on the circuit film 360. [

The sensing node Ns is connected to the bonding resistors R1 to R5 of the first to fifth bonding pads 11 to 15 because the input voltage Vin is 1 to 2 V through the bonding resistors R1 to R5, ), That is, the sensing voltage by the bonding resistance. The ADC 320 receives the sensing voltage generated from the sensing node Ns through the switch SW, converts the sensing voltage into sensing data, and provides the sensed data to the timing controller 400. Under the control of the timing controller 400, the switch SW is turned on in the bonding resistance sensing mode.

4 is a view illustrating various ways of sensing a bonding resistance of a driving circuit according to an exemplary embodiment of the present invention.

4 (a), first and second bonding resistance sensing paths (not shown) are formed on both sides of the driving circuit portion 370, which are bonded between the panel 100 and the substrate 700, 10A, and 10B, respectively. The ADC incorporated in the data IC 350 can be connected to the first and second bonding resistance sensing paths 10A and 10B to receive sensing voltages by the bonding resistors of the respective paths, The sensing data for each of the resistance sensing paths 10A and 10B can be provided to the timing controller 400. [

4B and 4C, first and second driving voltages EVDD and EVSS are applied to the panel 100 from the PCB 700 on both sides of the driving circuit unit 370 in the second direction X. [ A plurality of power supply wirings 30 and 32 for supplying a plurality of power supply wirings 30 and 32 may be located.

4 (a), when a plurality of power supply lines 30 and 32 are positioned between the bonding resistance sensing path 10 and the data IC 350 as shown in FIG. 4 (b), the fifth bonding pad 15 and the data IC 350 must be formed on different layers of the circuit film 360 and the power supply lines 30 and 32 and intersect with each other.

The fifth bonding pads 15A and 15B and the data IC 350 are connected to each other by changing the positions of the fifth bonding pads 15A and 15B in the driving circuit unit 370 as shown in Figs. 4 (b) and 4 (c) The connection lines 25A and 25B may be formed on the same layer without crossing the power supply lines 30 and 32. [

4B, the fifth bonding pad 15A is spaced apart from the fourth bonding pad 14 with the power supply wires 30 interposed therebetween, and is electrically connected to the fourth bonding pad 14 via a connection line 24 provided on the PCB 700 And the fourth and fifth bonding pads 14 and 15A are connected.

4C, the fifth bonding pad 15B may be located at a central portion of the driving circuit portion 370 and connected to the fourth and fifth bonding pads (not shown) through a connection line 24 provided on the PCB 700 14 and 15A are connected. All. In this case, the ADC 310 (FIG. 3) incorporated in the data IC 350 can sense the bonding resistance at the center as well as the one side or both sides of the driving circuit 370 by sensing the sensing voltage.

5 is an equivalent circuit diagram showing a part of a pixel circuit and a driving circuit according to an embodiment of the present invention.

5, the data IC 350 connected to the panel 100 senses the characteristics of each subpixel SP using the built-in ADC 310 and senses the bonding resistance of the driving circuit 370 do.

The ADC 310 controls the sensing node Ns between the bonding resistance sensing path 10 and the reference resistance Rf of the driving circuit unit 370 and the sensing node Ns between the sensing resistor Rs and the sensing resistor Rf, SW to sense the sensing voltage by the bonding resistance. The bonding resistance Ra between the driving circuit portion 370 and the PCB 700 and the bonding resistance Rb between the driving circuit portion 370 and the panel 100 in the bonding resistance sensing path 10 are the same as those of the input voltage Vin Connected in series between the supply line and the sensing node (Ns).

In the pixel sensing mode under the control of the timing controller 400, the ADC 310 can sense the characteristics of each subpixel SP through the sampling switch SAM and the reference line REF.

Each subpixel SP located in the panel 100 is connected between a high potential driving voltage (first driving voltage: EVDD) line PW1 and a low potential driving voltage (second driving voltage: EVSS) line PW2 A pixel circuit including at least a first and a second switching TFTs ST1 and ST2 and a driving TFT DT and a storage capacitor Cst to independently drive the OLED 10 Respectively. On the other hand, the pixel circuit may have various configurations different from the configuration of FIG.

The switching TFTs ST1 and ST2 and the driving TFT DT may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, an organic TFT or the like have.

The OLED 10 has an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the EVSS line PW2, and an organic light emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode may be a common electrode shared by all the subpixels. When a driving current is supplied from the driving TFT DT, electrons from the cathode are injected into the organic light-emitting layer, holes from the anode are injected into the organic light-emitting layer, and electrons and holes recombine in the organic light- By emitting phosphors, light of brightness proportional to the current value of the drive current is generated.

The first switching TFT ST1 is driven by the first gate signal SCAN supplied from the gate driver 200 to the first gate line GLn1 and supplied from the data IC 350 to the data line DL And supplies the data voltage Vdata to the gate node N1 of the driving TFT DT.

The second switching TFT ST2 is driven by the second gate signal SENSE supplied from the gate driver 200 to the second gate line GLn2 and supplied from the data IC 350 to the reference line REF And supplies the reference voltage Vref to the source node N2 of the driving TFT DT. Further, when each sub-pixel SP is driven in the sensing mode, the second switching TFT ST2 outputs the current supplied from the driving TFT DT to the floating reference line REF.

The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT is connected to the gate node N1 through the first and second switching TFTs ST1 and ST2 turned on during the scan period The difference voltage between the data voltage Vdata and the reference voltage Vref supplied to the first and second switching TFTs N1 and N2 is charged to the driving voltage Vgs of the driving TFT DT, ST1, and ST2 are turned off.

The driving TFT DT controls the current supplied from the EVDD line PW1 according to the driving voltage Vgs supplied from the storage capacitor Cst to supply the driving current determined by the driving voltage Vgs to the OLED 10 Thereby causing the OLED 10 to emit light.

During the scan period of the first and second gate signals SCAN and SENSE, the driver TFT DT supplies data from the data driver 300 to the data line DL and the first switching TFT < RTI ID = 0.0 > And supplies the sensing data voltage Vdata supplied through the first switching TFT ST1 and the reference voltage Vref supplied through the reference line REF and the second switching TFT ST2 to drive the OLED 10 can do. The pixel current reflecting the driving characteristic (Vth, mobility) of the driving TFT DT or the degradation of the OLED 10 is charged to the line capacitor of the reference line REF through the second switching TFT ST2. The ADC 310 receives the sensing voltage from the reference line REF through the sampling switch SAM, converts the sensing voltage into sensing data of each subpixel SP, and outputs the sensed data.

As such, the data IC 350 according to one embodiment utilizes the built-in ADC 310 to sense the pixel characteristics, and is connected to the bonding resistance supplied through the bonding resistance sensing path 10 of the driver circuit portion 370 It is possible to sense the sensing voltage by the timing controller 400 and provide the sensing result to the timing controller 400 as sensing data.

6 is a flowchart illustrating a bonding resistance sensing method of a driving circuit unit according to an embodiment of the present invention.

The timing controller 400 controls the data IC 350 to operate in a bonding resistance sensing mode of the driving circuit unit 370. The bonding resistance sensing mode can be checked not only before the product shipment but also after the product shipment to detect progressive bonding defects.

The input voltage Vin is supplied from the power supply unit 500 to the bonding resistance sensing path 10 of the driving circuit unit 370 (S602).

The ADC 310 senses the sensing voltage by the bonding resistance generated at the sensing node Ns via the switch SW via the bonding resistance sensing path 10 of the driving circuit unit 370 at step S604. The ADC 320 receives the sensing voltage through the switch SW, converts the sensing voltage into sensing data, and provides the sensed data to the timing controller 400.

The timing controller 400 determines whether or not each driving circuit 370 is defective in bonding using the sensing data supplied from each data IC 350 (S606, S608, and S6010). If the voltage sensing value by the bonding resistor is equal to or greater than the reference value (S606; Y), the timing controller 400 determines that the bonding resistance is increased because the bonding resistance is increased (S606; N) can be determined as normal bonding (S608) having a relatively small bonding resistance.

The timing controller 400 outputs the determination result of the bonding failure to the outside so that the operator can repair the bonding failure of each driving circuit unit 370 when the bonding is defective.

As described above, according to one embodiment of the present invention, the bonding resistance of the driving circuit portion can be sensed by using the ADC incorporated in the driving IC, and it is possible to easily check whether the bonding of the driving circuit portion is bad by using the sensing result. Can be reduced.

In one embodiment of the present invention, since the inspection time for inspecting the bonding resistance after the bonding process of the driving circuit portion can be reduced, the process tact time can be reduced and the measurement error can be reduced.

Since the advance bonding failure can be detected by sensing the bonding resistance of the driving circuit portion by using the ADC incorporated in the driving IC even after shipment of the product according to the embodiment of the present invention, .

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. It is intended that the scope of the invention be interpreted by the claims appended hereto, and that all techniques within the scope of equivalents thereof should be construed as being included within the scope of the present invention.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: memory 600:
700: PCB 310: ADC
350: Data IC 360: Circuit film
370: Driving circuit part 10: Bonding resistance sensing path
11, 12, 13, 14, 15: bonding pads 21, 22, 23, 24, 25:
362; 364: first and second bonding parts 110: panel bonding part
710: PCB bonding part

Claims (10)

A panel and a printed circuit board (PCB)
A drive circuit portion including a drive IC mounted on a circuit film and bonded between the panel and the PCB;
And a bonding resistance sensing path in which a plurality of bonding pads located in a second bonding section for bonding and connecting the panel and the circuit film are connected in series, and,
The driving IC
When the first sensing mode is selected, the first sensing data is outputted through the analog-to-digital converter (ADC) by sensing a signal reflecting the characteristic of each sub-pixel through the panel,
And sensing a signal reflecting the bonding resistance of the plurality of bonding pads through the bonding resistance sensing path when in the second sensing mode and outputting second sensing data through the ADC. The method according to claim 1,
Further comprising a timing controller for controlling the driving IC to operate in the first and second sensing modes,
The timing controller
And judging whether or not the bonding of the driving circuit unit is defective using the second sensing data. The method according to claim 1,
The driving circuit
A reference resistor serially connected between the bonding resistance sensing path and the ground,
Further comprising a switch for connecting a sensing node between the bonding resistance sensing path and the reference resistor and an input terminal of the ADC when the sensing mode is in the second sensing mode. The method according to claim 1,
The bonding resistance sensing path
A first bonding pad connected in series with a supply line of an input voltage and bonded between the PCB and the circuit film,
A second bonding pad connected in series with the first bonding pad and bonded between the panel and the circuit film,
A third bonding pad connected in series with the second bonding pad and arranged in parallel with the second bonding pad, the third bonding pad being bonded between the panel and the circuit film,
A fourth bonding pad connected in series with the third bonding pad and disposed in parallel with the first bonding pad, the fourth bonding pad being bonded between the PCB and the circuit film,
And a fifth bonding pad connected in series with the fourth bonding pad and disposed in parallel with the fourth bonding pad and bonded between the PCB and the circuit film,
Each of the first through fifth bonding pads
And a pair of pads bonded and connected by the anisotropic conductive film facing the circuit film and the PCB or the panel. The method of claim 4,
Wherein the first and second bonding pads are connected in series through a first connection line provided in the circuit film,
The second and third bonding pads are connected in series through a second connection line provided in the panel,
The third and fourth bonding pads are serially connected to the circuit film through a third connection line arranged in parallel with the first connection line,
The fourth and fifth bonding pads are connected in series through a fourth connection line provided on the PCB,
And a fifth connection line provided on the circuit film for connecting the fifth bonding pad to an input terminal of the driving IC. The method of claim 5,
The driving circuit
Further comprising a plurality of power wiring lines for supplying a driving voltage from the PCB to the panel through the circuit film,
Wherein the fourth and fifth bonding pads are spaced apart from each other with the plurality of power supply wirings therebetween,
Wherein the fifth bonding pad is disposed at one side of the circuit film adjacent to the plurality of power supply wirings or at a central portion of the circuit film. The method of claim 6,
The bonding resistance sensing path
A driver circuit portion disposed on one side of the driver circuit portion,
And are disposed on both side portions of the driving circuit portion. A plurality of bonding pads located in a second bonding section for bonding and connecting the panel and the circuit film are connected in series to each other, Supplying an input voltage to a bonding resistance sensing path connected thereto,
The input voltage generating a voltage reflecting the bonding resistance of the plurality of bonding pads at a sensing node between the bonding resistance sensing path and the reference resistance via the bonding resistance sensing path;
The ADC incorporated in the driving IC receives a voltage reflecting the bonding resistance from the sensing node, converts the voltage into sensing data, and outputs the sensed data;
And determining whether or not the bonding of the driving circuit unit is defective using the sensing data. The method of claim 8,
The ADC incorporated in the driving IC
In the first sensing mode, a signal indicating the characteristics of each sub-pixel is supplied through the first switch to the first sensing data,
And a second sensing mode, wherein the sensing resistor receives a voltage reflected from the sensing node through a second switch, converts the voltage into second sensing data, and outputs the second sensing data. The method of claim 8,
The step of determining whether or not the driving circuit unit is defective in bonding using the sensing data
Comparing the sensing data with a reference value,
Determining that bonding of the driving circuit unit is normal if the sensing data is equal to or greater than the reference value;
And determining that the bonding of the driving circuit unit is defective if the sensing data is smaller than the reference value.

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