KR20180066065A - Encoded multi-lane N-factor and other multi-wire communication systems - Google Patents

Abstract

In particular, systems, methods, and apparatus for facilitating communication of data over a multi-wire data communication link between two devices in an electronic device are described. The receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from and parallel to the multi-wire link. The receiving device uses the clock signal to decode the sequence of symbols. In an aspect, the second clock signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols. Thus, the receiving device decodes the sequence of symbols using the clock signal received over the dedicated clock line, ignoring the second clock signal.

Description

Encoded multi-lane N-factor and other multi-wire communication systems

This application claims the benefit of US Provisional Application No. 14 / 250,119, filed April 10, 2014, titled "Multi-Lane N-Factorial (N!) And Other Multi-Wire Communication Systems" Continuing application; In addition, U.S. Provisional Patent Application No. 61 / 886,567, entitled " N Factorial Clock And Data Recovery With Negative Hold Time Sampling, "filed October 3, 2013, Filed on April 14, 2014, entitled " Factorial Dual Data Rate Clock And Data Recovery ", which is a continuation-in-part of US Serial No. 14 / 252,450; In addition, the present application claims priority to U. S. Provisional Application No. 61 / 886,556, filed October 3, 2013, entitled " Method To Enhance MIPI D-PHY Link Rate With Minimal PHY Changes And No Protocol Changes & Part of the application serial no. 14 / 491,884 filed on September 19, 2014 entitled " Method To Enhance MIPI D-PHY Link Rate With Minimal PHY Changes And No Protocol Changes ", filed October 10, 2015 No. 14 / 875,592, filed May 5, 2005, the entire contents of which are incorporated herein by reference.

[0002] This disclosure relates generally to data communication interfaces, and more particularly to multi-lane multi-wire data communication interfaces.

[0003] Manufacturers of mobile devices, such as cellular phones, can obtain components of mobile devices from a variety of sources including different manufacturers. For example, an application processor of a cellular phone may be obtained from a first manufacturer, while a display for a cellular phone may be obtained from a second manufacturer. The application processor and display or other device may be interconnected using a standard-based or proprietary physical interface. For example, the display may provide an interface conforming to the DSI (Display System Interface) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).

[0004] In one example, a multi-signal data delivery system may utilize multi-wire differential signaling such as 3-phase or N-factor (N!) Low-voltage differential signaling (LVDS) Transcoding (e.g., digital-to-digital data conversion to another encoding type of one encoding type) may be performed to insert symbol clock information by causing a symbol transition in each symbol cycle. Inserting the clock information by transcoding minimizes the skew between clock and data signals as well as eliminates the need for a phase-locked loop (PLL) Method.

[0005] There is an ongoing need for optimized communications and improved data transfer rates over multi-signal communication links.

[0006] The embodiments disclosed herein provide systems, methods and apparatus related to multi-lane multi-wire interfaces.

[0007] In one aspect of the present disclosure, a method of data communication at a receiving device includes receiving a sequence of symbols over a multi-wire link. Each symbol in the sequence of symbols corresponds to the signaling state of the N wires of the multi-wire link, where N is an integer greater than one. The method further includes receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from and parallel to the multi-wire link, and decoding the sequence of symbols using the clock signal .

[0008] In one aspect of the present disclosure, a second clock signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols. Thus, the method decodes a sequence of symbols using a clock signal received over a dedicated clock line, ignoring the second clock signal.

[0009] In one aspect of the present disclosure, the step of decoding includes converting a sequence of symbols into a set of data bits using a clock signal. In a further aspect of the present disclosure, converting the sequence of symbols to a set of data bits includes using a transcoder to convert a sequence of symbols to a set of transition numbers, Into a set.

[0010] In one aspect of the present disclosure, at least one line of the multi-wire link is bi-directional. The method further includes transmitting a second sequence of symbols over at least one bi-directional line based on a clock signal received via a dedicated clock line.

[0011] In one aspect of the present disclosure, a dedicated clock line is bi-directional and can be driven from any device that transmits over a multi-wire link. The method further includes transmitting a third clock signal over a dedicated clock line. The third clock signal may be associated with a transmission clock used to encode data bits in a sequence of symbols transmitted over at least one bi-directional line.

[0012] In one aspect of the present disclosure, a receiving device includes a processing circuit. The memory may be coupled to the processing circuitry. The processing circuit receives the sequence of symbols over a multi-wire link and receives the clock signal through a dedicated clock line, the dedicated clock line being separate from and parallel to the multi-wire link, To decode the sequence of symbols.

[0013] In one aspect of the present disclosure, an apparatus includes means for receiving a sequence of symbols over a multi-wire link, means for receiving a clock signal over a dedicated clock line, And means for decoding the sequence of symbols using the clock signal.

[0014] In one aspect of the present disclosure, one or more instructions are stored or held in a processor-readable storage medium. When executed by at least one processing circuit, the instructions cause at least one processing circuit to receive a sequence of symbols over a multi-wire link and receive a clock signal over a dedicated clock line, Be separate from and parallel to the multi-wire link, and use a clock signal to decode the sequence of symbols.

[0015] In one aspect of the disclosure, a method of data communication in a transmitting device includes encoding data bits in a sequence of symbols, selectively inserting a second clock signal in a sequence of symbols, 2 clock signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols. Each symbol in the sequence of symbols corresponds to the signaling state of the N wires of the multi-wire link, where N is an integer greater than one. The method further includes transmitting a sequence of symbols over a multi-wire link, and transmitting a clock signal associated with the sequence of symbols over a dedicated clock line, wherein the dedicated clock line is a multi-wire link Are separate and parallel to it.

[0016] In one aspect of the present disclosure, encoding the data bits comprises using a transcoder to convert the data bits into a set of transition numbers, and using a set of transition numbers to obtain a sequence of symbols .

[0017] In an aspect of the present disclosure, at least one line of the multi-wire link is bidirectional. The method further includes receiving a second sequence of symbols over at least one bi-directional line based on a clock signal transmitted over a dedicated clock line.

[0018] In an aspect of the present disclosure, the dedicated clock line is bidirectional and may be driven from any device transmitting over a multi-wire link. The method further includes receiving a third clock signal via a dedicated clock line. The third clock signal may be associated with a transmission clock that is used to encode data bits in a sequence of received symbols over at least one bi-directional line.

[0019] In an aspect of the present disclosure, a transmitting device includes a processing circuit. The processing circuitry may be coupled to a memory. The processing circuitry may encode the data bits in a sequence of symbols and selectively insert a second clock signal into the sequence of symbols and the second clock signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols - to transmit a sequence of symbols over a multi-wire link, and to transmit a clock signal associated with a sequence of symbols over a dedicated clock line, wherein the dedicated clock line is separate from the multi- Respectively.

[0020] In one aspect of the present disclosure, an apparatus includes means for encoding data bits in a sequence of symbols using a clock signal, means for selectively inserting a second clock signal in a sequence of symbols, Wherein the signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols, means for transmitting a sequence of symbols over a multi-wire link, and means for transmitting a clock associated with the sequence of symbols over a dedicated clock line, Wherein the dedicated clock line is separate from and parallel to the multi-wire link.

[0021] In one aspect of the present disclosure, one or more instructions are stored or held in a processor-readable storage medium. When executed by at least one processing circuit, the instructions cause at least one processing circuit to encode data bits in a sequence of symbols, selectively insert a second clock signal into the sequence of symbols, Inserted into guaranteed transitions between pairs of consecutive symbols in a sequence of symbols, to transmit a sequence of symbols over a multi-wire link, and to transmit a clock signal associated with a sequence of symbols over a dedicated clock line , Where the dedicated clock line is separate from and parallel to the multi-wire link.

[0022] FIG. 1 illustrates an apparatus that utilizes a data link between integrated circuit (IC) devices selectively operating according to one of a plurality of available standards.
[0023] FIG. 2 illustrates a system architecture for a device that utilizes a data link between IC devices.
[0024] FIG. ≪ / RTI > illustrates a CDR circuit that may be used in a communication interface.
[0025] FIG. 4 illustrates the timing of certain signals generated by the CDR circuit of FIG. 3, in accordance with one or more aspects disclosed herein.
[0026] FIG. 5 is a diagram showing a basic N! An example of a multi-lane interface is illustrated.
[0027] FIG. 6 illustrates a first example of a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0028] FIG. 7 illustrates a second example of a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0029] FIG. 8 illustrates a third example of a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0030] FIG. 9 illustrates a fourth example of a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0031] FIG. 10 is a timing diagram illustrating the ordering of data transmitted over a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0032] FIG. 11 illustrates a fifth example of a multi-lane interface provided in accordance with one or more aspects disclosed herein.
[0033] FIG. 12 is a flow diagram of a method for operating a receiver in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein.
[0034] FIG. 13 is a diagram illustrating a simplified example of a receiver in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein.
[0035] Figure 14 is a flow diagram of a method for operating a transmitter in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein.
[0036] FIG. 15 is a diagram illustrating a simplified example of a transmitter in a multi-lane N-wire interface provided in accordance with one or more aspects disclosed herein.
[0037] Figure 16 is a diagram illustrating a further example of a multi-lane interface provided between two devices in accordance with one or more aspects disclosed herein.
[0038] FIG. 17 illustrates examples of transmitting symbols on a plurality of data lanes using a dedicated clock line.
[0039] FIG. 18 illustrates examples of multi-wire transcoding using dedicated clock lines.
[0040] FIG. 19 is an illustration of an apparatus (receiving device) configured to support operations related to communicating data bits over a multi-wire link in accordance with one or more aspects disclosed herein.
[0041] FIG. 20 is a flow diagram illustrating a method of a receiving device for communicating data bits over a multi-wire link.
[0042] FIG. 21 is an illustration of an apparatus (transmitting device) configured to support operations related to communicating data bits over a multi-wire link in accordance with one or more aspects disclosed herein.
[0043] FIG. 22 is a flow chart illustrating a method of a transmitting device for communicating data bits over a multi-wire link.

[0044] Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect (s) may be practiced without these specific details.

[0045] As used in this application, the terms "component," "module," "system," and the like are intended to refer to a combination of hardware, firmware, hardware and software, software, Computer-related entities are intended to be included. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, an execution thread, a program and / or a computer. By way of example, both an application running on a computing device and a computing device may be a component. One or more of the components may reside within a process and / or thread of execution, and the component may be localized on one computer and / or distributed between two or more computers. Additionally, these components may execute from various computer readable media having various data structures stored thereon. The components may be, for example, a signal having one or more data packets, such as a local system, a network interacting with other components in a distributed system and / or with other systems by means of a signal, Lt; / RTI > and / or remote processes in accordance with the data from the component of the device.

[0046] Also, the term "or" is intended to mean "exclusive" or "rather than" or ". That is, unless otherwise stated or contextually clear, the phrase "X uses A or B" is intended to mean any substitution of the original generic substitutions. That is, the following examples of the phrase "X uses A or B ", i.e., X uses A; X uses B; Or < RTI ID = 0.0 > X < / RTI > uses both A and B. Additionally, the singular expressions as used in this application and the appended claims should be interpreted generally to mean "one or more, " unless the context clearly dictates otherwise or in a singular form.

Certain aspects of the invention relate to communication links disposed between electronic devices that may include subcomponents of the device, such as a telephone, a mobile computing device, a device, automotive electronics, avionics systems, May be applicable. 1 illustrates an apparatus that can utilize a communication link between IC devices. In one example, the device 100 may include a wireless communication device that communicates via a radio frequency (RF) transceiver using a radio access network (RAN), a core access network, the Internet, and / or other networks. Apparatus 100 may include a communications transceiver 106 operably coupled to processing circuitry 102. The processing circuitry 102 may include one or more IC devices, such as an application specific integrated circuit (ASIC) The ASIC 108 may include one or more processing devices, logic circuits, and the like. The processing circuitry 102 may include and / or be coupled to a processor readable storage, such as memory 112, that may hold instructions and data that may be executed by the processing circuitry 102. For example, The processing circuitry 102 may include one or more of an application programming interface (API) 110 layer and an operating system that support and enable the execution of software modules resident on storage media, such as the memory device 112 of the wireless device. Lt; / RTI > The memory device 112 may be any type of memory device such as a read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory that may be used in processing systems and computing platforms Device. The processing circuitry 102 may include or have access to a local database 114 that may hold operating parameters and other information used to configure and operate the device 100. Local database 114 may be implemented using one or more of a database module, flash memory, magnetic media, EEPROM, optical media, tape, soft or hard disk, The processing circuitry may also be operably coupled to external devices, such as antenna 122, display 124, operator controls, such as button 128 and keypad 126, among other components.

[0048] Figure 2 is a block schematic diagram illustrating certain aspects of an apparatus 200 connected to a communication bus, wherein the apparatus 200 may be a wireless mobile device, a mobile telephone, a mobile computing system, a wireless telephone, a notebook computer, A device, a media player, a gaming device, or the like. Apparatus 200 may include a plurality of IC devices 202 and 230 that exchange data and control information over a communication link 220. The communication link 220 may be used to connect IC devices 202 and 230 that are closely located to each other or that are physically located in different parts of the device 200. In one example, communication link 220 may be provided on a chip carrier, substrate, or circuit board that holds IC devices 202 and 230. In another example, the first IC device 202 may be located in a keypad section of a flip-phone while the second IC device 230 may be located in a display section of a flip- have. In another example, a portion of communication link 220 may comprise a cable or an optical connection.

[0049] Communication link 220 may include multiple channels 222, 224, and 226. One or more of the channels 226 may be bi-directional and may operate in half-duplex and / or full-duplex modes. One or more of the channels 222 and 224 may be unidirectional. The communication link 220 is asymmetric and can provide higher bandwidth in one direction. In one example described herein, a first communication channel 222 may be referred to as a forward link 222, while a second communication channel 224 may be referred to as a reverse link 224. The first IC device 202 may be designated as a host system or transmitter while the second IC device 230 is configured to transmit and receive on the communication link 222, May be designated as a client system or receiver. In one example, the forward link 222 may operate at a higher data rate when communicating data from the first IC device 202 to the second IC device 230, while the reverse link 224 may operate at a higher data rate, And may operate at a lower data rate when communicating data from the second IC device 230 to the first IC device 202. [

[0050] Each of IC devices 202 and 230 may have a processor or other processing and / or computing circuit or device 206, 236. In one example, the first IC device 202 may perform core functions of the device 200, including maintaining wireless communications via the wireless transceiver 204 and the antenna 214, while the second IC < RTI ID = 0.0 > The device 230 may support a user interface that manages or operates the display controller 232. The first IC device 202 or the second IC device 230 may use the camera controller 234 to control the operation of the camera or video input device. Other features supported by one or more of the IC devices 202 and 230 may include a keyboard, a voice-recognition component, and other input or output devices. Display controller 232 may include circuitry and software drivers that support displays such as liquid crystal display (LCD) panels, touch-screen displays, indicators, and the like. The storage media 208 and 238 may be any type of storage device, such as temporary and / or non-volatile memory, adapted to hold instructions and data used by the respective processors 206 and 236 and / or other components of the IC devices 202 and 230. [ Or non-temporal storage devices. Communication between each processor 206 and 236 and its corresponding storage mediums 208 and 238 and other modules and circuits may be facilitated by one or more buses 212 and 242, have.

The reverse link 224 may be operated in the same manner as the forward link 222 and the forward link 222 and the reverse link 224 may be capable of transmitting at similar or different rates, Here, the speed may be expressed as data transfer rate and / or clocking rates. The forward and reverse data rates may be substantially the same or tens of times different depending on the application. In some applications, a single bi-directional link 226 may support communications between the first IC device 202 and the second IC device 230. In some applications, Forward link 222 and / or reverse link 224 may be configurable to operate in bidirectional mode, for example, when forward and reverse links 222 and 224 share the same physical connections and operate in a half-duplex fashion. have. In one example, communication link 220 may be operable to communicate control, command, and other information between first IC device 202 and second IC device 230 in accordance with industry or other standards.

In one example, the forward and reverse links 222 and 224 support wide video graphics array (WVGA) 80 frames per second LCD driver IC without a frame buffer to deliver pixel data at 810 Mbps for display refresh Or < / RTI > In another example, the forward and reverse links 222 and 224 may be configured or adapted to enable communications with dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (SDRAM). The encoding devices 210 and / or 240 may encode multiple bits per clock transition, and multiple sets of wires may be used to transmit and receive data, control signals, address signals, etc., from the SDRAM have.

[0053] Forward and reverse links 222 and 224 may follow or be compatible with application-specific industry standards. In one example, the MIPI standard defines physical layer interfaces between an application processor IC device 202 and an IC device 230 that support a camera or display in a mobile device. The MIPI standard includes specifications for managing operational characteristics of products that comply with MIPI specifications for mobile devices. The MIPI standard may define interfaces using complementary metal-oxide-semiconductor (CMOS) parallel busses.

[0054] In one example, the communication link 220 of FIG. 2 may be implemented as a wiring bus comprising a plurality of signal wires (denoted as N wires). The N wires may be configured to carry data encoded with symbols, wherein the clock information is inserted in a sequence of symbols transmitted over a plurality of wires.

[0055] FIG. 3 illustrates an example of a clock and data recovery (CDR) circuit 300 that may be utilized to recover embedded clock information in an N-wire system. 4 is a timing diagram 400 illustrating the specific signals generated through the operation of the CDR circuit 300. [ Although the CDR circuitry 300 and its timing diagram 400 are provided as generalized examples, other variations of the CDR circuitry 300 and / or other CDR circuits may be used in some examples. Received from N- wires 308, signals are processed by a receiver 302 of the number _(N C ₂₎ Initially, the receiver should generate the native (raw) signal of the corresponding number as output. In the illustrated example, N = 4 wires 308 are coupled to ₄ C ₂ ( _{2 <} RTI ID = 0.0 _> = Is processed by six receivers 302. For each raw signal output from each of the different receivers, there may be a setup time 408 provided between the symbols S ₀ 402, S ₁ 404 and S ₂ 406, The state of the corresponding signal is undefined, undetermined, transient, or otherwise unstable. Level latches 310, a comparator 304, a set-reset latch 306, a one-shot circuit 326, an analog delay element 312, Level latches 310 may be configured to generate a level-latched signal (S signal) 322 that represents a delayed instance of the SI signal 320, The delay before capturing and providing the updated S signal 322 may be selected by configuring the delay element (delay S)

In operation, the comparator 304 compares the SI signal 320 with the S signal 322 and outputs a binary comparison signal (NE signal) 314. The set-reset latch 306 may receive the NE signal 314 from the comparator 304 and output a signal (NEFLT signal) 316 that is a filtered version of the NE signal 314. The operation of the set-reset latch 306 may be configured to remove any transient instability in the NE signal 314, where transient instability is indicated as spikes 410 in the NE signal 314. [ The NEFLT signal 316 may be used to control the output latches 324 that capture the S signal 322 as the output data signal 328.

The one-shot circuit 326 receives the NEFLT signal 316 and generates a fixed width pulse 412 which is then delayed by the delay element 312 to produce a clock signal SDRCLK ( 318 < / RTI > In some instances, the SDRCLK signal 318 may be used by external circuitry to sample the data output 328 of the CDR 300. In one example, the SDRCLK signal 318 may be provided to the decoder or deserializer circuits. Level latches 310 receive the SI signal 320 and output an S signal 322 where the level latches 310 are triggered by the SDRCLK signal 318 or otherwise controlled.

[0058] In operation, the comparator 304 compares the SI signal 322 with the S signal 322 output from the level latches 310. Comparator 304 causes NE signal 314 to be in a first state (e.g., logic low) when SI signal 320 and S signal 322 are the same and SI signal 320 and S signal 322 (E.g., logic high) if they are not the same. The NE signal 314 is in a second state when the SI signal 320 and the S signal 322 represent different symbols. Thus, the second state indicates that a transition is occurring.

As can be appreciated from the timing diagram 400, the S signal 322 is essentially a delayed and filtered version of the SI signal 320, where the SI signal 320 and the S signal 322, The transients or glitches 408 are removed because of the delay 414 between them. Although a number of transitions 408 of the SI signal 320 may be reflected as spikes 410 in the NE signal 314, these spikes 410 may cause the NEFLT signal 316 . SDRCLK 318 may also be used to provide line skew and glitch tolerance of the symbol transitions based on the use of the delays 326a and 312 provided in the feedback path to level-latch 310 and set- Whereby the SDRCLK signal 318 controls the reset function of the set-reset latch 306.

[0060] At the start 416 of the transition between the first symbol value S ₀ 402 and the next symbol value S ₁ 404, the SI signal 320 begins to change state. The state of the SI signal 320 may be different from S ₁ 404 due to the possibility of intermediate or undetermined states 408 during the transition between S ₀ 402 and S ₁ 404. These intermediate or undetermined states 408 may be caused, for example, by inter-wire skew, over / undershoot, crosstalk, and the like.

The NE signal 314 is high as soon as the comparator 304 detects a difference in values between the SI signal 320 and the S signal 322 and the transition high of the NE signal 314 is set to a set- The latch 306 output is set asynchronously, causing the NEFLT signal 316 to go high. The NEFLT signal 316 remains at its high state until the set-reset latch 306 is reset by the high state of the SDRCLK signal 318. [ The SDRCLK signal 318 is a delayed version of the NE1SHOT signal 324, which is a limited pulse-width version of the NEFLT signal 316. [ For example, the SDRCLK signal 318 may be delayed for the NE1SHOT signal 324 through the use of the analog delay circuit 312. [

[0062] Intermediate or undetermined states 408 for SI 320 may represent invalid data. These intermediate or undetermined states 408 may include a short period of the previous symbol value S ₀ 402 and may cause the NE signal 314 to return to low for short time periods. Transitions of the SI signal 320 may generate spikes 410 on the NE signal 314. Spikes 410 are effectively filtered out and are not present in the NEFLT signal 316.

The high state of the NEFLT signal 316 causes the SDRCLK signal 318 to transition high after the delay period 340 caused by the delay circuit 312. The high state of the SDRCLK signal 318 resets the set-reset latch 306 output to cause the NEFLT signal 316 to transition to a low state. The high state of the SDRCLK signal 318 also enables the level latches 310 and the value of the SI signal 320 may be output on the S signal 322. [

[0064] The comparator 304 is (symbol S ₁ (402) to about) S signal 322 is detected that the symbol matches with the S ₁ (402) value present on the SI signal 320, and their (NE signal 314) to a low. The low state of the NEFLT signal 316 causes the SDRCLK signal 318 to go low after the delay period 342 caused by the analog delay 312. [ This cycle is repeated for each transition of the SI signal 320. At a time after the falling edge of the SDRCLK signal 318, a new symbol S ₂ 406 may be received and cause the SI signal 320 to switch its value according to the next symbol S ₂ 406 .

[0065] FIG. 5 is a diagram illustrating an example of a multi-lane interface 500 provided between two devices 502 and 532. Transcoders 506 and 516 transmit data 504 and 514 and the clock information to the symbols to be transmitted over the set of N wires on each lane 512 and 522, Can be used to encode using factorial (N!) Encoding. By ensuring that the clock information, is derived from each of the transmit clock (524, 526), a signaling state transition is generated on at least one of the _N C ₂ of the signal between successive symbols, on the N pieces of wires _N Lt; _{RTI ID = 0.0} > C < / _RTI > differential signals. N! If the encoding is used to drive N wires, each bit of the symbol is transmitted as a differential signal by one of a set of line drivers 510, 520, where the set of line drivers 510 , 520 are coupled to different pairs of N wires. The number of available combinations of wire pairs and signals can be calculated to be _N C ₂ , and the number of available combinations determines the number of signals that can be transmitted over the N wires. The number of data bits 504, 514 that can be encoded into symbols may be calculated based on the number of available signaling states available during each symbol transmission interval.

[0066] The termination impedance (typically resistive) couples each of the N wires to a common central point of the termination network 528, 530. It will be appreciated that the signaling states of the N wires reflect the combination of the currents of the termination networks 528, 530 due to the differential drivers 510, 520 coupled to each wire. It will be further appreciated that the center point of the termination network 528, 530 is a null point so that the currents of the terminating networks 528, 530 cancel each other at a central point.

Since at least one of the _N C ₂ signals in the link transitions between consecutive symbols, N! The encoding scheme need not use a separate clock channel and / or non-return-to-zero decoding. Efficiently, each transcoder 506, 516 generates a sequence of symbols, each symbol different from its previous full symbol, so that a transition between each pair of symbols transmitted on the N wires . In the example shown in Figure 5, each lane 512,522 has N = 4 wires, each set of ₄ wires having ₄ C ₂ = 6 differential signals can be carried. Transcoders 506 and 516 may use a mapping scheme to generate raw symbols for transmission on N wires available on lanes 512 and 522. [ Transcoders 506 and 516 and serializers 508 and 518 collaborate to generate raw symbols for transmission based on input data bits 504 and 514. At receiver 532, transcoder 540, 550 may use mapping to determine, for example, a transition number that characterizes the difference between successive symbols of the original symbols, i. E., Symbols in the lookup table. The transcoders 506, 516, 540, 550 operate on the basis that every successive pair of primitive symbols includes two different symbols.

[0068] Transcoder 506, 516 of transmitter 502 may select between N! -1 states available in every respective symbol transition. In one example, 4! The system provides 4! -1 = 23 signaling states for the next symbol to be transmitted in each symbol transition. The bit rate may be calculated as log ₂ (available_states) per cycle of the transmit clocks 524 and 526. In systems using double data rate (DDR) clocking, symbol transitions occur at both the rising and falling edges of the transmit clocks 524 and 526. In one example, two or more symbols may be sent per word (i.e., every transmission clock cycle), so that the total available states of the transmission clock cycle are ( _N C ₂ -1) ² = (23) ² = 529, and the number of data bits 504 that can be transmitted per symbol may be calculated as log2 (529) = 9.047 bits.

[0069] The receiving device 532 receives a sequence of symbols using a set of line receivers 534 and 544, wherein each receiver in the set of line receivers 534 and 544 receives one of the N wires To determine differences in signaling states for the pair. Thus, _N C ₂ receivers are used in each lane 512, 522, where N represents the number of wires in the corresponding lane 512, 522. _N C ₂ of the two receivers (534, 544) produces the raw number of symbols as the corresponding output.

In the illustrated example, each of the lanes 512, 522 has N = 4 wires, and the signals received on the four wires of each lane 512, 522 correspond to the corresponding CDRs 536, s 546) and de-serializer (538, 548) to six receivers to generate a state transition signal provided to the (C _{2 4} = 6). ≪ / RTI > The CDRs 536 and 546 may operate in generally the same manner as the CDR 300 of Figure 3 and each CDR 536 and 546 may be used by a corresponding deserializer 538 and 548 And generate receive clock signals 554,556. Clock signal 554 may include a DDR clock signal that may be used by external circuitry to receive data provided by transcoders 540 and 550. [ Each transcoder 540, 550 decodes a block of received symbols from the corresponding deserializer 538, 548 by comparing each subsequent symbol with its previous full-time. Transcoders 540 and 550 generate output data 542 and 552 corresponding to data 504 and 514 provided to transmitter 502. Transcoders 540 and 550 generate output data 542 and 552,

As illustrated in the example of FIG. 5, each lane 512, 522 may be operated independently, but in a typical application, the data 504 transmitted over one lane 512 may be different May be synchronized with the data 514 transmitted via the lane 522. In one example, data bits 504 for transmission over a first lane (lane X in this example) 512 are transmitted in a predetermined sequence, and a transition in the signaling state is applied to the first lane 512 And is received by a first transcoder 506 that generates a set of primitive symbols ensuring that it occurs on at least one signal transmitted on four wires. The serializer 508 generates a sequence of symbol values provided to the line drivers 510 that determines the signaling state of the four wires of the first lane 512 during each symbol interval. At the same time, the data bits 514 are received by the second transcoder 516 of the second lane (lane Y in this example) The second transcoder 516 generates a set of transition numbers serialized by the serializer 518 and the serializer 518 generates a signaling state of the four wires of the second lane 522 during each symbol interval To a set of symbol values provided to the line drivers 520 that determine the set of transition values. The sequence of primitive symbols ensures that a transition of the signaling state occurs in at least one signal transmitted on four wires of the second lane 522 between each pair of consecutive symbols.

[0072] FIG. 6 illustrates a first example of a multi-lane interface 600 provided in accordance with certain aspects disclosed herein. The multi-lane interface 600 may be configured such that the clock information encoded in the symbols transmitted on the first lane (here lane X) 612 is encoded on one or more other lanes including the lane Y 622, When used to receive symbols that are transmitted without the resulting clock information, provide improved data throughput and reduced circuit complexity. In the illustrated example, each lane 612, 622 includes four wires.

[0073] Data for transmission may be divided into two parts 604 and 614, where each part is transmitted on a different lane 612, 622. On the first lane 612, the information related to the data 604 and the transmission clock 624 is used by the transcoder / serializer 608 to obtain the raw symbols that are serialized as described in connection with FIG. Lt; / RTI > At receiver 632, the output of receivers 634 associated with first lane 612 is provided to CDR 636. [ CDR 636 detects transitions in the signaling state to generate a receive clock 654 that is used by both deserialization and transcoding circuits 638 and 648 for both lanes 612 and 622 . The first deserialization and transcoding circuits 638 extract data 642 from the raw symbols received from the first lane 612 while the second deserialization and transcoding circuits 648 extract the data 642 from the second And extracts data (652) from the raw symbols received from lane (622).

For second lane 622, transmission data 614 is provided to transcoding and serialization circuits 618 and may be transmitted on second lane 622 without encoded clock information. The transcoding circuit used to generate the raw symbols for the second lane 622 is a transcoding circuit that is used to generate raw symbols with embedded clock information for transmission on the first lane 612 It can be considerably less complex. For example, the transcoding circuits for the second lane 622 may not need to perform certain arithmetic operations and logic functions to ensure state transitions at every respective symbol boundary.

[0075] In the example shown in FIG. 6, the first lane 612 of the DDR clocked four-wire is (4! -1) ² = (23) ² = The second lane 622 of the DDR clocked four-wire provides (4!) The 529 signaling states and can encode the log ₂ 529 = 9.047 bits of data per received word 604, 614. ² = (24) ² = Provides 576 signaling states, and log _{2 of} data per word 576 = 9.170 bits can be encoded. In another example, the interface may have two 3-wire lanes, where the clock information is encoded in the first lane, not the second lane. In this latter example, seven symbols may be sent per word, and the first lane of the three-wire may be (3! -1) ⁷ = (5) ⁷ = Providing 78125 signaling states, and log _{2 of} data per word 78125 = 16.253 bits while the second lane of the 3-wire is (3!) ⁷ = 6 ⁷ = It provides 279936 signaling states and is able to encode log ₂ 279936 = 18.095 bits of data in each clock cycle. By encoding the clock information in a single lane of multi-lane N !, higher overall throughput can be achieved with fewer hardware.

[0076] FIG. 7 illustrates another example of a multi-lane interface 700 provided in accordance with one or more aspects disclosed herein. The multi-lane interface 700 provides improved flexibility in design in addition to optimized data throughput and reduced circuit complexity. Here, the clock information encoded with the symbols transmitted on one lane (here lane X) 712 may be used to receive symbols transmitted on one or more other lanes 722 having different numbers of wires Lt; / RTI >

[0077] In the illustrated example, the data for transmission may be divided into a plurality of portions 704 and 714, where each portion will be transmitted on a different lane 712, 722. On the first lane 712, the data 704 and the transmission clock 724 are transmitted by the transcoding and serialization circuits 708 to obtain a sequence of primitive symbols as described in connection with Figures 5 and 6 Can be converted. On the second lane 722, the received data 714 is provided to the transcoding and serialization circuits 718 and can then be transmitted without the embedded clock information.

At receiver 732, the output of receivers 734 associated with first lane 712 is provided to CDR 736. The CDR 736 detects the transition of the signaling state of the three wires in the first lane 712 and outputs the deserialization and transcoding circuits 738 and 748 both for the lanes 712 and 722 May be configured to generate a receive clock 754 that is used by all. The first deserialization and transcoding circuits 738 extract data 742 from the raw symbols received from the first lane 712 while the second deserialization and transcoding circuits 748 extract the data 742 from the second deserialization and transcoding circuits 748, And extracts data 752 from the raw symbols received from lane 722.

[0079] In an example, the first lane 712 is 3! While the second lane 722 includes three wires configured for operation < RTI ID = 0.0 > And includes four wires configured for operation. The first lane 712 is (3! -1) ² for two symbols per word system = (5) ² = It is possible to provide 25 signaling states, whereby the log ₂ 25 = 4.644 bits can be encoded per word. The second lane 722 of the 4-wire provides (4!) ² = (24) ² = 576 signaling states and can encode log ₂ 576 = 9.170 bits of data per word.

[0080] If a single lane 712 encodes clock information and variable number of wires can be assigned to different lanes 722, significant efficiencies can be obtained. In one example where ten interconnects (wires or connectors) are available between two devices, a conventional three! The system can configure three 3-wire lanes and the clock information is encoded on each lane. Each of the three lanes provides five signaling states per symbol for a total of 15 states per symbol. However, the system provided in accordance with the specific aspects described herein is not limited to two 3! Lanes and one four! Ten interconnects can be used to provide lanes, where the clock information is the first 3! Encoded in lanes. This combination of lanes is the first 3! Lane provides five states plus clock information per symbol, and the second three! Lane provides 6 states per symbol, 4! Provides a total of 5 x 6 x 24 = 720 signaling states per symbol based on the lanes providing 24 states per symbol.

[0081] FIG. 8 illustrates another example of a multi-lane interface 800 provided in accordance with one or more aspects disclosed herein. The multi-lane interface 800 provides a variety of advantages, including improved decoding reliability that can allow higher transmission rates. The construction and operation of this example multi-lane interface 800 is such that the CDR 836 generates a receive clock 854 from transitions detected on either the first lane 812 or the second lane 822 6 is similar to that of the multi-lane interface 600 of Fig. Thus, CDR 836 receives the outputs of receivers 834 and 844. Variations in the delay between the symbol boundary and the edge of the receive clock 854 may be reduced because the CDR 836 generates a clock from the first detected transition on either of the lanes 812 or 822. [ This approach may reduce the effects of variable transition times for the wires and / or variable switching times of the line drivers 810, 820 or receivers 834, 844.

[0082] In operation, data for transmission may be received at two or more portions 804 and 814, where portions 804 and 814 may be received on different lanes 812 and 822 For transmission. The combination of transcoder and serializer circuits 808 encodes the data bits X 804 as described with respect to FIG. 5 and adds the transmit clock (" X ") to the sequence of symbols to be transmitted on the first lane 812 824). At receiver 832, the outputs of both sets of receivers 834 and 844 detect transitions of the signaling state on either of lanes 812 and 822 and generate a receive clock 854 based on the transition To the CDR 836, which is configured to generate the < RTI ID = 0.0 > The receive clock 854 is used by both the deserialization / transcoding circuits 838 and 848 to generate the respective first and second lane data outputs 842 and 852.

[0083] FIG. 9 illustrates another example of a multi-lane interface 900 provided in accordance with one or more aspects disclosed herein. In this example, the multi-lane interface 900 ensures that transitions of the signaling state between consecutive symbol intervals occur on any one of the plurality of lanes 912, 922, Encoding efficiency. Thus, the percentage overhead associated with encoding the clock information can be reduced compared to a system in which the clock information is inserted into sequences of transmitted symbols on a single lane. In the multi-lane interface 900, the first lane (here, the lane X) 912 includes three wires carrying 3! Encoded signals, while the second lane (here the lane Y) 922 ) Contains four wires, and 4! Lt; / RTI > encoding. Different numbers and configurations of lanes can be used, and the specific example shown in Figure 9 is provided for illustrative purposes only. The transcoder 906 may be adapted to combine the data 904 with the clock information in the symbols to be transmitted via two or more lanes 912 and / or 922.

[0084] Encoding efficiencies can be achieved by inserting clock information based on a combination of the available signaling states for all lanes 912, 922. The clock information is inserted by ensuring that a transition of the signaling state occurs on at least one lane 912, 922 between consecutive symbol intervals. In operation, a transcoder 906 may be configured to generate different sets of symbols for each lane 912, 922. In one example, the data 904 received by the transmitter 902 in accordance with the clock signal 924 includes a first sequence of symbols encoded with three signals transmitted on the first lane 912 of 3, May be transmitted as a second sequence of encoded symbols with six signals transmitted simultaneously on the second lane 922 of the second lane 922. [ The transcoder 906 inserts the clock information by ensuring that the signaling state transition occurs on at least one of the lanes 912 and 922 between consecutive symbols. The total number of states per symbol interval is the product of the number of states per symbol transmitted on the first lane 912 and the number of states per symbol transmitted on the second lane 922. Thus, when clock information is inserted across both lanes 912 and 922, the number of states available to the transcoder at each symbol interval can be calculated as: < RTI ID = 0.0 >

In another example, if the clock information is inserted over two lanes encoded with three signals using 3s, then the number of states available to the transcoder at each symbol interval may be calculated as :

[0085] The number of states available to the transcoder in each symbol transition manages the number of bits that can be transmitted in each received data cycle.

[0086] Tables 1 and 2 show the case where the clock information is 2 or more N! Illustrate increased coding efficiencies when inserted by a transcoder across lanes. Table 1 relates to the multi-lane interface 900 of FIG. As can be seen from the table, the maximum encoding efficiency is obtained when the transcoder 906 inserts the clock information by considering the sequences of symbols transmitted on both lanes 912, 922.

Table 2 shows two 3! Lane < / RTI > interface with lanes.

In the example of FIG. 9, the receiver 932 includes a CDR 936 that generates a received clock 954 by detecting transitions on both lanes 912, 922. Deserializers 938 and 948 provide received symbols from respective lanes 912 and 922 to a transcoder 940 that inverts the transcoding performed by the transcoder 906 of the transmitter . The transcoder 940 of the receiver 932 operates by examining the combined sequences of received symbols to produce output data 942 corresponding to the data 904 received at the transmitter 902. The sets of line drivers 910, 920 and receivers 934, 944 are set to N! May be provided according to the number of wires of the lanes 912, 922.

[0088] The multi-lane interface 900 may be configured to provide additional advantages over conventional interfaces. 10 illustrates an example that transcoder 1024 may be used to control the order of delivery of data to a receiver. One multi-lane interface 1000, such as the multi-lane interface 500 of FIG. 5, may include two or more sets of data bits 1002, 1004 for transmission over a corresponding number of lanes May be independently encoded with sequences of symbols 1006, 1008. Data may be provided to a pre-segmented multi-lane interface 1000 with sets of data bits 1002 and 1004 and / or sets of data bits 1002 and 1004 may be provided to a multi- Gt; 1000 < / RTI > The data bits may be allocated between two or more sets of data bits 1002 and 1004, arbitrarily, depending on function, according to design preferences or for convenience and / or for other reasons.

[0089] In the illustrated multi-lane interface 1000, each word, byte, or other data element received in the first clock cycle is sent as a pair of symbol intervals 1012a-1012g on one of the two lanes And may be encoded into two or more symbols that are sequentially transmitted. The receiver may decode the data element when two or more symbols are received from a pair of symbol intervals 1012a through 1012g.

[0090] A multi-lane interface 1020, such as the multi-lane interface 900 of FIG. 9, includes a plurality of sequences 1026, 1028 of symbols transmitted simultaneously through two or more lanes, 1022 and a transcoder 1024 for encoding clock information. The transcoder 1024 may control the order of transmission of data to the receiver by simultaneously transmitting symbols for transmission over the two lanes. In one example, data bits 1022 received in a first clock cycle (bits 0) are transcoded into two symbols and transmitted in parallel on two lanes during a first symbol interval 1030 . Data bits 1022 received in a second clock cycle (bits 1) may be transmitted as two symbols in parallel on two lanes during a second symbol interval 1032. [ The transmission of data on two parallel data lanes may provide specific advantages for timing-sensitive applications such as camera shutter and / or flash control, control signals associated with game applications.

[0091] FIG. 11 illustrates another example of a multi-lane interface 1100 provided in accordance with one or more aspects disclosed herein. In this example, the multi-lane interface 1100 includes at least one N! An encoded lane 1112 and a serial data link 1122. The serial data link 1122 may be a single ended serial link (as illustrated) or a differentially encoded serial data link. The serial data link 1122 may include a serial bus such as an inter-integrated circuit (I2C) bus, a camera control interface (CCI) serial bus, or derivatives of these serial bus technologies. In the example shown, the clock signal 1124 is N! Serializer 1108 of the link and serializer 1118 of the serial link 1122 and the clock signal 1124 need not be transmitted to the receiver 1132 via a separate clock signal lane. Instead, the transcoder 1106 converts N! And inserts the clock information into the sequence of symbols provided through the serializer as differential line drivers of lane 1112. [

At the receiver 1132, the CDR 1136 generates a receiver clock signal 1154 from the detected transitions at the outputs of the receivers 1134. Receiver clock signal 1154 includes N! Lane deserializer 1138 and serial link deserializer 1148. In the example of FIG. In some instances, the CDR 1136 may monitor the output of line receivers 1144 associated with the serial link 1122 to improve the detection of transitions between symbol intervals. N! The lane deserializer 1138 receives the N! And provides deserialized symbol information to a transcoder 1140 that generates output data 1142 that represents the input data 1104 transmitted over the encoded lane 1112.

[0093] In one example, the transmitter 1102 receives 3! And transmits the symbols on the encoded first lane 1112 with three signals. The symbols include embedded clock information, and five signaling states per symbol are available on the first lane 1112. The transmitter may also transmit data on the second lane using the four serial signals transmitted on the wires of the serial link 1122. [ The receiver 1132 may generate a clock signal 1154 from the symbols transmitted on the first lane 1112 where the clock is used to decode / deserialize the data transmitted on both lanes 1112 and 1122 Lt; / RTI > Thus, when used by a serial link 1122, CDR (1136) clock 1154 inverse serializer 1148 with respect to the serial link (1122) of the second lane provided by the 2 ⁴ = 16 per symbol of States. The sum of 5 x 16 = 80 states per symbol is achieved when the clock 1154 provided by the CDR 1136 is used.

[0094] As a comparison, a conventional or traditional 4-wire serial link 1122 can dedicate one of the four wires to carry the clock signal, Lt; / RTI > signals. In this latter configuration, 2 ³ = 8 signaling states per symbol may be provided on the serial link 1122, The total of 5 x 8 = 40 signaling states per symbol is also effected when transmitted in the encoded first lane 1112 as well.

[0095] FIG. 12 is a flowchart 1200 illustrating a method for data communications on an N-wire communication link. The communication link is N! And may include a plurality of connectors carrying encoded symbols using a suitable encoding scheme such as encoding, multiphase encoding, multi-wire differential encoding, and the like. The connectors may include electrically conductive wires, optical signal conductors, semiconducting interconnects, and the like. The method may be performed by one or more processors of the receiving device.

[0096] At step 1202, a first sequence of symbols is received from the first lane of the multi-lane interface. Each symbol in the sequence of symbols may correspond to the signaling state of the N wires of the first lane.

[0097] At step 1204, the clock signal is recovered or extracted from the multi-lane interface. The clock signal may include edges corresponding to a plurality of transitions of the signaling state of the N wires between pairs of consecutive symbols in a first sequence of symbols.

[0098] In step 1206, a first sequence of symbols is converted to a first set of data bits using a clock signal. A first sequence of symbols may be generated by using a transcoder to transform a first sequence of symbols into a set of transition numbers and by converting a set of transition numbers into a set of data bits to obtain a first set of data bits May be converted to a first set of data bits.

[0099] In step 1208, a second set of data bits is derived from one or more signals received from a second lane of the multi-lane interface using a clock signal. The second set of data bits may be derived without using a transcoder.

[00100] According to certain aspects disclosed herein, a first sequence of symbols may be encoded with the _N C ₂ of the differential signal received from the C _{2 N} different pairs of the N wires. Second lane may comprise the M pieces of wires, wherein the second sequence of symbols is encoded into the _{M 2} C differential signals received from _M C ₂ different pairs of two wires M. M and N may have the same or different values.

[00101] According to certain aspects disclosed herein, deriving the second set of data bits comprises receiving serial signals from each of the M wires of the serial interface, and sampling the serial signals according to the clock signal And extracting a second set of data bits. Deriving a second set of data bits comprises receiving M / 2 differential signals from the M wires of the serial interface and sampling a second set of data bits by sampling M / 2 differential signals according to the clock signal, Lt; / RTI >

[00102] According to certain aspects disclosed herein, a clock signal provides a transition of a clock signal corresponding to a detected transition in the signaling state of the N wires or in the signaling state of one or more of the wires in the second lane Or the like. The clock signal may include edges corresponding to one or more transitions of the signaling state of at least one wire of the second lane of the multi-lane interface.

[00103] According to certain aspects disclosed herein, a first sequence of symbols is encoded with _N C ₂ differential signals. _{Each of the N} C ₂ differential signals may be received from a different pair of N wires. The second sequence of symbols may be encoded with _M C ₂ differential signals received from the _M wires of the second lane. C _{2 M} each of the differential signal may be received from a different pair of the two M wire. A first sequence of symbols may be converted to a first set of data bits using a transcoder circuit. A second sequence of symbols may be converted to a second set of data bits using the same transcoder circuit.

[00104] According to certain aspects disclosed herein, a transition of one or more signaling states of N wires and M wires occurs between each successive pair of symbols in a first sequence of symbols do. Each of the first sequences of symbols may be transmitted at different symbol intervals. A first set of data bits and a second set of data bits received in each symbol interval may be combined to obtain a data element completed from each symbol interval.

[00105] FIG. 13 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1300 using processing circuitry 1302. The processing circuitry typically includes a processor 1316, which may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. Processing circuitry 1302 may be implemented using a bus architecture generally represented by bus 1320. [ The bus 1320 may include any number of interconnect busses and bridges depending on the particular application of the processing circuit 1302 and overall design constraints. Bus 1320 may include one or more processors and / or hardware modules, modules and / or circuits 1304, 1306 and 1308 represented by processor 1316, connectors or wires Link interface circuitry 1312 and a processor-readable / computer-readable storage medium 1318 that are configurable to communicate over a network interface (e.g., a lane interface 1314). The bus 1320 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described.

[0106] Processor 1316 is responsible for general processing, including the execution of software stored on computer-readable storage medium 1318. The software, when executed by the processor 1316, causes the processing circuit 1302 to perform the various functions described above for any particular device. The computer-readable storage medium 1318 also includes instructions for performing the steps of, when executing the software, including data decoded from symbols transmitted via the connectors 1314, to be used to store data manipulated by the processor 1316 . The processing circuit 1302 further includes at least one of the modules and / or circuits 1304, 1306, and 1308. Modules and / or circuits 1304,1306 and 1308 may be software modules stored in and stored on a computer-readable storage medium 1318 to be coupled to a processor 1316, Or more of the hardware modules, or some combination thereof. The modules and / or circuits 1304, 1306, and / or 1308 may include microcontroller commands, state machine configuration parameters, or some combination thereof.

In an arrangement, the apparatus 1300 for wireless communication comprises modules and / or circuits 1306, 1312 configured to receive a first sequence of symbols from a first lane of a multi-lane interface 1314, , A module 1306 configured to recover a clock signal from the multi-lane interface 1314 and / or circuitry 1306. The clock signal may comprise a plurality of signaling states of the N signals between pairs of consecutive symbols in a first sequence of symbols And / or circuits (1304 and / or 1308) configured to transform a first sequence of symbols into a first set of data bits using a clock signal, Configured to derive a second set of data bits from one or more signals received from a second lane of the multi-lane interface 1314 And / or 1308). In one example, the circuits illustrated in FIGS. 6-9 and 11 provide logic implementing the various functions performed by processing circuitry 1302. In one embodiment,

[00108] In one aspect of the present disclosure, one or more instructions are stored or held in computer-readable storage medium 1318. Instructions, when executed by at least one processor 1316 of the processing circuit 1302, cause the processing circuit 1302 to receive a first sequence of symbols from a first lane of the multi-lane interface 1314, Restores the clock signal from the multi-lane interface 1314 and the clock signal includes edges corresponding to a plurality of transitions of the signaling state of the N wires between pairs of consecutive symbols in a first sequence of symbols - one or more signals received from the second lane of the multi-lane interface 1314 using a clock signal to cause a first sequence of symbols to be converted to a first set of data bits using a clock signal, To derive a second set of data bits from the second set of data bits. Each symbol in the sequence of symbols may correspond to the signaling state of the N wires.

The above-described means may be implemented using, for example, some combination of processors 206 or 236, physical layer drivers 210 or 240, and storage media 208 and 238.

[00110] Figure 14 is a flowchart 1400 illustrating a method for data communications on an N-wire communication link. The communication link is N! And may include a plurality of connectors carrying encoded symbols using a suitable encoding scheme such as encoding, multiphase encoding, multi-wire differential encoding, and the like. The connectors may include electrically conductive wires, optical signal conductors, semiconducting interconnects, and the like. The method may be performed by one or more processors of the receiving device.

[00111] In step 1402, the clock information is inserted into the first sequence of symbols that encode the first data bits. Each symbol of the first sequence of symbols may correspond to the signaling state of the N wires of the first lane of the multi-lane interface. The clock information may be encoded by using a transcoder to transform the first data bits into a set of transition numbers and may convert a set of transition numbers to obtain a first sequence of symbols. The second data bits may be encoded in a second sequence of symbols without using a transcoder.

[00112] In step 1404, a first sequence of symbols is transmitted on the first lane.

[00113] In step 1406, a second sequence of symbols is transmitted on the second lane of the multi-lane interface. The second sequence of symbols may be encoded with the second data bits and without the embedded clock information.

[00 114] According to certain aspects disclosed herein, a first sequence of symbols may be transmitted by transmitting the first sequence of _N C ₂ of the differential signal symbols on _N C ₂ different pairs of the N wires. The second lane may comprise M wires. A second sequence of symbols may be sent to the _{M 2} C ₂ C differential signals on _M different pairs of two wires M. The values of M and N may be the same or different.

[00115] According to certain aspects disclosed herein, a second sequence of symbols may be transmitted on the M wires of the serial bus. Sending a second sequence of symbols may comprise transmitting a second set of data in M / 2 differential signals.

[00116] According to certain aspects disclosed herein, each symbol of the first sequence of symbols is transmitted at a different symbol interval. Inserting the clock information may include causing a transition of the signaling state of the N wires or the signaling state of one or more wires of the second lane between each pair of consecutive symbols in a first sequence of symbols .

[00117] According to certain aspects disclosed herein, a single transcoder circuit may be used to encode the first data bits in a first sequence of symbols and the second data bits in a second sequence of symbols.

[00118] In accordance with certain aspects disclosed herein, inserting clock information may be performed in a signaling state of N wires in each pair of consecutive symbols in a first sequence of symbols, or a continuous symbol in a second sequence of symbols To cause a transition of the signaling state of the M wires of the second lane in each pair of the first and second lanes. The clock information may relate to a transmission clock used to encode both the first sequence of symbols and the second sequence of symbols.

[00119] According to certain aspects disclosed herein, a data element may be partitioned to obtain a first set of data bits and a second set of data bits. A first symbol corresponding to a first set of data bits may be transmitted on a first lane concurrently with transmission of a second symbol corresponding to a second set of data bits on a second lane.

[00120] FIG. 15 is a diagram illustrating a simplified example of a hardware implementation for an apparatus 1500 employing a processing circuit 1502. The processing circuitry typically includes a processor 1516 that may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. The processing circuitry 1502 may be implemented using a bus architecture generally represented by bus 1520. [ The bus 1520 may include any number of interconnect buses and bridges depending on the particular application of the processing circuitry 1502 and overall design constraints. Bus 1520 may include one or more processors and / or hardware modules, modules and / or circuits 1504, 1506 and 1508 represented by processor 1516, connectors or wires 1514 ) And the processor-readable / computer-readable storage medium (1518). Bus 1520 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described.

[00121] Processor 1516 is responsible for general processing, including execution of software stored on computer-readable storage medium 1518. The software, when executed by the processor 1516, causes the processing circuit 1502 to perform the various functions described above for any particular device. The computer-readable storage medium 1518 may also include other data that may be used to store data manipulated by the processor 1516, including data decoded from symbols transmitted via the connectors 1514, . The processing circuitry 1502 further includes at least one of the modules and / or circuits 1504, 1506, and 1508. Modules and / or circuits 1504,1506 and 1508 may be implemented as software modules stored in computer-readable storage medium 1518 and stored in processor 1516, coupled to processor 1516, Or more of the hardware modules, or some combination thereof. The modules and / or circuits 1504, 1506, and / or 1508 may include microcontroller commands, state machine configuration parameters, or some combination thereof.

In an arrangement, the apparatus 1500 for wireless communication comprises a module and / or circuit 1504 configured to insert the encoded information of the first data bits into a first sequence of symbols, Modules and / or circuits (1506 and / or 1512) configured to transmit a first sequence of symbols on a first lane, modules configured to transmit a second sequence of symbols on a second lane of a multi-lane interface, and / Circuits 1504, 1506, and / or 1508. In one example, the circuits illustrated in Figs. 6-9 and 11 provide logic to implement various functions performed by the processing circuit 1502. Fig.

[00123] In an aspect of the present disclosure, one or more instructions are stored or held in a processor-readable / computer-readable storage medium 1518. Instructions, when executed by at least one processor 1516 of the processing circuit 1502, cause the processor 1516 to cause the first data bits to insert the encoded clock information into the first sequence of symbols, To transmit a first sequence of symbols on a first lane of interface 1514 and to transmit a second sequence of symbols on a second lane of multi-lane interface 1514. [ Each symbol of the first sequence of symbols may correspond to the signaling state of the N wires of the first lane of the multi-lane interface 1514. [ The second sequence of symbols may be encoded with the second data bits and without the embedded clock information.

[00124] The above-described means may be implemented using, for example, some combination of processors 206 or 236, physical layer drivers 210 or 240, and storage media 208 and 238.

A multi- wire symbol Transition  Illustrative description of the link

[00125] As described above, multi-wire symbol transition clocking can be implemented by inserting a clock into symbol transitions. However, the inserted clock requires the clock and data recovery (CDR) logic / circuit of the receiving device to recover the inserted clock from the symbol transitions. Such CDR logic / circuit may be complex or costly to implement by some receiving devices. Inserted clocks may also experience symbol sleep errors due to excessive jitter, lane skews, signal spikes, and other reasons.

[00126] In one aspect of the present disclosure, N! The multi-wire bus / link may be used to facilitate transmission of symbols to be inserted into the embedded / clocked symbol transitions, while a dedicated clock line is used to transmit the dedicated clock. In other aspects of the present disclosure, the bus / link may be a single-ended multi-wire bus / link. The dedicated clock transmitted over the dedicated clock line enables the receiver to decode the transmitted symbols over the multi-wire bus / link without the need for using the CDR logic / circuit and relying on the inserted clock. Thus, the use of a dedicated clock line to receive a dedicated clock allows the receiver to abandon the implementation of the CDR logic / circuit, thereby minimizing the complexity and cost associated with such implementation, Allows to reduce sleep errors.

[00127] In another aspect, in a system that uses a dedicated clock line to transmit / receive a clock signal, a separate clock need not be encoded / inserted in the symbol transitions of the sequence of symbols to be transmitted. Thus, it is not mandatory for the system to guarantee a transition between each symbol in the sequence of symbols, and thus the system can interleave different types of symbols on the data lane and across multiple data lanes. Also, since no clock recovery from the symbol transitions can occur in such a system, the circuit / modules for converting the primitive symbols into symbols with guaranteed transitions can be omitted from the transmitter, and symbols with guaranteed transitions / RTI > circuitry / modules for converting signals to raw symbols can be omitted at the receiver, thus minimizing the complexity and cost associated with implementing such circuits / modules.

[00128] In a further aspect, in a system that uses a dedicated clock line to transmit / receive a clock signal, the clock signal is transmitted separately from the data signal, and thus the direction of the data signal transmission is determined by the direction of the clock signal transmission It is not constrained. Thus, such a system allows the clock signal to be transmitted from the first device to the second device over the dedicated clock line, while the data / symbols associated with the clock signal are transmitted from the second device to the first device. In addition, such systems can now use multi-wire bus / link and / or dedicated clock lines for bi-directional transmission. Thus, both the first device and the second device utilize a multi-wire bus / link for transmission by interleaving the lines of the multi-wire bus / link and / or by alternately transmitting a dedicated clock over the dedicated clock line .

[00129] FIG. 16 is a diagram illustrating a further example of a multi-lane interface 1600 provided between two devices 1602 and 1632. At the transmitter 1602, a transcoder 1606 generates a symbol (e.g., a symbol) to be transmitted over a set of N wires on a lane (or "multi- wire link") 1612 using, Gt; N, < / RTI > where N is an integer greater than two. The clock information may be derived from a first transmission clock (e.g., DDRCLK X) 1624 or a second transmission clock (e.g., DDRCLK Y) 1626 and the signaling state transition may be derived from _N C ₂ by ensuring that occur on at least one of the two signals it may be encoded into a sequence of transmitted symbols from the _N C ₂ of the differential signals on the N pieces of wires. N! If the encoding is used to drive N wires, each bit of the symbol is transmitted as a differential signal by one of a set of line drivers 1610, where the set of line drivers 1610 The differential drivers are coupled to different pairs of N wires. The number of available combinations of wire pairs and signals can be calculated to be _N C ₂ , and the number of available combinations determines the number of signals that can be transmitted over the N wires. The number of data bits 1604 that can be encoded into symbols may be computed based on the number of available signaling states available during each symbol transmission interval.

The termination impedance (typically resistive) couples each of the N wires to a common center point of the termination network 1628. It will be appreciated that the signaling states of the N wires reflect the combination of currents in the termination network 1628 due to differential drivers 1610 coupled to each wire. It will be further appreciated that the center point of the termination network 1628 is a null point, whereby the currents in the termination network 1628 cancel each other at a central point.

[00131] At least one of the _N C ₂ signals in the link transitions between consecutive symbols. Efficiently, the transcoder 1606 ensures that a transition occurs between each pair of symbols transmitted on the N wires, by generating a sequence of symbols where each symbol is different from its previous full symbol do. 16, lane 1612 has N = 4 wires, and a set of _four wires has ₄ C ₂ = 6 differential signals can be carried. The transcoder 1606 may use a mapping scheme to generate primitive symbols for transmission on the N wires available on the lane 1612. [ Transcoder 1606 and serializer 1608 collaborate to generate raw symbols for transmission based on input data bits 1604. At the receiver 1632, the transcoder 1640 may use the mapping to determine, for example, a transition number that characterizes the difference between consecutive primitive symbols, i. E., The symbols in the lookup table. Transcoders 1606 and 1640 operate based on the assumption that every successive pair of primitive symbols includes two different symbols.

[00132] The transcoder 1606 of the transmitter 1602 may select between N! -1 states available in every respective symbol transition. In one example, 4! The system provides 4! -1 = 23 signaling states for the next symbol to be transmitted in each symbol transition. The bit rate may be calculated as log ₂ (available_states) per cycle of the first transmission clock 1624 or the second transmission clock 1626. In systems using double data rate (DDR) clocking, symbol transitions occur at both the rising and falling edges of the first transmission clock 1624 or the second transmission clock 1626. In one example, two or more symbols may be transmitted per word (i.e., per transmission clock cycle), so that the total available states of the transmission clock cycle are ( _N C ₂ -1) ² = (23) ² = 529, and the number of data bits 1604 that can be transmitted per symbol may be calculated as log ₂ (529) = 9.047 bits.

[00133] In an aspect, a second transmit clock 1626 used to encode data 1604 may be transmitted to receiver 1632 using line driver 1620. For example, the line driver 1620 may generate a clock signal based on the second transmission clock 1626 and transmit the clock signal via the dedicated clock line 1622. [ The dedicated clock line 1622 is separate and parallel to the lane / multi-wire link 1612 and may be limited to communicating clock signals between the transmitter 1602 and the receiver 1632.

[00134] Receiver 1632 receives a sequence of symbols using a set of line receivers 1634, where each receiver in a set of line receivers 1634 receives a signaling state for one pair of N wires . Thus, _N C ₂ receivers are used in lane 1612, where N represents the number of wires in lane 1612. _{The N} C ₂ receivers 1634 generate a corresponding number of primitive symbols as outputs.

[00135] Receiver 1632 receives the clock signal transmitted via dedicated clock line 1622 using line receiver 1644. Upon receipt of the clock signal on dedicated clock line 1622, line receiver 1644 generates a receive clock (e.g., DDRCLK Y) 1656 corresponding to the second transmit clock 1626.

[00136] In the illustrated example, lane 1612 has N = 4 wires, and signals received on the four wires of lane 1612 produce a state transition signal provided to deserializer 1638 6 receivers ( ₄ C ₂ = 6). ≪ / RTI > Deserializer 1638 deserializes the symbols based on the state transition signal from the set of line receivers 1634 and the receive clock 1656 (corresponding to the second transmit clock 1626). Receive clock 1656 may be used by external circuitry to receive data provided by transcoder 1640. [ Transcoder 1640 decodes the received block of symbols from deserializer 1638 by comparing each subsequent symbol with its previous full previous. The transcoder 1640 generates output data 1642 corresponding to the data 1604 provided to the transmitter 1602. [ Thus, because receiver 1632 may utilize a second transmit clock 1626 provided over a dedicated clock line 1622 to decode received symbols corresponding to data 1604, Lt; RTI ID = 0.0 > 1624 < / RTI > Thus, the receiver 1632 can ignore the first transmission clock 1624.

[00137] As illustrated in the example of FIG. 16, lanes (or "multi-wire links") 1612 may be operated in accordance with the following examples. In one example, data bits 1604 for transmission over a lane (lane X in this example) 1612, when transmitted in a predetermined sequence, cause a transition in the signaling state to be transmitted to four wires Lt; RTI ID = 0.0 > 1606, < / RTI > Serializer 1608 generates a sequence of symbol values provided to line drivers 1610 that determine the signaling state of the four wires of lane 1612 during each symbol interval.

[00138] In another example, data bits 1604 are received by a transcoder 1606 of a lane (lane X in this example) 1612. The transcoder 1606 generates a set of serialized transitional numbers by the serializer 1608 and the serializer 1608 generates a set of transition numbers for each of the four lines of the lane 1612, Converts the set of transition numbers into a sequence of symbol values provided to drivers 1610. [ The sequence of primitive symbols ensures that transitions in the signaling state occur in at least one signal transmitted on four wires of lane 1612 between each pair of consecutive symbols.

[00139] In an aspect, at least one line / wire of the lane (or "multi-wire link") 1612 is bidirectional. Thus, the transmitter 1602 may be configured to receive a sequence of symbols transmitted from the receiver 1632 over at least one bi-directional line / wire of the lane 1612. In a further aspect, the dedicated clock line 1622 is bi-directional and may be driven by either the transmitter 1602 or the receiver 1632 that transmit via the lane 1612. For example, the transmitter 1602 may be configured to receive a dedicated clock signal from the receiver 1632 via a dedicated clock line 1622. The dedicated clock signal may be associated with a transmission clock that is used to encode a sequence of symbols transmitted by the receiver through at least one bidirectional line / wire of the lane 1612. [

[00140] FIG. 17 illustrates examples of transmitting symbols on multiple data lanes using a dedicated clock line. In an example 1700, symbols of a first type 1710 are transmitted on a first data lane (data lane 1) 1704 and symbols of a second type 1712 are transmitted on a second data lane (data lane 2) 1706, and the symbols of the third type 1714 are transmitted on the third data lane (data lane 3) 1708. [ All of the symbols of the first type 1710, the second type 1712 and the third type 1714 are transmitted on their respective data lanes in accordance with a clock signal transmitted separately on a dedicated clock line 1702 .

[00141] As described above, in a system that uses a dedicated clock line to transmit / receive clock signals, a separate clock need not be encoded / inserted in the symbol transitions of the sequence of symbols to be transmitted. Thus, the transmitter need not guarantee a transition of the signaling state between each symbol in the sequence of symbols. Thus, referring to example 1750, a transmitter may interleave different types of symbols on the data lane and across multiple data lanes. For example, a symbol of a first type 1760, a symbol of a second type 1762, and a symbol of a third type 1764 may be interleaved and transmitted on a first data lane (data lane 1) 1754 . Further, the symbols of the second type 1762, the symbols of the third type 1764, and the symbols of the first type 1760 may be interleaved and transmitted on the second data lane (data lane 2) 1756 . Further, symbols of the third type 1764, symbols of the first type 1760, and symbols of the second type 1762 may be interleaved and transmitted on the third data lane (data lane 3) 1758 .

In one aspect, the symbols of the second type 1762 and the symbols of the third type 1764 can be transmitted on a data lane (e.g., on the first data lane 1754) without a transition of the signaling state between the symbols A symbol of the first type 1760 and a symbol of the second type 1762 may be transmitted on the data lane (e.g., on the second data lane 1756) without a transition of the signaling state between the symbols The symbol of the second type 1762, the symbol of the third type 1764 and the symbol of the first type 1760 may be used as data of the first type 1760 without any transition of the signaling state between any pair of symbols. All of the symbols of the first type 1760, the second type 1762, and the third type 1764 may be transmitted on a lane (e. G., On a third data lane 1758 (see 1770 and 1772) May be transmitted on each of the data lanes in accordance with a clock signal transmitted separately on clock line 1752 have.

[00143] FIG. 18 illustrates examples of multi-wire transcoding using dedicated clock lines. In a first example 1800, at the transmitter, the data bits to be transmitted are received by a bit-to-transition symbol converter (bits to T) 1802. Based on the data bits, bit to T 1802 generates a set of primitive transition symbols 1804 for transmission over multi-wire link 1820. A set of primitive transition symbols 1804 is provided to a transition symbol-to-symbol converter (T to S) 1806. The T-to-S 1806 selects the raw transition symbols for transmission so that a transition in the signaling state is guaranteed between each symbol, thus allowing clock information to be encoded / inserted in the symbol transitions. The symbols output by T-S 1806 may be serialized by serializer (SER) 1808 based on the clock signal transmitted on dedicated clock line 1812. The SER 1808 generates a sequence of symbols that determines the signaling state of the wires of the multi-wire link 1820. A sequence of symbols 1814 is provided to the line drivers 1810 for transmission on the multi-wire link 1820.

[00144] Continuing with the first example 1800, at the receiver, the process described above for the transmitter is reversed. Deserializer (DES) 1824 receives the sequence of symbols 1814 via line receivers 1822. DES 1824 deserializes the received symbols based on the clock signal received on dedicated clock line 1812. The output of DES 1824 is provided to a symbol-to-transition symbol converter (S to T) 1826. S to T 1826 reconstructs the raw transition symbols 1804 based on transitions existing between each deserialized symbol. The transition symbol-to-bits converter (T-to-bits) 1828 then converts the recovered raw transition symbols to data bits (bits).

[00145] As described above, in a system that uses a dedicated clock line to transmit / receive clock signals, a separate clock need not be encoded / inserted into the symbol transitions of the sequence of symbols to be transmitted. Thus, with reference to a second example 1850 of multi-wire transcoding using a dedicated clock line, if no clock information is encoded / inserted into the symbol transitions, the transmitter will switch between each symbol in the sequence of symbols It is not necessary to guarantee the transition of Also, since no clock information is inserted into the symbol transitions at the transmitter or at the receiver it will not be recovered from the symbol transitions, the circuits / modules for converting the primitive symbols into symbols with guaranteed transitions are omitted from the transmitter And circuits / modules for converting symbols with guaranteed transitions to raw symbols may be omitted at the receiver, thus minimizing the complexity and cost associated with implementing such circuits / modules.

[00146] For example, in a second example 1850, at the transmitter, the data bits to be transmitted are received by a bit-to-transition symbol converter (bit to T) 1852. Based on the data bits, bit to T 1852 generates a set of primitive transition symbols 1854 for transmission over multi-wire link 1870. The transmitter does not need to guarantee a transition of the signaling state between each symbol of the set of symbols to be transmitted, since no clock information will be inserted into the encoding / them in the symbol transitions. Thus, a transition symbol-to-symbol converter (e.g., T to S 1806 of the first example 1800) may be omitted from the transmitter of the second example 1850, and the raw transition symbols 1854 may be directly And may be supplied to a serializer (SER) 1858. Primitive transition symbols 1854 may be serialized by SER 1858 based on the clock signal transmitted on dedicated clock line 1862. The SER 1858 generates a sequence of symbols that determines the signaling state of the wires of the multi-wire link 1870. A sequence of symbols 1854 is provided to the line drivers 1860 for transmission on the multi-wire link 1870.

[00147] Continuing with the second example 1850, at the receiver, the process described above for the transmitter is reversed. Deserializer (DES) 1874 receives a sequence of symbols 1854 via line receivers 1872. [ DES 1874 deserializes the received symbols based on the clock signal received on dedicated clock line 1862 to recover the set of raw transition symbols 1854. In particular, because no clock information is embedded in the encoding / their symbol transitions, the receiver need not reconstruct the raw transition symbols based on the transitions existing between each deserialized symbol. Thus, the symbol-to-transition symbol converter (e.g., S to T 1826 of the first example 1800) may be omitted in the receiver of the second example 1850. The transition symbol-to-bits converter (T-to-bits) 1878 converts the recovered original transition symbols into data bits (bits). In an aspect, the second example 1850 improves throughput because it allows one extra state per symbol to be transmitted.

Exemplary reception device  And methods thereon

[00148] Figure 19 illustrates operations related to communicating data bits over a multi-wire link in accordance with one or more aspects of the present disclosure (e.g., aspects related to the method of Figure 20 described below) (Receiving device) 1900 that is configured to support the device. Apparatus 1900 includes a communication interface (e.g., at least one transceiver) 1902, a storage medium 1904, a user interface 1906, a memory device 1908, and a processing circuitry 1910.

[00149] These components may be arranged to be coupled to one another and / or in electrical communication with one another via a signaling bus or other suitable component, generally represented by the connection lines of FIG. The signaling bus may include any number of interconnect busses and bridges depending on the particular application of the processing circuitry 1910 and overall design constraints. A signaling bus is coupled to the processing circuitry 1910 so that each of the communication interface 1902, the storage medium 1904, the user interface 1906 and the memory device 1908 is coupled to and / Link together. The signaling bus may also link various other circuits (not shown), such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described.

[00150] The communication interface 1902 may be adapted to facilitate wireless communication of the device 1900. For example, communication interface 1902 may include circuitry and / or code (e.g., instructions) adapted to facilitate communication of information in one direction or two directions to one or more communication devices in a network. Communication interface 1902 may be coupled to one or more antennas 1912 for wireless communication within a wireless communication system. The communication interface 1902 may be comprised of one or more independent receivers and / or transmitters as well as one or more transceivers. In the illustrated example, the communication interface 1902 includes a transmitter 1914 and a receiver 1916.

[00151] Memory device 1908 may represent one or more memory devices. As indicated, memory device 1908 may retain network-related information 1918 along with other information used by device 1900. In some implementations, the memory device 1908 and the storage medium 1904 are implemented as a common memory component. The memory device 1908 may also be used to store data manipulated by the processing circuitry 1910 of the device 1900 or some other component.

[00152] The storage medium 1904 may include one or more computer-readable media for storing code, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, Capable, machine-readable, and / or processor-readable devices. The storage medium 1904 may also be used to store data manipulated by the processing circuitry 1910 when executing the code. The storage medium 1904 can include any or all of the various types of media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other media capable of storing, May be available media.

As a non-limiting example, the storage medium 1904 can be a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic strip), an optical disk (e.g., a compact disk (CD) ), A smart card, a flash memory device (e.g., a card, a stick or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM) A removable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing code that can be accessed and read by a computer. The storage medium 1904 may be embodied in an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium on packaging materials. In view of the above, in some implementations, the storage medium 1904 may be a non-temporary (e.g., type) storage medium.

The storage medium 1904 can be coupled to the processing circuitry 1910 so that the processing circuitry 1910 can read information from, and write information to, the storage medium 1904 . In other words, the storage medium 1904 may be any type of storage medium such as, for example, one in which at least one storage medium is integrated into the processing circuitry 1910 and / or at least one storage medium is separated from the processing circuitry 1910 The storage medium 1904 may be coupled to the processing circuitry 1910 such that the storage medium 1904 is at least accessible by the processing circuitry 1910, including, for example, external to the device 1900, distributed across multiple entities, .

[00155] The code and / or instructions stored by storage medium 1904 may cause processing circuitry 1910 to perform various functions and / or operations as described herein, when executed by processing circuitry 1910 To perform one or more of the following. For example, the storage medium 1904 may be configured to coordinate operations in one or more hardware blocks of the processing circuitry 1910, as well as a communication interface 1902 for wireless communication using their respective communication protocols. As shown in FIG.

[00156] Processing circuitry 1910 is generally adapted for processing involving the execution of such codes / instructions stored on storage medium 1904. The term "code" or "instructions ", as used herein, refers to a program, instruction, set of instructions, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, , Data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, And the like, without departing from the scope of the invention.

[00157] Processing circuit 1910 is arranged to acquire, process and / or transmit data, control data access and storage, issue commands, and control other desired operations. The processing circuitry 1910 may comprise circuitry configured to implement the desired code provided by suitable media in at least one example. For example, the processing circuitry 1910 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable code. Examples of the processing circuitry 1910 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, Or any combination of these designed to perform the functions described herein. A general purpose processor may include any conventional processor, controller, microcontroller, or state machine as well as a microprocessor. The processing circuitry 1910 may also include a combination of computing components, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, May be implemented as various configurations of other numbers. These examples of processing circuit 1910 are for illustration purposes and other suitable configurations within the scope of this disclosure are also contemplated.

[00158] According to one or more aspects of the invention, the processing circuitry 1910 may include, without being limited to, the features, processes, functions, operations, and functions of any or all of the devices described herein 0.0 > and / or < / RTI > routines. As used herein, the term "adapted " in connection with processing circuitry 1910 is intended to encompass all types of processing, circuitry, and / or code that causes processing circuitry 1910 to perform particular processes, functions, operations and / or routines in accordance with the various aspects described herein And / or < / RTI > programmed to perform the functions described herein.

[00159] According to at least one example of an apparatus 1900, a processing circuit 1910 may be configured to perform the functions, processes, functions, operations and / or routines described herein (e.g., A symbol receiving circuit / module 1920 adapted to perform any or all of the described functions, processes, functions, operations and / or routines, a clock receiving circuit / module 1922, May include one or more of circuit / module 1924, symbol transmission circuit / module 1926, and clock transmission circuit / module 1928.

The symbol receiving circuit / module 1920 may include circuitry and / or instructions (e.g., storage medium 1904) adapted to perform several functions related to receiving a sequence of symbols over a multi-wire link (E.g., symbol receive instructions 1930 stored on the memory).

[00161] Clock receiving circuit / module 1922 may include circuitry and / or instructions (e.g., on storage medium 1904) adapted to perform several functions related to receiving a clock signal via a dedicated clock line (E.g., clock receive instructions 1932 stored in memory), where the dedicated clock line is separate from and parallel to the multi-wire link.

[00162] Symbol decoding circuitry / module 1924 includes circuitry and / or instructions (e.g., storage medium 1904) adapted to perform several functions related to decoding a sequence of symbols using, for example, Stored symbol decoding instructions 1934). In an aspect, the second clock signal may be inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols. Thus, the symbol decoding circuit / module 1924 can be configured to perform decoding by decoding a sequence of symbols using a clock signal received over a dedicated clock line, ignoring the second clock signal. The symbol decoding circuit / module 1924 can be configured to perform decoding by converting the sequence of symbols into a set of data bits using a clock signal. The symbol decoding circuit / module 1924 may be configured to perform the transform by using a transcoder to transform the sequence of symbols into a set of transition numbers and by converting the set of transition numbers into a set of data bits.

[00163] The symbol transmission circuit / module 1926 may include, for example, a number of transmitters / modulators 1926 associated with transmitting a second sequence of symbols over at least one bi-directional line of a multi-wire link based on a clock signal received via a dedicated clock line May include circuitry and / or instructions (e.g., symbol transmission instructions 1936 stored on storage medium 1904) adapted to perform the functions.

[00164] The clock transmission circuit / module 1928 may include circuitry and / or instructions (e.g., storage medium 1904 (E.g., clock transmission instructions 1938 stored on a memory). The third clock signal may be associated with a transmission clock that is used to encode data bits in a sequence of symbols transmitted by symbol transmission circuit / module 1926 through at least one bi-directional line of the multi-wire link.

As noted above, the instructions stored by the storage medium 1904, when executed by the processing circuitry 1910, cause the processing circuitry 1910 to perform various functions and / or processes described herein To perform one or more of the operations. For example, the storage medium 1904 may include one or more of the following: symbol receive instructions 1930, clock receive instructions 1932, symbol decoding instructions 1934, symbol transmit instructions 1936, and clock transmit instructions 1938 One or more.

[00166] Figure 20 is a flow diagram 2000 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a receiving device (e.g., device 100 of FIG. 1, receiver 1632 of FIG. 16, or device 1900 of FIG. 19).

[00167] The receiving device receives (2002) a sequence of symbols over a multi-wire link (eg, multi-wire link 1612) from a transmitting device (eg, transmitter 1602). Each symbol in the sequence of symbols may correspond to the signaling state of the N wires of the multi-wire link, where N is an integer greater than one. The receiving device further receives a clock signal (e.g., DDRCLK Y 1626) via a dedicated clock line (e.g., dedicated clock line 1622), wherein the dedicated clock line is separate from the multi-wire link It is in parallel with him (2004). The receiving device also decodes the sequence of symbols using the clock signal (2006).

[00168] In an aspect, a second clock signal (e.g., DDRCLK X 1624) is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols. Thus, the receiving device decodes the sequence of symbols using the clock signal received over the dedicated clock line, ignoring the second clock signal.

[00169] In an aspect, a receiving device decodes a sequence of symbols by converting a sequence of symbols into a set of data bits using a clock signal. In a further aspect, the receiving device performs translation by using a transcoder (e.g., transcoder 1640) to convert a sequence of symbols into a set of transition numbers and a set of transition numbers into a set of data bits .

[00170] In an aspect, at least one line of the multi-wire link is bidirectional. The receiving device may transmit a second sequence of symbols over at least one bi-directional line based on the clock signal received over the dedicated clock line (2008). In a further aspect, both the receiving device and the transmitting device can utilize the multi-wire link for bidirectional transmissions by interleaving the lines of the multi-wire link.

[00171] In another aspect, the dedicated clock line is bi-directional and may be driven from any device transmitting over a multi-wire link. The receiving device may transmit the third clock signal on a dedicated clock line (2010). The third clock signal may be associated with a transmission clock that is used to encode data bits in a sequence of symbols transmitted by the receiving device over at least one bi-directional line. In a further aspect, both the receiving device and the transmitting device may utilize a dedicated clock line by alternately transmitting a dedicated clock signal through a dedicated clock line.

Exemplary transmission device  And methods thereon

[00172] FIG. 21 illustrates operations related to communicating data bits over a multi-wire link in accordance with one or more aspects of the present disclosure (eg, aspects related to the method of FIG. 22 described below) (Sending device) 2100 that is configured to support the device. Apparatus 2100 includes a communication interface (e.g., at least one transceiver) 2102, a storage medium 2104, a user interface 2106, a memory device 2108, and a processing circuit 2110.

[00173] These components may be arranged to be coupled to each other and / or in electrical communication with one another via a signaling bus or other suitable component, generally represented by the connection lines of FIG. The signaling bus may include any number of interconnect busses and bridges depending on the particular application of the processing circuit 2110 and overall design constraints. The signaling bus is coupled to the processing circuit 2110 so that each of the communication interface 2102, the storage medium 2104, the user interface 2106, and the memory device 2108 is coupled to and / Link together. The signaling bus may also link various other circuits (not shown), such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described.

[00174] The communication interface 2102 may be adapted to facilitate wireless communication of the device 2100. For example, the communication interface 2102 may include circuitry and / or code (e.g., instructions) adapted to facilitate communication of information bidirectionally to one or more communication devices in a network. Communication interface 2102 may be coupled to one or more antennas 2112 for wireless communication within a wireless communication system. The communication interface 2102 may be comprised of one or more of the independent receivers and / or transmitters as well as one or more transceivers. In the illustrated example, the communication interface 2102 includes a transmitter 2114 and a receiver 2116.

[00175] The memory device 2108 may represent one or more memory devices. As indicated, memory device 2108 may retain network-related information 2118 along with other information used by device 2100. In some implementations, the memory device 2108 and the storage medium 2104 are implemented as a common memory component. The memory device 2108 may also be used to store data manipulated by the processing circuit 2110 of the device 2100 or some other component.

[00176] The storage medium 2104 can include one or more computer-readable instructions for storing code, such as processor executable code or instructions (eg, software, firmware), electronic data, databases, Capable, machine-readable, and / or processor-readable devices. The storage medium 2104 may also be used to store data manipulated by the processing circuit 2110 when executing code. The storage medium 2104 can include any or all of any of the various types of media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other media capable of storing, May be available media.

As a non-limiting example, the storage medium 2104 can be a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic strip), an optical disk (e.g., a compact disk (CD) ), A smart card, a flash memory device (e.g., a card, a stick or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM) A removable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing code that can be accessed and read by a computer. The storage medium 2104 may be embodied as an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium on packaging materials. In view of the above, in some implementations, the storage medium 2104 may be a non-temporary (e.g., type) storage medium.

The storage medium 2104 can be coupled to the processing circuit 2110 so that the processing circuit 2110 can read information from, and write information to, the storage medium 2104 . In other words, the storage medium 2104 can be any type of storage medium such as those in which at least one storage medium is integrated into the processing circuit 2110 and / or at least one storage medium is / The storage medium 2104 may be coupled to the processing circuitry 2110 such that the storage medium 2104 is at least accessible by the processing circuitry 2110, including, for example, external to the device 2100, distributed across multiple entities, .

[00179] The code and / or instructions stored by storage medium 2104 may cause processing circuitry 2110 to perform various functions and / or operations as described herein, when executed by processing circuitry 2110 To perform one or more of the following. For example, the storage medium 2104 may be configured to coordinate operations in one or more hardware blocks of the processing circuit 2110, as well as to communicate with the communication interface 2102 for wireless communication using their respective communication protocols. As shown in FIG.

[00180] Processing circuit 2110 is generally adapted for processing involving the execution of such codes / instructions stored on storage medium 2104. The term "code" or "instructions ", as used herein, refers to a program, instruction, set of instructions, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, , Data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, And the like, without departing from the scope of the invention.

[00181] Processing circuit 2110 is arranged to acquire, process and / or transmit data, control data access and storage, issue commands, and control other desired operations. The processing circuit 2110 may comprise circuitry configured to implement the desired code provided by suitable media in at least one example. For example, the processing circuitry 2110 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable code. Examples of the processing circuit 2110 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, Or any combination of these designed to perform the functions described herein. A general purpose processor may include any conventional processor, controller, microcontroller, or state machine as well as a microprocessor. The processing circuit 2110 may also include a combination of computing components, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, May be implemented as various configurations of other numbers. These examples of the processing circuit 2110 are for illustrative purposes and other suitable configurations within the scope of the present disclosure are also contemplated.

[00182] According to one or more aspects of the invention, the processing circuitry 2110 may include features, processes, functions, operations, and functions for any or all of the devices described herein, 0.0 > and / or < / RTI > routines. As used herein, the term "adapted " in relation to processing circuit 2110 means that processing circuit 2110 performs certain processes, functions, operations and / or routines in accordance with various aspects described herein And / or < / RTI > programmed to perform the functions described herein.

[00183] According to at least one example of an apparatus 2100, the processing circuit 2110 may include one or more of the features, processes, functions, operations and / or routines described herein Module 2120, a symbol transmission circuit / module 2122, a clock transmission / reception module 2120, a clock transmission circuit / module 2120, and a clock transmission circuit / module 2120. The clock transmission circuit / module 2120 is adapted to perform any or all of the described functions, functions, operations and / Module 2128, and encoding circuit / module 2140. In one embodiment, the circuit / module 2124 may include one or more of: a symbol receiving circuit / module 2126; a clock receiving circuit / module 2128;

[00184] Encoding circuitry / module 2140 may include circuitry and / or instructions (e.g., stored on storage medium 2104) adapted to perform several functions related to encoding data bits into a sequence of symbols Encoding instructions 2142). The encoding circuit / module 2140 may be configured to perform encoding by converting data bits into a set of transition numbers, and by converting a set of transition numbers to obtain a sequence of symbols.

The clock insertion circuit / module 2120 includes circuitry and / or instructions (e.g., storage medium 2104) adapted to perform several functions related to inserting a second clock signal into a sequence of symbols, Clock insertion instructions 2130), where the second clock signal is inserted into guaranteed transitions between successive pairs of symbols in a sequence of symbols.

[00186] Symbol transmission circuit / module 2122 may include circuitry and / or instructions (e.g., storage medium 2104 (e.g., a digital signal processor) and / or code that is adapted to perform several functions related to transmitting a sequence of symbols over a multi- (E.g., transmit symbol instructions 2132 stored on the network).

[00187] The clock transmission circuit / module 2124 may include circuitry and / or instructions (e.g., a clock signal) that are adapted to perform several functions related to transmitting a clock signal associated with a sequence of symbols over a dedicated clock line, Clock transmission instructions 2134 stored on media 2104), where the dedicated clock line is separate from and parallel to the multi-wire link.

[00188] The symbol transmission circuit / module 2126 may be, for example, coupled to receive a second sequence of symbols over at least one bi-directional line of a multi-wire link based on a clock signal transmitted via a dedicated clock signal And / or instructions (e.g., symbol receive instructions 2136 stored on storage medium 2104) adapted to perform the functions described herein.

The clock receiving circuit / module 2128 may include circuitry and / or instructions (e.g., storage medium 2104 (e.g., a clock, etc.)) adapted to perform several functions related to receiving a third clock signal via a dedicated clock line, (E.g., clock receive instructions 2138 stored on a memory). The third clock signal may be associated with a transmission clock that is used to encode data bits in a sequence of symbols received by symbol receiving circuit / module 2126 via at least one bi-directional line of the multi-wire link.

As noted above, the instructions stored by the storage medium 2104, when executed by the processing circuit 2110, cause the processing circuit 2110 to perform various functions and / or processes described herein To perform one or more of the operations. For example, storage medium 2104 may include clock insertion instructions 2130, symbol transmission instructions 2132, clock transmission instructions 2134, symbol reception instructions 2136, clock reception instructions 2138, and May include one or more of the encoding instructions (2142).

[00191] FIG. 22 is a flow chart 2200 illustrating a method of communicating data bits over a multi-wire link. The method may be performed by a transmitting device (e.g., device 100 of FIG. 1, transmitter 1602 of FIG. 16, or device 2100 of FIG. 21).

[00192] The transmitting device encodes data bits (eg, bits X 1604) into a sequence of symbols (2202). Additionally or alternatively, the transmitting device inserts a second clock signal (e.g., DDRCLK X 1624) into the sequence of symbols, where the second clock signal is a guarantee between pairs of consecutive symbols in the sequence of symbols Gt; 2204 < / RTI > Each symbol in the sequence of symbols may correspond to the signaling state of the N wires of a multi-wire link (e.g., multi-wire link 1612), where N is an integer greater than one. The transmitting device additionally transmits a sequence of symbols over the multi-wire link (2206). The transmitting device also transmits a clock signal (e.g., DDRCLK Y 1626) associated with the sequence of symbols via a dedicated clock line (e.g., dedicated clock line 1622), where the dedicated clock line is a multi- And is in parallel with it (2208).

[00193] In an aspect, a transmitting device may use a transcoder (eg, transcoder 1606) to convert data bits into a set of transition numbers, and by converting a set of transition numbers into a sequence of symbols, And encodes the bits into a sequence of symbols.

[00194] In an aspect, at least one line of the multi-wire link is bidirectional. The transmitting device may receive from the receiving device a second sequence of symbols via at least one bidirectional line 2210. [ In a further aspect, both the receiving device and the transmitting device can utilize the multi-wire link for bidirectional transmissions by interleaving the lines of the multi-wire link.

[00195] In another aspect, the dedicated clock line is bidirectional and may be driven from any device transmitting over the multi-wire link. The transmitting device may receive the third clock signal via a dedicated clock line. The third clock signal may be associated with a transmit clock used to encode the data bits into a sequence of symbols received by the transmitting device over at least one bi-directional line (2212). In a further aspect, both the receiving device and the transmitting device may utilize a dedicated clock line by alternately transmitting a dedicated clock signal through a dedicated clock line.

[00196] It is understood that the particular order or hierarchy of steps within the disclosed processes is exemplary of exemplary approaches. It will be appreciated that, based on design preferences, a particular order or hierarchy of steps within the processes may be rearranged. The appended method claims present elements of the various steps in a sample order and are not intended to be limited to the particular order or hierarchy presented.

[00197] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to be limited to the aspects described herein, but rather to the maximum extent consistent with the claims, wherein references to singular elements, unless specifically so stated, Is intended to mean "one or more" rather than "only one ". Unless specifically stated otherwise, the term "some" refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure which will be known or later disclosed to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims . Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element will be construed as a plus function unless explicitly mentioned by the use of the phrase "means for doing ".

Claims (18)

As a receiving device,
Processing circuit,
The processing circuit comprising:
Receiving a sequence of symbols over a multi-wire link,
Receiving a clock signal through a dedicated clock line, said dedicated clock line being separate from said multi-wire link and parallel to said multi-wire link, and
To decode the sequence of symbols using the clock signal
Respectively,
A second clock signal is inserted into guaranteed transitions between successive pairs of symbols in the sequence of symbols,
Wherein the processing circuit is configured to decode the sequence of symbols using the clock signal received on the dedicated clock line, ignoring the second clock signal,
At least one line of the multi-wire link is bidirectional,
Wherein the processing circuitry is further configured to transmit a second sequence of symbols over the at least one bidirectional line based on the clock signal received over the dedicated clock line. The method according to claim 1,
Wherein the processing circuit configured to decode is further configured to use the clock signal to convert the sequence of symbols into a set of data bits. 3. The method of claim 2,
The processing circuit configured to convert the sequence of symbols into a set of data bits,
Using a transcoder to convert the sequence of symbols into a set of transition numbers; And
To convert the set of transition numbers into a set of data bits
≪ / RTI > The method according to claim 1,
Each symbol in the sequence of symbols corresponding to a signaling state of the N wires of the multi-wire link,
Where N is an integer greater than one. The method according to claim 1,
Wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link. A data communication method in a receiving device,
Receiving a sequence of symbols over a multi-wire link;
Receiving a clock signal via a dedicated clock line, the dedicated clock line being separate from the multi-wire link and parallel to the multi-wire link; And
And decoding the sequence of symbols using the clock signal,
A second clock signal is inserted into guaranteed transitions between successive pairs of symbols in the sequence of symbols,
Wherein the sequence of symbols is decoded using the clock signal received on the dedicated clock line, ignoring the second clock signal,
At least one line of the multi-wire link is bidirectional,
The method further comprising transmitting a second sequence of symbols over the at least one bi-directional line based on the clock signal received over the dedicated clock line. The method according to claim 6,
Wherein the decoding comprises converting the sequence of symbols to a set of data bits using the clock signal. 8. The method of claim 7,
Wherein converting the sequence of symbols into the set of data bits comprises:
Using a transcoder to convert the sequence of symbols into a set of transition numbers; And
And converting the set of transition numbers into the set of data bits. The method according to claim 6,
Each symbol in the sequence of symbols corresponding to a signaling state of the N wires of the multi-wire link,
Where N is an integer greater than one. The method according to claim 6,
Wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link. As a transmitting device,
Processing circuit,
The processing circuit comprising:
Encodes the data bits into a sequence of symbols,
Inserting a second clock signal into the sequence of symbols, the second clock signal being inserted into guaranteed transitions between successive pairs of symbols in the sequence of symbols;
Transmitting the sequence of symbols over a multi-wire link; And
To transmit a clock signal associated with the sequence of symbols over a dedicated clock line
Respectively,
Wherein the dedicated clock line is separate from the multi-wire link and parallel to the multi-wire link,
At least one line of the multi-wire link is bidirectional,
Wherein the processing circuitry is further configured to receive a second sequence of symbols over the at least one bi-directional line based on the clock signal transmitted over the dedicated clock line. 12. The method of claim 11,
Wherein the processing circuit configured to encode the data bits comprises:
Use a transcoder to convert the data bits into a set of transition numbers; And
To transform the set of transition numbers to obtain a sequence of the symbols
Further comprising a transmitting device. 12. The method of claim 11,
Each symbol in the sequence of symbols corresponding to a signaling state of the N wires of the multi-wire link,
Where N is an integer greater than one. 12. The method of claim 11,
Wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link. A data communication method in a transmitting device,
Encoding data bits into a sequence of symbols;
Inserting a second clock signal into the sequence of symbols, wherein the second clock signal is inserted into guaranteed transitions between successive pairs of symbols in the sequence of symbols;
Transmitting the sequence of symbols over a multi-wire link; And
Transmitting a clock signal associated with the sequence of symbols over a dedicated clock line,
Wherein the dedicated clock line is separate from the multi-wire link and parallel to the multi-wire link,
At least one line of the multi-wire link is bidirectional,
The method further comprising receiving a second sequence of symbols over the at least one bi-directional line based on the clock signal transmitted over the dedicated clock line. 16. The method of claim 15,
Wherein encoding the data bits comprises:
Using a transcoder to convert the data bits into a set of transition numbers; And
And transforming the set of transition numbers to obtain a sequence of the symbols. 16. The method of claim 15,
Each symbol in the sequence of symbols corresponding to a signaling state of the N wires of the multi-wire link,
Wherein N is an integer greater than one. 16. The method of claim 15,
Wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.

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