KR20170088138A - Memory device, memory module and memory system - Google Patents

Abstract

Disclosed are a memory device with reduced power consumption in a circuit, a memory module, and a memory system. According to an embodiment of the present disclosure, the memory device comprises: a memory cell array including a plurality of memory areas; a data pattern providing unit for providing a preset data pattern; and a write circuit for writing the data pattern provided by the data pattern providing unit in the memory area corresponding to an address when a first write command and the address are received from an external device.

Description

[0001] MEMORY DEVICE, MEMORY MODULE, AND MEMORY SYSTEM [0002]

The present disclosure relates to a semiconductor memory device, and more particularly, to a memory device, a memory module, and a memory system that write predetermined data to a memory cell array without using an input / output circuit when a specific write command is received.

BACKGROUND ART [0002] Semiconductor memory devices such as DRAMs are widely used as main memories of computers, smart watches, smart phones and tablet PCs. There is a demand for a memory in which power consumption is reduced and operation speed is increased in accordance with the weight and speed of hardware and the complexity of software. Accordingly, various techniques for providing a memory device that operates at a high speed with low power have been developed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device in which the power consumption of a circuit is reduced. It is also an object of the present invention to provide a memory device, a memory module, and a memory system that operate at low power and high speed.

According to an aspect of the present invention, there is provided a memory device including: a memory cell array including a plurality of memory areas; A data pattern providing unit for providing a predetermined data pattern; And a write circuit for writing a data pattern provided from the data pattern provisioner into a memory area corresponding to the address signal when the first write command and the address signal are received from the external device.

According to an aspect of the present invention, there is provided a memory system for comparing input data input from the outside with a preset data pattern, and when the input data matches the data pattern, A memory controller for transmitting the data; And a memory device that internally generates the data pattern in response to the pattern write command and writes the data pattern in a memory area corresponding to the address information.

According to the memory device, the memory module and the memory system according to the technical idea of the present disclosure, if the data to be written in the memory device matches the preset data pattern, By writing to the array, the power consumption of the memory device, the memory module, and the memory system can be reduced. In addition, since the occupancy time of the data bus used by the memory device is reduced, the efficiency of the data bus can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the detailed description of the present disclosure.
1 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure
2 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure;
3 is a block diagram illustrating one implementation of a memory device in accordance with an embodiment of the present disclosure.
4 is a diagram showing an example of a data pattern providing unit of FIG.
5A and 5B are diagrams showing a method of setting a write command.
6 is a table showing an example of setting of a write command according to the embodiment of the present disclosure.
7 shows a timing diagram of an input signal of a memory device during a write operation according to an embodiment of the present disclosure;
8 is a timing diagram showing an example of address setting in a write operation according to the embodiment of the present disclosure.
9 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure;
10 is a block diagram illustrating one implementation of a memory controller in accordance with an embodiment of the present disclosure.
11 is a flow chart illustrating a method of operating a memory controller in accordance with an embodiment of the present disclosure.
12 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied.
13 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure;
14 is a flow chart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied.
15A and 15B are diagrams showing an embodiment in which, in an electronic device according to an embodiment of the present disclosure, pattern buffers provided in a memory controller and a memory device, respectively, are updated.
16 is a table showing an example of setting of a write command according to the embodiment of the present disclosure.
17 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure;
18 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied.
19 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure;
20 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure;
21 is a block diagram illustrating one implementation of a memory controller in accordance with an embodiment of the present disclosure;
22 is a table showing an example of setting of a write command according to the embodiment of the present disclosure.
23 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure.
24 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure;
25 is a block diagram schematically illustrating a memory controller according to an embodiment of the present disclosure;
26 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied.
27 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure.
28 shows a timing diagram of an input signal applied to the rank of the memory system.
29A and 29B are block diagrams illustrating memory controllers and memory modules according to embodiments of the present disclosure.
30 is a block diagram showing a memory device having a stacked structure including a plurality of semiconductor layers.
31 is a block diagram illustrating a computer system in accordance with an embodiment of the present disclosure;
32 is a block diagram illustrating a computer system including a memory system in accordance with an embodiment of the present disclosure;

Various embodiments of the present disclosure are described below in connection with the accompanying drawings. The various embodiments of the present disclosure are capable of various modifications and have various embodiments, and specific embodiments are illustrated in the drawings and detailed description is set forth in the accompanying drawings. It should be understood, however, that it is not intended to limit the various embodiments of the disclosure to specific embodiments, but includes all changes and / or equivalents and alternatives falling within the spirit and scope of the various embodiments of the disclosure. In connection with the description of the drawings, like reference numerals have been used for like elements.

Or " may " may be used in various embodiments of the disclosure to refer to the presence of such a function, operation, or component as disclosed herein, Components and the like. Furthermore, in various embodiments of the present disclosure, terms such as "comprises" or "having" are intended to specify that there exist features, numbers, steps, operations, elements, But do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In various embodiments of the present disclosure, the expressions " or " and the like include any and all combinations of words listed together. For example, " A or B " may comprise A, comprise B, or both A and B.

&Quot; first, " " second, " " first, " or " second, " etc. used in various embodiments of the present disclosure may denote various elements of various embodiments, I never do that. For example, the representations do not limit the order and / or importance of the components. The representations may be used to distinguish one component from another. For example, both the first user equipment and the second user equipment are user equipment and represent different user equipment. For example, without departing from the scope of the various embodiments of the present disclosure, a first component can be named a second component, and similarly, a second component can also be named a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it is to be understood that the element may be directly connected or connected to the other element, It should be understood that there may be other new components between the different components. On the other hand, when it is mentioned that an element is "directly connected" or "directly connected" to another element, it is understood that there is no other element between the element and the other element It should be possible.

The terminology used in the various embodiments of this disclosure is used only to describe one specific embodiment and is not intended to limit the various embodiments of the disclosure. The singular expressions include plural expressions unless the context clearly dictates otherwise.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present disclosure belong.

Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art, and unless otherwise clearly defined in the various embodiments of this disclosure, ideally or excessively formal It is not interpreted as meaning.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure;

Referring to FIG. 1, a memory system 1000 may include a memory controller 200 and a memory device 100. The memory controller 200 may include a data comparator 210 and the memory device 100 may include a memory cell array 110, a read / write circuit 150, and a data pattern provider 180.

The memory controller 200 provides the memory device 100 with various signals for controlling the memory device 100, such as a command CMD and an address signal ADDR. The memory controller 200 can exchange data with the memory device 100.

The memory device 100 stores data (DATA) in the memory cell array 110 or data stored in the memory cell array 110 to the memory controller 200 based on signals received from the memory controller 200. [ As shown in FIG.

When writing data to the memory device 100, the memory controller 200 can transmit a write command, an address signal ADDR indicating a memory area to be written, and data to be written (DATA) to the memory device 100 . Meanwhile, the memory controller 200 according to the embodiment of the present disclosure does not provide the data (DATA) to the memory device 100 when the data (DATA) to be written in the memory device 100 matches a preset data pattern It is possible to provide the memory device 100 with a command (for example, a pattern write command) and an address signal ADDR that instruct writing of a predetermined data pattern.

The predetermined data pattern may be data recognized by the memory controller 200 and the memory device 100 in the same manner and may be data previously agreed upon by the memory controller 200 and the memory device 100. For example, the data pattern may be data whose consecutive bits are '0' or '1'. Or the data pattern may be data previously provided as write data to the memory device 100. [ As another example, the data pattern may be data set by a user (hereinafter referred to as user setting data). The user setting data refers to a data pattern set by the host during operation of the memory device 100 or the memory system 1000. In addition, the data pattern may be data that is frequently written to the memory device 100. In addition, the data pattern may be data that is set during operation of the memory device 100 and the memory system 1000.

The memory controller 200 can provide the memory device 100 with a command for instructing writing of a predetermined data pattern (e.g., a pattern writing command) and an address signal ADDR. At this time, the memory device 100 may internally generate the data pattern, or select one of the previously stored data patterns, and write the data pattern to the memory cell array 110.

The memory controller 200 may include a data comparison unit 210. When the data comparison unit 210 receives a write request from an external device such as a host, the data comparison unit 210 may compare the data requested to be written with a predetermined data pattern and determine whether the data is matched. When the data requested to be written matches the data pattern, the memory controller 200 may transmit the pattern write command and the address ADDR to the memory device 100. The memory controller 200 may transmit the normal write command, the address signal ADDR and the data DATA to the memory device 100 if the data requested to be written does not match the data pattern. Data (DATA) may be transmitted through a data bus (not shown) that transfers data between the memory controller 200 and the memory device 100.

The memory device 100 can be applied to a random access memory requiring a high processing speed. As a random access memory, the memory device 100 may include a dynamic random access memory (DRAM) cell. The memory device 100 may be a DRAM chip including a DRAM cell. Alternatively, the memory device 100 may include other random access memory cells such as a magnetic RAM (MRAM) cell, a spin transfer torque magnetic RAM (STT) cell, a phase change RAM (PRAM) cell, and a resistive RAM .

The memory cell array 110 may include a plurality of memory regions, each of which is composed of a plurality of memory cells. As described above, the memory cell may be a DRAM cell, and may also include various kinds of memory cells capable of random access. Also, the memory cells may be single level cells each storing single bit data or multi level cells storing at least two bits of data.

The data pattern providing unit 180 may generate a predetermined data pattern and provide the data pattern to the read / write circuit 150. [ In one embodiment, the data pattern provisioner 180 may generate a data pattern in response to a pattern write command received from the memory controller 200.

The read / write circuit 150 can write data (DATA) to the memory cell array 110 or read the data (DATA) from the memory cell array 110. The read / write circuit 150 can write data (DATA) into a memory area corresponding to an address ADDR received from the memory controller 200 or read data (DATA) from the memory area. According to the present embodiment, when the pattern write command and the address ADDR are received from the memory controller 200, the read / write circuit 150 supplies the address signal ADDR to the data pattern provided from the data pattern provider 180, In the memory area corresponding to the memory area.

In the memory system 1000 according to the present embodiment, when the data (DATA) requested to be written in the memory device 100 matches with a predetermined data pattern, the memory controller 200 can transfer the data (DATA) And supplies the write command and the address signal ADDR to the memory device 100. The memory device 100 does not receive the data DATA from the memory controller 200 but generates data internally generated based on the pattern write command A data pattern to be selected in response to the pattern write command among the data patterns stored in the pattern memory or the data pattern stored in the memory cell array 110 can be written. Accordingly, since data transmission / reception does not occur between the memory controller 200 and the memory device 100, the power consumption of the memory system 1000 can be reduced. In addition, in the write operation of the memory system 1000, since the data transfer time between the memory controller 200 and the memory device 100 is reduced, the operation speed of the memory system 1000 can be increased.

2 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure;

2, the memory device 100 includes a memory cell array 110, a control logic 120, an address register 130, a row decoder 140, a column decoder 160, a read / write circuit 150, An input / output buffer 170, and a data pattern providing unit 180. In addition, the memory device 100 may further include various kinds of circuits used for data write and read operations.

The memory cell array 110 may include memory cells arranged in a region where a plurality of bit lines BL and a plurality of word lines WL are crossed. A plurality of memory cells may constitute a memory region, where each memory region may include memory cells of a write unit.

The control logic 120 includes a command decoder 121 and a mode register 122 and is capable of controlling the overall operation of the memory device 100. [ The command decoder 121 receives commands (CMD) related signals externally applied, such as a chip select signal (CS), a row address strobe signal (RAS), a column address strobe signal Address strobe (CAS), write enable (WE) and clock enable (CKE) signals to generate decoded command signals internally. In one embodiment, the control logic 120 may also decode the address signal ADDR to generate a control signal associated with the write command. The mode register 122 may set an internal register in response to a mode register signal and an address signal ADDR for designating an operation mode of the memory device 100. [

The address register 130 may temporarily store an externally input address signal ADDR. The address register 130 then transfers the row address X-ADD to the row decoder 140 and the column address Y-ADD to the column decoder 160.

The row decoder 140 and the column decoder 160 may each include a plurality of switches. The row decoder 140 selects the word line WL in response to the row address X-ADDR and the column decoder 160 can select the bit line BL in response to the column address Y-ADDR .

The input / output buffer 170 provides data (DATA) read from the memory cell array 110 to the outside of the memory device 100, for example, a memory controller (200 in FIG. 1) To the read / write circuit 150. The data DATA may be transmitted to the outside via the data pad DQ [m-1: 0] (or referred to as a data pin) or may be received from the outside.

The data pattern providing unit 180 may provide the read / write circuit 150 with a predetermined data pattern. The data pattern providing unit 180 may generate a data pattern in response to a pattern write command received from the outside, for example, the memory controller 200. [ In one embodiment, the data pattern providing unit 180 may select one of a plurality of preset data patterns in response to the pattern write command. For example, the data pattern provider 180 may select a data pattern corresponding to the pattern write command from a pattern buffer (not shown) storing a plurality of data patterns, and output the selected data pattern.

The read / write circuit 150 includes a write circuit 151 and a read circuit 152 and is capable of writing data to the memory cell array 110 or reading data from the memory cell array 110. For example, the write circuit 151 may include a plurality of write drivers, and the read circuit 152 may include a plurality of sense amplifiers.

The write circuit 151 selectively supplies one of the data DATA provided from the input / output buffer 170, that is, the data received from the outside and the data pattern provided from the data pattern provider 180, to the memory cell array 110, . When a normal write command is received from the outside, the write circuit 151 writes data (DATA) provided from the input / output buffer 170 to the memory cell array 110. When a pattern write command is received from the outside, The circuit 151 may write the data pattern provided from the data pattern providing unit 180 to the memory cell array 110. [

As described above, when the pattern write command and the address ADDR are received from the memory controller 200, the memory device 100 according to the embodiment of the present disclosure sets a predetermined data pattern in the memory area corresponding to the address signal ADDR . Accordingly, at the time of writing the predetermined data pattern, since no data is received from the outside, the power consumption of the memory device 100 can be reduced. The data (DATA) is transferred from the memory controller 200 through the data bus. When the predetermined data pattern is written, no data is transmitted / received between the memory controller 200 and the memory device 100, Since the bus is not used, the data bus occupation time can be reduced. At this time, since the data bus can be used for the operation of another memory device or other operations of the memory device 100 (for example, a read operation and a consecutively performed write operation), the data bus utilization .

3 is a block diagram illustrating one implementation of a memory device in accordance with an embodiment of the present disclosure. 3 shows the main configuration of the memory device in relation to the write operation, and the configurations of the memory device shown in Fig. 2 may be provided in the memory device of Fig. The write operation of the memory device will be described in detail with reference to FIG.

3, the memory device 100a includes a memory cell array 110, a command decoder 121, a write circuit 151, an input buffer 171, a data pattern providing unit 180, and a selector 190 .

The command decoder 121 decodes the command CMD related to the write operation received from the outside, for example, from the memory controller (200 in FIG. 1) to control the data pattern providing unit 180 and the operation of the selector 190 Signals. In the write operation, the command decoder 121 can receive one of the normal write command NW and the pattern write command PW. The command decoder 121 can control the operations of the data pattern provider 180 and the selector 190 on the basis of the normal write command NW and the pattern write command PW.

The data pattern providing unit 180 can output a predetermined data pattern in response to the pattern writing command PW. In one embodiment, the data pattern providing unit 180 may selectively generate one of a plurality of predetermined data patterns corresponding to the pattern writing command PW. For example, when the preset data pattern is data having the same bit value, for example, '0' or '1', the data pattern providing unit 180 repeatedly repeats the same bit value in accordance with the pattern write command PW Lt; / RTI > In the embodiments, the data pattern providing unit 180 includes a pattern buffer 181 that stores a plurality of predetermined data patterns, and in response to the pattern write command PW, One of the data patterns of FIG.

The input buffer 171 is a constitution of the input / output buffer 170 of FIG. 2 and can receive data (DATA) from the outside via the data pad DQ. The input buffer 171 may temporarily store the data (DATA) and provide the data (DATA) to the write circuit 151.

The selector 190 selects one of the data pattern DP output from the data pattern providing unit 180 and the input data IDATA output from the input buffer 171 based on the selection signal SEL, 151). The selector 190 selectively outputs the data pattern DP or the input input data IDATA in response to the pattern writing command PW and the selection signal SEL whose level is set in accordance with the normal write command NW . For example, when the normal write command NW is received, the select signal SEL is at the first level, e.g., logic high, and when the pattern write command PW is received, the select signal SEL is at the second level, For example, logic high. The selector 190 outputs the input data IDATA in response to the selection signal SEL of the first level and can output the data pattern DP in response to the selection signal SEL of the second level .

The write circuit 151 can write the data output from the selector 190 to the memory area of the memory cell array 110 corresponding to the address signal ADDR.

When the normal writing is performed, the memory device 100a can receive the normal write command NW, the address signal ADDR and the data DATA from the outside, for example, the memory controller (200 in FIG. 1). At this time, the data pattern providing unit 180 does not output the data pattern. The selector 190 provides externally received data DATA from the input buffer 171 to the write circuit 151 and the write circuit 151 outputs the data DATA from the outside to the memory area corresponding to the address signal ADDR. The received data (DATA) can be written.

When the pattern writing is performed, the memory device 100a can receive the pattern writing command PW and the address signal ADDR from the outside. The data pattern providing unit 180 may output the data pattern in response to the pattern writing command PW. At this time, data (DATA) is not received from the outside. The selector 190 may provide the write circuit 151 with the data pattern DP output from the pattern write data providing unit 180. [ The write circuit 151 can write the data pattern DP in the memory area corresponding to the address signal ADDR.

FIG. 4 is a diagram showing an example of the data pattern providing unit 180 of FIG.

Referring to FIG. 4, the data pattern providing unit 180 may include a pattern buffer 181. The pattern buffer 181 may store one or more preset data patterns. In embodiments, the data pattern may include data 181a with consecutive bits set to '0' or '1'. For example, the data pattern may be data in which all bits are set to '0' or set to '1'.

In embodiments, the data pattern may include data 181b previously written to a memory cell array (110 of FIG. 3). The previously written data 181b refers to the data received with the normal write command NW from the memory controller (200 in FIG. 1) and written to the memory cell array (110 in FIG. 1). In an embodiment, the data pattern may include a plurality of previously written data PWD1, PWD2, ... PWDk.

In embodiments, the data pattern may be buffer data 181c from the memory controller (200 of FIG. 1) that has been requested to write to the pattern buffer 181. In the embodiment, the data pattern may include a plurality of buffer data UDD1, UDD2, ..., UDDz that the memory controller 200 has requested to store in the pattern buffer 181. [ For example, the buffer data may include a data pattern set by the user or a data pattern that is frequently written to the memory device 100.

In embodiments, the pattern buffer 181 may store at least one data pattern of the various types of data patterns described above. However, this is an exemplary one, and the pattern buffer 181 may store other types of data patterns in addition to the above-described data pattern.

The data pattern providing unit 180 may select one of the data patterns stored in the pattern buffer 181 in response to the internal pattern write control signal IPW generated by decoding the pattern write command PW. In another embodiment, the data pattern providing 180 may extend the selected data pattern to create a new data pattern. For example, when the capacity of the memory area requested to be written is 64 bytes and the selected data pattern is 32 bytes, the data pattern providing unit 180 selects a data pattern in which the selected data pattern is repeated twice And output the generated data pattern.

5A and 5B are diagrams showing a method for setting a write command.

5A and 5B, the type of the write command can be set by a combination of a general write command WCMD indicating a write command and a write mode command MCMD indicating a write mode. In the normal write command NW and the pattern write command PW, the setting of the general write command WCMD is the same and the write mode command MCMD may be different. Therefore, the normal write command NW and the pattern write command PW can be distinguished according to the setting value of the write mode command MCMD.

The general write command WCMD includes a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS received via the command pins (or command pad) of the memory device 100, Can be set by a write enable signal / WE. For example, the general write command WCMD is a write command for the column address strobe signal / CAS and the row enable strobe signal / RAS, / WE) is a low level. The general write command WCMD may be received in synchronization with the rising edge (R edge) of the clock signal CLK. However, it is not so limited, and the write command WCMD (or other signals) may be received in synchronization with at least one of the rising edge and the falling edge of the clock signal CLK. However, for convenience of explanation, it is assumed that signals are received in synchronization with the rising edge of the clock signal CLK.

On the other hand, the write mode command MCMD may be set by a signal received via address pins (CA Pins) of the memory device 100. 5A, the memory device 100 includes twelve address pins CA [11: 0], and address signals A0-A8 through address pins CA [8: 0] ), E.g., a column address signal, is received and the write mode command MCMD may be received via the remaining three address pins CA [11: 9]. A normal write command or a pattern write command can be set according to the setting values of the mode signals M0, M1, and M2 received via the address pins CA [11: 9].

5B, the memory device 100 includes six address pins CA [5: 0] and is synchronized with the two rising edges of the clock signal CLK through six address pins, And a write mode command MCMD may be received. The first to sixth address signals A0 to A5 are received through the six address pins CA [5: 0] in synchronization with the first rising edge REdge1 of the clock signal CLK, and the clock signal The sixth to ninth address signals A6 to A8 are received via the three address pins CA [2: 0] in synchronization with the second rising edge REdge2 of the address pins CLK and CLK, Mode signals M0, M1, and M2 may be received via the CA [5: 3].

6 is a table showing an example of setting of a write command according to the embodiment of the present disclosure.

As described above with reference to Figs. 5A and 5B, the write command can be set by a combination of a general write command and a write mode command MCMD. The write mode command MCMD may be sent via the address pins (or address pads) of the memory device that are not used to transfer the address signal, e.g., some address pins CAx, CAy, CAz.

6, when a mode signal of '0 0 0' is received via the address pins CAx, CAy and CAz, the normal write command NW is set. Otherwise, the pattern write command is set . In response to the normal write command NW, the memory device (100 in FIG. 1) can write data received from the memory controller 200 to the memory cell array 110. FIG. At this time, since the memory device 100 receives the data, the data pad DQ may be used. The data pad DQ includes a plurality of pads.

In one embodiment, in response to the normal write command NW, the memory device 100 of FIG. 1 not only receives the data received from the memory controller 200, but also the pattern buffer 181 as well as the memory cell array 110 Can be stored.

In response to the pattern write command PW, the memory device (100 in FIG. 1) can internally write a predetermined data pattern into the memory cell array 110. FIG. At this time, since the memory device 100 does not receive data, the data pad DQ is not used.

On the other hand, one of a plurality of pattern writing commands PW1, PW2, PW3, and PW4 may be set according to a setting value of a signal received through the address pins CAx, CAy, CAz. For example, when the signal received through the address pins CAx, CAy, CAz is '0 0 1' or '0 1 0', the first pattern write command PW1 or the second pattern write command PW2, And in response to the first pattern write command PW1 or the second pattern write command PW2, the memory device 100 writes the data pattern in which all the bits are set to '0' or '1' 110). As another example, when the signal received through the address pins CAx, CAy, CAz is '0 1 1', the third pattern write command PW3 is set, and when the signal is set to '1 0 0' , The fourth pattern write command PW4 can be set. In response to the third pattern write command PW3, the memory device 100 can write the previously written data to the memory cell array 110 as a data pattern. In addition, the memory device 100 can write the buffer data to the memory cell array 110 in response to the fourth pattern write command PW4. As described above with reference to FIG. 4, the buffer data is stored in the pattern buffer 181 as a data pattern requested to be written in the pattern buffer 181 from the memory controller (200 in FIG. 1) user defined data pattern) or a data pattern that is frequently written to the memory device 100.

On the other hand, the memory controller 200 stores a pattern storing command PS and data for instructing writing of buffer data to the pattern buffer 181, for storing the buffer data in the pattern buffer 181 of the memory device 100, In other words, the buffer device 100 transmits the buffer data to the memory device 100, and when the pattern store command PS is received, the buffer device 181 can store the buffer data received via the data pad DQ in the pattern buffer 181 have. The pattern store command PS may be provided as one of the write commands. As shown in the figure, when a mode signal of '1 0 1' is received through the address pins CAx, CAy, and CAz, a pattern save command PS may be set.

As described above, the write command has been exemplarily described with reference to FIG. However, the present invention is not limited thereto, and the signals indicating the normal write command and the pattern write command can be set variously.

7 shows a timing diagram of an input signal of a memory device during a write operation according to an embodiment of the present disclosure;

Referring to FIG. 7, in a write operation, a command indicating write (e.g., a general write command WCMD in FIGS. 5A and 5B), an address signal ADDR, and a write command PW , NW) may be received. The write commands PW and NW may be received through a part of the address pins CA [n-1: 0]. When the pattern write command PW is received, no data is received. When the normal write command NW is received, data Din can be received from the outside, for example, from the memory controller 200 (FIG. 1). The data Din can be received after a predetermined time after the normal write command NW is received. As shown in the figure, the first period T1 according to the pattern write command PW does not require the time at which the data Din is received. Therefore, the write command can be performed in a relatively short time. In addition, since no data is received, power consumption of the memory device due to data reception can be reduced.

On the other hand, FIG. 7 shows a case where an address signal ADDR indicating one memory area is transferred during a write operation. However, the present invention is not limited thereto, and an address signal ADDR indicating a plurality of memory areas may be transferred during a write operation. This will be described with reference to FIG.

8 is a timing diagram showing an example of address setting in a write operation according to the embodiment of the present disclosure.

Referring to FIG. 8, in a write operation, memory device 100 may receive a start address signal (Start ADDR) and an end address signal (End ADDR). The start address signal (Start ADDR) indicates a start point at which data is stored in the memory cell array (110 in FIG. 1), and the end address signal (End ADDR) indicates a point at which data storage is completed. The address signals may be transmitted in synchronization with the twice rising edges of the clock signal CLK. For example, in synchronization with the first and second rising edges of the clock signal CLK, a start address signal Start ADDR may be received. In one embodiment, as described with reference to FIG. 5B, the pattern write command PW may be received along with the address signal. The pattern write command PW may be received with the start address signal Start ADDR in synchronization with the second rising edge of the clock signal CLK. Thereafter, the end address signal End ADDR may be received in synchronization with the next rising edge of the clock signal CLK, e.g., the third rising edge and the fourth rising edge. The memory device 100 can write the data pattern in the plurality of memory areas corresponding to the start address (Start ADDR) to the end address (End ADDR).

On the other hand, as another embodiment, after the start address signal (Start ADDR) and the pattern write command PW are received, the length information can be received in synchronization with the third rising edge. The length information may include information corresponding to the length of the memory area in which the data pattern is to be written. The memory device 100 can write a data pattern generated from the memory area corresponding to the start address signal Start ADDR to the memory area set according to the length information.

9 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure;

Referring to FIG. 9, the memory device 100 sets a data pattern (S110). The data pattern may be predefined data between the memory controller 200 and the memory device 100. For example, the data pattern may be data whose consecutive bits are '0' or '1'. Or the data pattern may be data previously provided as write data to the memory device 100. [ As another example, the data pattern may be data set by the user or data in which writing to the memory device 100 is performed frequently. In addition, the data pattern may be data that is set during operation of the memory device 100 and the memory system 1000. The memory device 100 may store a data pattern in a buffer (e.g., a pattern buffer 181 in FIG. 3) provided therein.

When the pattern write command and the address signal are received from the memory controller 200 in step S120, the memory device 100 may generate the data pattern, that is, a predetermined data pattern in response to the pattern write command (S130) . The memory device 100 may select and output a data pattern corresponding to the pattern write command from the pattern buffer 181 or may expand the selected data pattern to generate a new data pattern.

The memory device 100 writes the data pattern in a memory area corresponding to the received address signal (S140).

As described above, when the pattern write command is received from the memory controller, the memory device 100 internally generates a predetermined data pattern, writes the data pattern to the memory cell array, It is possible to perform the write operation without receiving it.

10 is a block diagram illustrating one implementation of a memory controller in accordance with an embodiment of the present disclosure.

Referring to FIG. 10, the memory controller 200 may include a data comparator 210 and a pattern buffer 220. In one embodiment, the pattern buffer 220 may be implemented as the same functional block as the data comparison unit 210. In another embodiment, a part of the buffer included in the memory controller 200 may be used as the pattern buffer 220. [

The pattern buffer 220 may store a preset data pattern. In one embodiment, a plurality of data patterns (Pattern 1 to Pattern m) may be stored in the pattern buffer 220. The plurality of data patterns (Pattern 1 to Pattern m) are stored in a plurality of data patterns (181a, 181b, 181c in Fig. 4) stored in the pattern buffer 181 of the data pattern preparation unit 180 of the memory device ). ≪ / RTI > In the embodiments, the plurality of data patterns (Pattern 1 to Pattern m) may include data in which all bits are set to '0' or '1'. In embodiments, the plurality of data patterns (Pattern 1 to Pattern m) may include write data previously sent to the memory device 100. In the embodiments, the plurality of data patterns (Pattern 1 to Pattern m) are user setting data, and may include data provided from a host.

The data comparison unit 210 may compare the data DATA with the data pattern stored in the pattern buffer 220 when receiving the address information ADD and the data DATA together with the write request from the host . In one embodiment, the data comparison unit 210 may compare the data DATA with a plurality of data patterns (Pattern 1 to Pattern m). When the data DATA matches a data pattern, for example, one of a plurality of data patterns (Pattern 1 to Pattern m), the memory controller 200 can generate a pattern write command PW corresponding to the matched data pattern . 6, a detailed description thereof will be omitted.

The memory controller 200 can send the command PW and the address signal ADDR to the memory device 100. [ At this time, the address signal ADDR indicates a memory area of the memory device corresponding to the address information ADD received from the host (Host).

On the other hand, if the data DATA does not match the data pattern, the memory controller 200 can generate the normal write command NW. The memory controller 200 can transfer the normal write command NW, the address signal ADDR and the data DATA to the memory device 100. [

11 is a flow chart illustrating a method of operating a memory controller in accordance with an embodiment of the present disclosure.

Referring to FIG. 11, the memory controller 200 sets a data pattern (S210). The data pattern may be predefined data between the memory device 100 and the memory controller 200. For example, the data pattern may be data whose consecutive bits are '0' or '1'. Or the data pattern may be data that was previously sent to the memory device 100 as write data. As another example, the data pattern may be data set by a user and data received from a host. As another example, the data pattern is data in which writing is frequently performed in the memory device 100. The memory controller 200 analyzes data requested to be written in the memory device 100, The data requested to be written can be determined as frequently used data, and the data can be set as a data pattern. In addition, the data pattern may be various kinds of data set in the operation of the memory controller 200 and the memory system 1000. The memory controller 200 may store information on the data pattern or may store the data pattern in the pattern buffer 220 provided therein. The memory controller 200 provides the information or the data pattern of the data pattern to the memory device 100 and the memory device 100 stores the data pattern of the data pattern received from the memory controller 200 By storing the information or data pattern in a pattern buffer (181 in FIG. 3) provided therein, the data pattern can be set.

When data and address information are received together with a write request from the host (S220), the memory controller 200 compares the received data with a preset data pattern (S230). When the received data matches the data pattern, the memory controller 200 sends a pattern write command and an address signal to the memory device 100 (S240). If the received data does not match the data pattern, the memory controller 200 sends the normal write command, the data and the address signal to the memory device 100 (S250).

12 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied. The electronic device includes a host 300, a memory controller 200, and a memory device 100, and Fig. 12 shows a write operation among the normal operations of the electronic device.

Referring to FIG. 12, the memory device 100 and the memory controller 200 set data patterns (S311, S312). 9 to 11, the data pattern is mutually contracted data between the memory device 100 and the memory controller 200, and is commonly set in the memory controller 200 and the memory device 100. [ .

When a write request is received from the host 300 (S320), the memory controller 200 compares the received data with a preset data pattern and determines whether the data is matched (S330). If the data is not matched, the memory controller 200 transmits the normal write command NW, the address signal ADDR, and the data DATA to the memory device 100 (S341). The memory device 100 writes the data DATA in a memory area corresponding to the address signal ADDR (S342).

On the other hand, if the received data matches the preset data pattern, the memory controller 200 can transmit the pattern write command PW and the address signal ADDR to the memory device 100 (S351). The memory device 100 may generate a data pattern in response to the pattern write command PW (S352). At this time, the data pattern may be generated based on one of preset data patterns in step S312. In one embodiment, the generated data pattern may be one of a plurality of predetermined data patterns in step S312. The memory device 100 can write the data pattern in the memory area corresponding to the address signal ADDR (S353).

13 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure; The writing method of Fig. 13 shows a writing method of the memory device in the case where data previously written in the memory device 100 is set as a data pattern, as one embodiment of the writing method of Fig.

Referring to FIG. 13, the memory device 100 receives a write command, a first address (or address signal), and data from the memory controller 200 (S410). At this time, the write command may be a normal write command. The memory device 100 stores the data in an internal buffer, for example, a pattern buffer 181 in FIG. 3 (S420), and writes the data in a memory area corresponding to the first address (S430). In one embodiment, steps S410 and S420 are performed a plurality of times, and a plurality of data may be stored in the internal buffer. In one embodiment, since the capacity of the internal buffer is limited, data received in the memory device 100 relatively late, that is, data received near the current time, may be updated in the internal buffer.

Thereafter, when the pattern write command and the second address are received (S440), the memory device 100 may generate a data pattern based on the data stored in the internal buffer (S450). In response to the pattern write command, the memory device 100 can select one of a plurality of data stored in the internal buffer and output the selected data as a data pattern.

The memory device 100 may write the data pattern in a memory area corresponding to the second address (S460). The second address may represent the same memory area as the first address. As another example, the second address may represent a memory area different from the first address. For example, the second address may indicate a memory area adjacent to the first address.

14 is a flow chart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied. The electronic device may include a memory device in which a write operation is performed in accordance with the write method of FIG. The electronic device includes a host 300, a memory controller 200 and a memory device 100, and Fig. 14 shows a write operation among the normal operations of the electronic device. In this embodiment, the memory controller 200 and the memory device 100 may each include a pattern buffer for storing data patterns therein, and may store the pattern buffer of the memory controller 200 as a first buffer, 100) will be referred to as a second buffer.

Referring to FIG. 14, first, the host 300 may request a data write to the memory controller 200 (S510). The host 300 may transmit the write request signal, the data to be written, and the address signal to the memory controller 200. When a write request is received from the host 300 (S510), the memory controller 200 may store the received data together with the data write request in the first buffer (S520). The memory controller 200 may transmit the normal write command NW, the address signal ADDR and the data DATA to the memory device 100 (S530).

The memory device 100 stores the data received from the memory controller 200 in the second buffer S540 and writes the data in the memory area corresponding to the address signal ADDR at step S550.

According to the above steps S510 to S550, the data written in the memory device 100 can be set as a data pattern.

Thereafter, when a data write request is received again from the host 300 (S560), the memory controller 200 compares the received data with data stored in the first buffer, that is, a predetermined data pattern, and determines whether to match S570). If the data are not matched, steps S520 to S550 may be performed. The data requested to be written from the host 300 can be written to the memory device 100. [ At this time, the memory controller 200 can update the data pattern of the first buffer by storing the data received from the host 300 in the first buffer. The memory device 100 also writes the data received from the memory controller 200 into a new memory area corresponding to the address signal ADDR and stores the data in the second buffer so that the data of the second buffer You can update the pattern. The updating of the first buffer and the second buffer will be described later in more detail with reference to FIG.

When the data match, the memory controller 200 provides the pattern writing command PW and the address signal ADDR to the memory device 100 (S581). The memory device 100 may output the data pattern stored in the second buffer in response to the pattern write command PW (S582). In one embodiment, when a plurality of data patterns are stored in the second buffer, the memory device 100 may output one data pattern selected in accordance with the pattern write command PW. The memory device 100 writes the data pattern in the memory area corresponding to the address signal ADDR (S583).

Data to be written to the memory device 100 may have temporal locality. For example, when one frame of image data is stored in the memory device 100, there is a high probability that the same data will be continuously stored in the memory device 100. Accordingly, the host 300 can request the memory controller 200 to continuously write the same data. Therefore, the memory controller 200 and the memory device 100 can store data transmitted and received between them in a pattern buffer provided in each of them for data writing. The memory controller 200 provides the pattern writing command PW to the memory device 100 instead of transmitting the data to the memory device 100 again when the host 300 requests writing of the data again , The memory device 100 can output a corresponding data pattern from the pattern buffer according to the pattern write command PW and write it into the memory cell array.

15A and 15B are diagrams showing an embodiment in which, in an electronic device according to an embodiment of the present disclosure, pattern buffers provided in a memory controller and a memory device, respectively, are updated. Figs. 15A and 15B show embodiments of the first pattern buffer and the second pattern buffer update method, which are performed in steps S520 and S540 in the flowchart of Fig.

Referring to FIG. 15A, the memory controller 200 can sequentially receive a plurality of data from the host 300 according to time. At this time, the received data may be the same data as one of the previously received data, or may be new data different from the previously received data. For example, the first data (Data1) may be received, and thereafter the first data (Data1) may be received or the second data (Data2) different from the first data (Data1) may be received. Or after the first data (Data1) is received and after the new data are received, the first data (Data1) can be received again.

The memory controller 200 may store the received data in the first pattern buffer PBUF1 provided therein. Then, the received data is supplied to the memory device 100. The memory device 100 can write the received data into the memory cell array and store it in the second pattern buffer PBUF2 provided therein.

If the new data received from the host 300 is the same as the previously received data, the memory controller 200 may send a pattern write command to the memory device 100 (as described above), instead of providing the data to the memory device 100 200). The pattern write command may include a signal for indicating pattern writing and a signal for selecting pattern data of one of the pattern data stored in the second pattern buffer PBUF2.

For example, when the first data (Data 1) is received together with the write request from the host 300, the memory controller 200 stores the first data (Data 1) in the first pattern buffer PBUF 1 therein, 1 data (Data 1) to the memory device 100. Thereafter, when the first data (Data1) is again received from the host 300, a pattern write command is provided to the memory device 100. [ Thereafter, when the second data (Data2) different from the first data (Data1) is received from the host 300, the second data (Data2) is stored in the first pattern buffer (PBUF1) Can be provided to the memory device 100. In this manner, the memory controller 200 can store N new data in the first pattern buffer PBUF1. At this time, when the first pattern buffer PBUF1 includes N storage areas SR1 to SRN, there is no more area to be stored in the first pattern buffer PBUF1.

1) different from the data stored in the first pattern buffer PBUF1 is received from the host 300, the memory controller 200 receives the first data from the first pattern buffer PBUF1 For example, the first data Data1 and the (N + 1) -th data DataN + 1 in the first pattern buffer PBUF1, among the data stored in the first pattern buffer PBUF1. In this manner, the memory controller 200 can update the data pattern of the first pattern buffer PBUF1 by deleting the old data and storing the old data in the first pattern buffer PBUF1 with the new data.

As another embodiment, when new data, that is, the (N + 1) -th data (DataN + 1) different from the data stored in the first pattern buffer PBUF1 is received from the host 300, (N + 1) th data (DataN + 1) may be stored in the first pattern buffer PBUF1, and the data matched with the data received the longest among the data stored in the first pattern buffer PBUF1 may be deleted.

Referring to FIG. 15B, the memory controller 200 may store data in the first pattern buffer PBUF1 and store the matching order MN of the stored data. At this time, the matching order MN indicates the order of the most recently received from the host 300 among the data stored in the first pattern buffer PBUF1, and the lower the matching order MN is, the more recently received from the host 300 . For example, the matching order (MN) of the data written most recently to the first pattern buffer (PBUF1) or the most recently matched data may be low. When the number of storage areas of the first pattern buffer PBUF1 is N, the matching order MN of the data most recently written or most recently matched to the first pattern buffer PBUF1 is set to 1, The matching order MN of the matched data may be set to N. [ The matching sequence (MN) may be updated each time data is received from the host 300.

All the data is stored in the storage space of the first pattern buffer PBUF1 and new data, for example, the (N + 1) -th data DataN + 1 is received, and the memory controller 200 stores the data matched the longest ago The data pattern of the first pattern buffer PUF1 is updated by deleting the data, i.e., the N-1th data DataN, whose matching order MN is N, and storing the (N + 1) can do.

On the other hand, when data is received from the memory controller 200, the memory device 100 stores the received data in the corresponding memory cell area and also stores the received data in the second internal pattern buffer PBUF2. The memory device 100 may store data received in the second pattern buffer PBUF2 in substantially the same manner as the memory controller 200. [ In one embodiment, the storage capacities of the first pattern buffer PBUF1 and the second pattern buffer PBUF2 are the same, and the data storing order may be set to the same. The data stored in the first pattern buffer PBUF1 and the second pattern buffer PBUF2 and the order of storing the data may be the same. Accordingly, the same data patterns between the memory controller 200 and the memory device 100 are stored in the first pattern buffer PBUF1 and the memory (not shown) of the memory controller 200 without an additional command or an address signal designating a position in the pattern buffer. May be stored at substantially the same position in the second pattern buffer PBUF2 of the device 200, or may be stored in the same order.

16 is a table showing an example of setting of a write command according to the embodiment of the present disclosure. 16 shows an example of setting of a write command transmitted between a memory device and a memory controller to which the write method of FIG. 13 is applied. In this example, data to be written previously is written as a data pattern into the memory cell array 110 (Refer to FIG. 6).

Referring to FIG. 16, the third pattern write command PW3 may be set according to a signal received through some of the address pins (CAx, CAy, CAz, CAj, CAk, CAl). A value received via the upper three address pins (CAx, CAy, CAz) among the illustrated address pins (CAx, CAy, CAz, CAj, CAk, CAl), for example, '0 1 1' And the lower three address pins CAj, CAk, CAl of the address pins CAx, CAy, CAz, CAj, CAk, and CAl indicate a write command to select and write to the memory cell array, Indicates whether to select previously written data. 15A and 15B, the memory device 100 may store a plurality of previous write data in the second pattern buffer PBUF2. The memory device 100 is capable of storing a plurality of patterns stored in the second pattern buffer PBUF2 based on the third pattern write command PW3 received via the illustrated address pins CAx, CAy, CAz, CAj, CAk, Of the previous write data. For example, the second pattern buffer PBUF2 may store eight previous write data, and based on the values received via the three address pins CAj, CAk, CAl of the memory device 100, eight previous writes One of the data may be selected and stored in a memory area corresponding to the address signal ADDR.

16, it is assumed that the second pattern buffer PBUF2 stores eight previous write data. However, this is only an embodiment, and the number of previous write data stored in the second pattern buffer PBUF2 is variable .

17 is a flow chart illustrating a method of writing a memory device according to an embodiment of the present disclosure; The writing method shown in Fig. 17 is an embodiment of the writing method shown in Fig. 9, and shows a method of writing a memory device when setting user setting data to a data pattern.

Referring to FIG. 17, the memory device 100 may receive the pattern store command and data from the memory controller 200 (S610). The pattern store command may be a command that instructs to store the received data in an internal buffer other than the memory cell array 110 of the memory device 100. [ The received data may be user setting data. For example, the user preference data may be data that is primarily stored in the memory device 100, with respect to operation of the electronic device on which the memory device 100 is mounted. A host, such as a host processor, of the electronic device may analyze and provide data to the memory device 100 as user preference data that is primarily stored in the memory device 100.

In response to the pattern store command, the memory device 100 may store the data, i. E., The user configuration data, in an internal buffer (S620). In one embodiment, steps S610 and S620 are performed a plurality of times, and a plurality of user setting data may be stored in the internal buffer.

Thereafter, when the pattern write command and the address are received (S630), the memory device 100 may generate a data pattern based on the user setting data stored in the internal buffer in response to the pattern write command (S640). In one embodiment, the memory device 100 may select one of a plurality of user setup data and output the selected data as a data pattern, in accordance with the pattern write command.

The memory device 100 may write the data pattern, that is, the user setting data, in the memory area corresponding to the address (S650).

18 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied. The electronic device includes a host 300, a memory controller 200 and a memory device 100, and Fig. 18 shows a write operation among the normal operations of the electronic device. In this embodiment, the memory controller 200 and the memory device 100 may each include a pattern buffer for storing data patterns therein, and may store the pattern buffer of the memory controller 200 as a first buffer, 100) will be referred to as a second buffer.

Referring to FIG. 18, the memory controller 200 may receive a data pattern storage request from the host 300 (S710). In one embodiment, if the host 300 transmits invalid address information together with a data write request, data, the memory controller 200 may interpret the write request as a data pattern storage request. The memory controller 200 may store the data received from the host 300 as a data pattern in the first buffer (S720). The data pattern to be stored may be referred to as a user set data pattern. The memory controller 200 may transmit the pattern store command PS and the data pattern DPT, i.e., the user set data pattern, to the memory device 100 (S730). The memory device 100 may store the user data pattern DPT in the second buffer in response to the pattern save command PS (S740). Thereby, a user setting data pattern can be set in the memory controller 200 and the memory device 100.

Thereafter, if a data write request is received from the host 300 (S750), the memory controller 200 may compare the received data with the data pattern stored in the first buffer and determine whether to match (S760). When the data match, the memory controller 200 can transmit the pattern write command PW and the address signal ADDR to the memory device 100 (S771). In response to the pattern write command PW, the memory device 100 can output the data pattern stored in the second buffer (S772). In other words, the memory device 100 may output a user set data pattern.

If the data is not matched, the memory controller 200 can transmit the normal write command NW, the address signal ADDR, and the data DATA to the memory device 100 (S781).

The memory device 100 may write the data pattern or the received data in a memory area corresponding to the address signal ADDR (S782).

19 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure; The memory device 100b of Fig. 19 is a modification of the memory device 100 of Fig. 2, and the above description with reference to Fig. 2 can also be applied to the memory device 100b of Fig.

Referring to FIG. 19, the memory device 100b may include a plurality of banks. A bank may be defined as a set of simultaneously accessible memory cells. The bank is typically divided by the address signal ADDR. Although not particularly shown, can be distinguished by the received bank address signal. Different banks can function independently. For example, the different banks may be independently read and write operations.

One row decoder 140, one read / write circuit 150, and one column decoder 160 may correspond to one memory cell array 110 in FIG. In this case, one memory cell array 110 may constitute one bank. However, the present invention is not limited thereto, and two or more memory cell arrays may constitute one memory bank, and one row decoder 140 or one column decoder 160 may correspond to two or more memory cell arrays .

Meanwhile, the data pattern providing unit 180 and the input / output buffer 170 may be shared by the read / write circuits 150 of different banks. The data pattern providing section 180 provides data patterns to the read / write circuits 150. The input / output buffer 170 transfers data (DATA) output from the read / write circuits 150 to the outside, Or data (DATA) is received from the outside, the received data can be provided to the read / write circuit 150.

In the memory device 100b according to the embodiment of the present disclosure, when a pattern write command is received from the outside, the memory device 100b transfers data provided from the data pattern providing portion 180 to the address signal Can be written in the memory area corresponding to the address ADDR. A read / write operation can be independently performed for different banks, and a read / write operation can be performed simultaneously in different banks. At this time, since the different banks share the input / output buffer 170 and the data pad DQ [m-1: 0], even if the read / write operation is performed simultaneously in different banks, Output buffer 170 and the data pad DQ are used in the case where the other banks use the input / output buffer 170 and the data pad DQ when the input / output buffer 170 and the data pad DQ are used. Wait until the use of the bank is finished. Accordingly, the read / write operation may be delayed. However, according to the pattern write command, the memory device 100b according to the embodiment of the present disclosure does not use the input / output buffer 170 and the data pad DQ when the write operation is performed. Therefore, when the pattern write operation is performed for one bank, the other banks can simultaneously use the input / output buffer 170 and the data pad DQ [m-1: 0] while performing the normal write operation or the read operation have. Thus, the operating speed of the memory device 100b can be improved.

20 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure;

Referring to Fig. 20, the memory system 1000a may include a memory controller 200a and a memory device 100. Fig. The memory controller 200 includes a data comparator 210, a pattern buffer 220 and a data pattern analyzer 230. The memory device 100 includes a memory cell array 110, a read / write circuit 150, And a data pattern providing unit 180. The memory system 100a of Fig. 20 is a modification of the memory system 1000 of Fig. 1, and the contents described with reference to Fig. 1 can also be applied to this embodiment. Therefore, redundant description will be omitted.

The data pattern analyzing unit 230 of the memory controller 200a analyzes data received from an external device such as a host and stores frequently used data, that is, data frequently written in the memory device 100 It can be judged. For example, the data pattern analyzing unit 230 may determine data having a write request count from the host equal to or greater than a predetermined threshold value as frequently used data. The memory controller 200a can store frequently used data as a data pattern in the pattern buffer 220 and transfer it to the memory device 100. [ The memory device 100 may store frequently used data received from the memory controller 200a in a pattern buffer (not shown) provided in the data pattern providing unit 180. [ As a result, frequently used data can be set as a data pattern in the memory controller 200a and the memory device 100. [ In one embodiment, data pattern providing 180 may be a pattern buffer.

The data comparison unit 210 may compare the data requested to be written from the host with the data patterns stored in the pattern buffer 220 and determine whether the write requested data matches one of the data patterns. The memory controller 200a sends the pattern write command and the address signal ADDR to the memory device 100 without sending the data to the memory device 100 when the write requested data matches one of the data patterns Lt; / RTI > The memory device 100 can select one of the data patterns stored in the pattern buffer based on the pattern write command and write the selected data pattern to the memory cell array 110. [

In the memory system 1000a according to the present embodiment, the memory controller 200a analyzes the data requested to be written, determines frequent data to be frequently written to the memory device 100, Is used as a data pattern between the memory controller 200a and the memory device 100 so that data can be transferred between the memory controller 200a and the memory device 100 without interrupting the transfer of data between the memory controller 200a and the memory device 100 110). ≪ / RTI >

21 is a block diagram illustrating one implementation of a memory controller in accordance with an embodiment of the present disclosure; FIG. 21 shows an implementation of the memory controller 200a of the memory system 1000a of FIG.

Referring to FIG. 21, the data pattern analyzing unit 230 analyzes data (DATA) received with a write request from a host to determine frequently used data. In one embodiment, the data pattern analyzing unit 230 may determine data having a write request count from the host equal to or greater than a predetermined threshold as frequently used data. In another embodiment, the data pattern analyzing unit 230 may determine data having the number of write requests from the host equal to or greater than the threshold value as frequently used data within a predetermined time.

The data pattern analyzing unit 230 provides frequently used data to the pattern buffer 220, and the pattern buffer 220 can store frequently used data as a data pattern. A plurality of data patterns (Pattern 1 to Pattern m) may be stored in the pattern buffer 220. The memory controller 200a can transfer the data set as the data pattern to the memory device (100 in Fig. 20) together with the address signal ADDR and the second normal write command NW2. The memory device 100 may store the data in the memory area corresponding to the address signal ADDR and in the pattern buffer inside when the second normal write NW2 is transmitted. As a result, the data can be set to a data pattern in the memory controller 200a and the memory device 100. [

When the write request is received from the host, the data comparison unit 210 may compare the data (DATA) requested to be written with a plurality of data patterns (Pattern 1 to Pattern m) stored in the pattern buffer 220 . When the data DATA matches one of the plurality of data patterns (Pattern 1 to Pattern m), the memory controller 200a can transfer the pattern write command PW and the address signal ADDR to the memory device 100 . If the data DATA does not match any of the plurality of data patterns (Pattern 1 to Pattern m), the memory controller 200a sets the first normal write command NW1, the data DATA and the address signal ADDR to To the memory device (100). The memory device 100 can output one of the data patterns stored in the internal pattern buffer and write the output data in the memory area corresponding to the address signal ADDR based on the pattern write command PW . Further, the memory device 100 can write the received data (DATA) in the memory area corresponding to the address signal ADDR, based on the first normal write command NW1.

22 is a table showing an example of setting of a write command according to the embodiment of the present disclosure.

Referring to FIG. 22, when a mode signal of '0 0 0' is received through the address pins CAx, CAy, and CAz, this indicates the first normal write command NW1. Data can be transmitted from the memory controller 200a to the memory device 100 via the data pad DQ when a mode signal of '0 0 0' is received via the address pins CAx, CAy, CAz. The memory device 100 can write data received from the memory controller 200 to the memory cell array 110 in response to the first normal write command NW1.

 When a mode signal of '0 0 1' is received via the address pins CAx, CAy, and CAz, this indicates the second normal write command NW2. Data can be transmitted from the memory controller 200a to the memory device 100 via the data pad DQ when a mode signal of '0 0 1' is received via the address pins CAx, CAy, CAz. The memory device 100 can write the data received from the memory controller 200 to the memory cell array 110 and the pattern buffer in response to the first normal write command NW1. In this way, the data pattern can be stored in the pattern buffer of the memory device 100.

If the signal received via the upper one pin CAx of the address pins CAx, CAy and CAz is '0', this means that the buffer data, that is, the pattern written to the memory cell array to write the data written in the pattern buffer Indicates the command PW. The data pad DQ is not used because there is no data transmission / reception between the memory controller 200a and the memory device 100 when the pattern write command PW is received. As described above with reference to FIGS. 20 and 21, the data written to the pattern buffer may be frequently used data. One of the data patterns stored in the pattern buffer may be selected and output according to a signal received via the lower two pins CAy, CAz among the address pins CAx, CAy, CAz.

22, a write command that can be transmitted to the memory device 100 of the memory system 1000a of FIG. 20 has been exemplarily described. However, the present invention is not limited thereto, and the signals indicating the normal write command and the pattern write command can be set variously.

23 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring to Fig. 23, the memory system 1000c may include a memory controller 200c and a memory device 100c. The memory controller 200c may include a pattern buffer 220 and the memory device 100c may include a memory cell array 110 and a data pattern providing unit 180 and a data comparing unit 185. [ Although not shown, the memory controller 200c may further include a data comparing unit and a data pattern analyzing unit.

As described above with reference to Figs. 1 to 22, the memory controller 200c and the memory device 100c contract the data pattern in advance, and when the data requested to be written from the host matches the data pattern, the memory controller 200c Instead of transferring the data to the memory device 100c, the memory device 100c transmits a predetermined pattern write command, and the memory device 100c can write the data pattern to the memory cell array 110 in response to the pattern write command have.

On the other hand, if the data read out from the memory cell array 110 in the memory system 1000c of FIG. 23 matches the data pattern, the memory device 100c can transfer the data read out to the memory controller 200c, Pattern reading signals, such as the matching signal (RDM) and pattern information (BPIF), to the memory controller 200c. The memory controller 200c can transmit the data pattern to the outside, e.g., the host, based on the received pattern read signals.

More specifically, when the memory controller 200c transfers the read command CMD and the address signal ADDR to the memory device 100c, the memory device 100c outputs the address signal ADDR to the memory cell array 110 The data can be read from the memory area of the flash memory. The data comparing unit 185 may compare the read data with the data pattern received from the data pattern providing unit 180 or access the data pattern providing unit 180 to compare the stored data pattern with the read data . The data comparing unit 185 may generate a matching signal RDM indicating that the read data is matched with the data pattern if the read data matches the data pattern.

The memory device 100c may send the matching signal RDM to the memory controller 200c. In addition, when the read data is matched with one of the plurality of data patterns, the memory device 100c stores information on the matched data pattern (e.g., the position of the matched data pattern in the pattern buffer) BPIF to the memory controller 200c.

The memory controller 200c can provide data received from the memory device 100c to the host as a read signal. However, when the matching signal RDM is received from the memory device 100c, the memory device 100c does not transmit the read data to the memory controller 200c. The memory controller 200c can transmit a predetermined data pattern to the host when the matching signal RDM is received. In the embodiment, when a plurality of data patterns are stored in the pattern buffer 220, the memory controller 200c selects one of the plurality of data patterns based on the pattern information (BPIF) received from the memory device 100c And transmit the selected data pattern to the host.

As described above, in the memory system 1000c according to the present embodiment, when the data read from the memory cell array 110 matches the preset data pattern, the memory controller 200c receives data from the memory device 100c , The data pattern can be transmitted to the host as read data based on the preset pattern readout signals. Therefore, since data transmission / reception does not occur between the memory controller 200c and the memory device 100c, the power consumption of the memory system 1000c can be reduced. In addition, since the data transfer time at the time of reading is reduced, the operating speed of the memory system 1000c can be improved.

Specific configurations and operations of the memory device 100c and the memory controller 200c will be described below with reference to FIGS. 24 and 25. FIG.

24 is a block diagram that schematically illustrates a memory device according to an embodiment of the present disclosure; The memory device 100c of Fig. 24 can be applied to the memory system 1000c of Fig. Fig. 24 shows the main configuration of the memory device in relation to the read operation, and the configurations of the memory device shown in Fig. 2 may be provided in the memory device 100c of Fig.

Referring to FIG. 24, the memory device 100c may include a memory cell array 110, a read circuit 152, an output buffer 172, a data pattern providing unit 180, and a data comparing unit 185.

The reading circuit 152 can read data from the memory area of the memory cell array 110 corresponding to the address signal. The read data may be provided to the output buffer 172 and the data comparator 185.

The output buffer 172 is a constitution of the input / output buffer 170 of FIG. 2 and can transmit data (DATA) to the outside via the data pad DQ.

The data pattern providing unit 180 may output a predetermined data pattern. In one embodiment, the data pattern providing unit 180 may generate a predetermined data pattern. In another embodiment, the data pattern providing unit 180 may include a pattern buffer 181 for storing a plurality of data patterns.

The data comparing unit 185 can compare the read data received from the reading circuit 152 with the data pattern output from the data pattern providing unit 180. [ Or the data comparison unit 185 may access the pattern buffer 185 to compare the read data with a plurality of data patterns. The data comparison unit 185 may output the matching signal RDM. If the read data matches the data pattern, the data comparator 185 outputs a first level, for example, a logic high matching signal RDM, and if the read data does not match the data pattern, 185 may output a second level, e.g., a logic low matching signal (RDM). The matching signal RDM may be provided to the output buffer 172 and the memory controller (200c in Fig. 23).

If the read data does not match the data pattern, the output buffer 172 can output the data read through the data pad DQ to the memory controller 200c. However, if the read data matches the data pattern, the output of the output buffer 172 may be interrupted. The output buffer 172 may be cut off in response to the first level of matching signal RDM. Accordingly, the read data can not be transmitted through the data pad DQ. When the read data is matched with one of the plurality of data patterns stored in the pattern buffer 181, the data pattern preparation unit 180 generates pattern information BPIF indicating the position of the matched data pattern in the pattern buffer 181, Can be output. The pattern information (BPIF) may be provided to the memory controller 200c.

25 is a block diagram schematically illustrating a memory controller according to an embodiment of the present disclosure; The memory controller 200c of Fig. 25 can be applied to the memory system 1000c of Fig.

Referring to FIG. 25, the memory controller 200c may include a pattern buffer 220, a data input buffer 9260, and a selector 290. FIG.

The memory controller 200c can receive the data (DATA) and the matching signal (RDM) from the memory device 100c. The memory controller 200c can also receive pattern information (BPIF) from the memory device 100c.

Data input buffer 260 may receive data (DATA) from memory device 100c. The received data (DATA) can be transmitted to the host (Host) as read data (RDATA) via the selector (290).

The pattern buffer 220 may store a plurality of pattern data (Pattern1 to Pattern m). The pattern buffer 220 can select and output one of a plurality of pattern data (Pattern 1 to Pattern m) based on the pattern information (BPIF). The output pattern data can be transmitted to the host as read data (RADAT) via the selector 290. [

The selector 290 can output one of the data DATA provided from the data input buffer 260 and the data pattern provided from the pattern buffer 220 as the read data RDATA based on the matching signal RDM have. The selector 290 outputs the data pattern in response to the first level matching signal RDM and outputs the data DATA provided from the input buffer 270 in response to the second level matching signal RDM can do.

26 is a flowchart showing an operation method of an electronic device to which a memory device according to an embodiment of the present disclosure is applied. 26 shows a read operation among the normal operations of the electronic device. The electronic device includes a host 300, a memory controller 200 and a memory device 100. The memory controller 200 includes the memory controller 200c described with reference to Figures 23 and 25, ) May include the memory device 100c described with reference to Figures 23 and 24. [

Referring to Fig. 26, the memory device 100 and the memory controller 200 set data patterns (S811, S812). The data pattern can be commonly set in the memory controller 200 and the memory device 100 as mutually agreed data between the memory device 100 and the memory controller 200. [

When a data read request is received from the host 300 in operation S820, the memory controller 200 transmits a read command RDCMD and an address signal ADDR to the memory device 100 in operation S830.

The memory device 100 can read data from the memory area corresponding to the address signal ADDR (S840). The memory device 100 may determine whether the read data matches the data pattern (S850). The memory device 100 may compare the read data with a preset data pattern and judge whether or not to match.

When the data is matched, the memory device 100 may transmit the matching signal RDM and the pattern information BPIF to the memory controller 200 (S861). When there are a plurality of preset data patterns, the memory controller 8610 selects one of a plurality of data patterns based on the pattern information (BPIF) (S870), and transmits the selected data pattern as read data to the host 300 (S881).

When the data is not matched, the memory device 100 sends the read data to the memory controller 200 and the memory controller 200 sends the data received from the memory device 100 as read data to the host 300 (S882).

Figure 27 is a block diagram illustrating a memory system according to an embodiment of the present disclosure, and Figure 28 shows a timing diagram of an input signal applied to a rank of a memory system.

27, memory system 1000d may include a plurality of ranks 1100, 1200 and a memory controller 200. [ The plurality of ranks 1100 and 1200 may be mounted on one memory module. The rank may be defined as a memory device that receives a command and an address signal at the same time, and is selected according to the same chip select signal CS. For example, in a memory module, a rank may be defined as a set of DRAM chips selected according to the same chip select signal CS. The rank can be distinguished by using the chip select signal CS provided to the memory module.

The first rank 1100 includes first to fourth memory devices 101, 102, 103 and 104 and the second rank 1200 includes fifth to eighth memory devices 105, 106, 107, . ≪ / RTI > At least one of the first to eighth memory devices 101 to 108 may be implemented with the memory device 100, 100a according to the embodiments of the present disclosure described with reference to Figs.

The memory devices 101 to 108 of the first rank 1100 and the second rank 1200 can simultaneously receive the command / address signal C / A. At this time, the memory devices 101 to 104 of the first rank 1100 are selected by the first chip select signal CS0 and the memory devices 105 to 108 of the second rank 1200 are selected by the second chip Can be selected by the selection signal CS1. The memory devices 101-108 of the first rank 1100 and the second rank 1200 are connected to the data bus 400 via data pads DQ [m-1: 0], respectively.

The first rank 1100 and the second rank 1200 share the data bus 400. If the first rank 1100 is using the data bus 400, the second rank 1200 can not use the data bus 400. For example, when data is to be written to the first rank 1100 and the second rank 1200, the memory controller 200 transmits the write command and data to the first rank 1100, It is possible to wait until the completion of the occupation of the data bus 400 of the first rank 1100 and then send the write command and data to the second rank 1200. [ Accordingly, the data transmission / reception delay time through the data bus 400 affects the operation speed of the memory system 1000a.

However, according to the method of operation of the memory device and the memory system according to the embodiment of the present disclosure described with reference to Figs. 1 to 26, when executing the pattern write command in the first rank 1100, the first rank 1100, The data bus 400 is not used because the data bus 400 does not receive data from the memory controller 200. Therefore, the memory controller 200 can transmit a write command (pattern write command or normal write command) and data to the second rank 1200 immediately after transmitting the pattern write command to the first rank 1100. The second rank 1100 may receive data via the data bus 400. Similarly, the memory controller 200 transmits a read command to the second rank 1200 immediately after transmitting the pattern write command to the first rank 1100, and receives the read data from the second rank 1200 . Accordingly, when the first rank 1100 executes the pattern write command, the second rank 1200 can directly execute the write or read command.

28, write commands, such as pattern write commands and normal write commands PW, NW, can be received in synchronization with the rising edge of the clock signal CLK in a write operation. As shown, when the pattern write command PW is received, no data is received. The data Din may be received after a predetermined time after the normal write command NW is received and the time at which the data Din is received may be longer than the time at which the command CMD is received relatively.

As shown, the pattern write command PW can be received in the first rank 1100, Rank0. The time period during which the data Din is received is not required in the first period T1 according to the pattern write command PW. Therefore, after the pattern write command PW is received in the first rank 1100 in response to the rising edge (or clock) of the clock signal CLK, the clock signal CLK is synchronized with the next rising edge (or the next clock) (1200, Rank 1) may be received. When the first rank 1100 executes the pattern write command, the second rank 1200 can directly execute the normal write command. Thus, the operating speed of the memory system 1000d can be improved. Also, when pattern writing is performed, there is no data transmission / reception between the memory controller 200 and the memory device, and the data bus 400 is not used, so that the data bus efficiency can be improved.

29A and 29B are block diagrams illustrating memory controllers and memory modules according to embodiments of the present disclosure.

29A, a memory system 2000A includes a memory module 2100A and a memory controller 2200A. The memory module 2100A may include a printed circuit board 2120A, a plurality of memory chips 2110A, and a connector 2130A. The plurality of memory chips 2110A may be coupled to the upper surface and the lower surface of the printed circuit board 2120A. The connector 2130A is electrically connected to the plurality of memory chips 2110A via conductive lines (not shown). Also, the connector 4230A can be connected to a slot of an external host. Memory module 2100A may be in the form of a dual in-line memory module (DIMM).

The plurality of memory chips 2110A may include nonvolatile memory cells such as volatile memory such as DRAM cells or STT-MRAM cells. At this time, the memory chips 2110A can store data of the computer system such as an operation memory, a cache memory, etc. in the short term or temporarily.

The plurality of memory chips 2110a may be arranged in two rows in the longitudinal direction of the printed circuit board 2120A. The memory chips 2110A in the first row relatively far from the connector 4230A constitute the first rank R0 and the memory chips in the adjacent second row from the connector 4230A constitute the second rank Rl .

The first rank R0 and the second rank R1 may be activated by different selection signals.

The memory controller 2200A can perform an operation of queuing a command or outputting a command. A DRAM interface may be applied between memory controller 2200A and memory module 2100A in a memory system. According to the DRAM interface according to the embodiment of the present disclosure, when the data to be stored in the memory chip 21100A matches a preset data pattern, the memory controller 2200A transmits a pattern write command and an address signal to the memory chip 21100A And data may not be transmitted. The memory chip 2110A can internally generate the data pattern and write the generated data pattern to the memory cell array in response to the pattern write command without receiving the data. The memory chip 2110A has a pattern buffer for storing data patterns, and can write one of the data patterns stored in the pattern buffer to the memory cell array in response to the pattern write command.

In the memory system 2000A of FIG. 29A, the memory controller 2200A is shown separately from the memory module 2100A, but the memory controller 2200A may be included in the memory module 2100A. Memory controller 2200A may be coupled to the top or bottom surface of printed circuit board 2110A and may communicate with memory chips 2110A via conductive lines (not shown).

29B, the memory system 2000B includes a memory module 2100B and a memory controller 2200B, and the memory module 2100B includes one or more semiconductor chips each including a cell array, And a buffer chip 2110B for managing memory operations for the array.

Buffer chip 2120B may receive commands, address signals and data from memory controller 2200B and provide commands and data to selected ones of the ranks R0 and R1. The buffer chip 2120B may include a pattern buffer 2111B. When a pattern write command is received from the memory controller 2200B, the buffer chip 2120B outputs a data pattern corresponding to the pattern write command from the pattern buffer 2111B and is included in a selected one of the plurality of ranks R0 and R1 To the memory chips 2110B. When the normal write command is received from the memory controller 2200B, the buffer chip 2120B transfers the data received from the memory controller 2200B to the memory chips 2110B included in the selected one of the plurality of ranks R0 and R1 .

In the example of FIG. 29B, an example in which a part of the function of the memory controller is performed in the memory module of the LRDIMM type is shown, but the embodiment of the present invention need not be limited thereto. For example, as an FBDIMM type memory module is applied, an AMB (Advanced Memory Buffer) chip may be mounted on a memory module as a management chip. In addition, another type of memory module may be applied, and at least a part of the functions of the memory controller described above may be implemented in the memory module.

30 is a block diagram showing a memory device having a stacked structure including a plurality of semiconductor layers.

Referring to FIG. 30, the memory device 3000 may include a plurality of semiconductor layers LA1 to LAn. Each of the semiconductor layers LA1 to LAn may be a memory chip including a memory cell array 1100. [ Alternatively, a part of the semiconductor layers LA1 to LAn may be a memory chip, and another part (or any one layer) may be a controller chip for interfacing with a memory chip. In the example of Fig. 30, it is assumed that the n-th layer (LAn) is a controller chip.

The controller chip LAn communicates with the memory chips LA1 to LAn-1 and controls the operation mode of the memory chips LA1 to LAn-1. The controller chip LAn can control various functions, characteristics and modes using the mode registers of the memory chips LA1 to LAn-1. Further, the controller chip (LAn) can perform an operation of queuing a command or outputting a command.

In addition, the controller chip (LAn) may include a pattern buffer (3210). When a pattern write command is received from the memory controller (not shown), the controller chip LAn outputs a data pattern corresponding to the pattern write command from the pattern buffer 3210 and supplies it to the memory chips LA1 to LAn-1 . When the normal write command is received from the memory controller, the controller chip LAn can provide the data received from the memory controller to the memory chips LA1 to LAn-1.

The plurality of semiconductor layers LA1 to LAn of the stacked structure in the memory device 3000 may be interconnected through a through silicon via (TSV)

31 is a block diagram illustrating a computer system in accordance with an embodiment of the present disclosure;

The computer system 4000 may be a desktop computer, a notebook computer, a workstation, a handheld device, a wearable device, or the like. 21, the computer system 4000 includes a processor 4100, a system controller 4200, and a memory system 4300. [ The computer system 4000 may further include a processor bus 4510, an expansion bus 4520, an input device 4410, an output device 4420 and a storage device 4430. The memory system 4300 may include at least one memory device 4320 and a memory controller 4310. The memory controller 4310 may be included in the system controller 4200.

The processor 4100 may be capable of executing various computing systems, such as executing particular calculations or specific software executing tasks. For example, the processor 4100 may be a microprocessor or a central processing unit. The processor 4100 may be coupled to the system controller 4200 via a processor bus 4510 that includes an address bus, a control bus, and / or a data bus. The system controller 4200 is coupled to an expansion bus 4520, such as a Peripheral Component Interconnection (PCI) bus. Accordingly, processor 4100 may be coupled to system controller 4200 via one or more input devices 4410, such as a keyboard or a mouse, one or more output devices 4420, such as a printer or display device, or a hard disk drive, And may control one or more storage devices 4430, such as CD-ROMs.

The memory controller 4310 may control the memory device 4320 to perform the instructions provided by the processor 4100. [ The memory device 4320 may store the data provided from the memory controller 4310 and provide the stored data to the memory controller 4310. [ The memory device 4320 may include a plurality of memory chips, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a non-volatile memory chip .

According to the embodiment of the present disclosure, when the write data supplied with the write command from the processor 4100 matches the preset data pattern, the memory controller 4310 writes the pattern to the memory device 4320 without transmitting the data Command can be transmitted. The memory device 4320 can store the write data requested to be written from the processor 4100 by writing a predetermined data pattern into the memory cell array. As a result, data transmission / reception between the memory controller 4310 and the memory device 4320 is reduced, so that the power consumption of the computer system 4000 can be reduced and the operation speed of the computer system 4000 can be improved .

32 is a block diagram illustrating a computer system including a memory system in accordance with an embodiment of the present disclosure; 32, a computer system 5000 may include a central processing unit 5200, a modem 5300, a user interface 5400 and a memory system 5500 that are electrically connected to the system bus 5100 . The memory device 5520 may include volatile memory cells such as DRAM cells or non-volatile memory cells such as STT-MRAM cells.

The memory system 5500 may include a memory device 5520 and a memory controller 5510. The memory device 5520 may store data processed by the central processing unit 5200 or externally input data. The memory device 5520 may be applied to a main memory application that stores data for storing a large amount of data required for the computer system 5000, or data requiring quick access such as system data.

A memory system 5500 according to an embodiment of the present disclosure may include a data transmission link 5510 between a memory controller 5510 and a memory device 5520 when data input from the central processing unit 5200 or externally matches a predetermined data pattern. / RTI > may store the data in memory device 5520 without receiving / receiving data. The memory controller 5510 sends a pattern write command to the memory device 5520 to write a preset data pattern. The memory device 5520 can internally store the data input from the central processing unit 5200 or by externally generating the data pattern internally in response to the pattern write command and storing the generated data pattern. The data transmission / reception between the memory controller 5510 and the memory device 5520 is reduced, so that the power consumption of the computer system 5000 can be reduced and the operation speed of the computer system 5000 can be improved.

Although not shown, the computer system 5000 may further include an application chipset, a camera image processor (CIS), an input / output device, and the like.

Although the present disclosure has been described with reference to the embodiments shown in the drawings, it is to be understood that various modifications and equivalent embodiments may be made by those skilled in the art without departing from the scope and spirit of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

100, 100a, 100b: memory device
200, 200a: memory controller
180: Data pattern offerer
170: I / O buffer
1000: Memory system

Claims (10)

A memory controller for comparing input data input from the outside with a preset data pattern and transmitting a pattern write command and address information when the input data and the data pattern match; And
And a memory device for internally outputting the data pattern in response to the pattern write command and writing the data pattern in a memory area corresponding to the address information. 2. The apparatus of claim 1, wherein the memory controller
When the input data matches one of the plurality of data patterns, transmits the pattern write command having a set value corresponding to the data pattern to the memory device ≪ / RTI > 2. The apparatus of claim 1, wherein the memory controller
A first pattern buffer for storing the data pattern; And
And a comparator for comparing the input data with the data pattern stored in the pattern buffer. 4. The memory device according to claim 3,
And a second pattern buffer for storing the data pattern,
Wherein the data patterns stored in the first pattern buffer and the second pattern buffer are the same. The memory controller according to claim 3,
If the input data and the data pattern do not match,
And updates the pattern buffer by storing the input data in the pattern buffer. The memory controller according to claim 3,
Further comprising a data pattern analyzing unit that analyzes the input data and determines input data having a write request to the memory device equal to or greater than a predetermined threshold value as the data pattern. 2. The method of claim 1,
And the memory controller is one of data transmitted to the memory device. The memory device according to claim 1,
And a controller for comparing the read data with the data pattern in response to the read command and transmitting the matching signal to the memory controller when the read data and the data pattern match,
Wherein the memory controller outputs the data pattern provided from the internal buffer to the outside in response to the matching signal. 2. The method of claim 1,
Wherein the data includes at least two of the following: data whose consecutive bits are '0' or '1'; data previously written to the memory device; and data provided from the outside. The method according to claim 1,
Each including a first rank and a second rank that share at least one of the memory devices and share a data bus,
When the first rank receives the first write command in response to a first clock of a clock signal provided from the memory controller and performs a write operation according to the received first write command, A second write command, a second write command, or a read command in response to a second clock of the clock signal, and performs a write operation or a read operation in accordance with the received command ≪ / RTI >

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