KR20170075835A

KR20170075835A - Memory system and operating method of memory system

Info

Publication number: KR20170075835A
Application number: KR1020150184649A
Authority: KR
Inventors: 변유준
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2015-12-23
Filing date: 2015-12-23
Publication date: 2017-07-04
Also published as: US10073628B2; US20170185295A1; CN106909316A

Abstract

The present invention relates to a memory system for processing data in a memory device and a method of operating the memory system, including a plurality of pages including a plurality of memory cells connected to a plurality of word lines, A memory device including a plurality of memory blocks including the pages; And a command execution unit operable to perform a command operation corresponding to a command received from the host and to confirm a parameter for the memory blocks corresponding to the command operation, Correspondingly, a controller for selecting source memory blocks and target memory blocks in the memory blocks, respectively, may be included.

Description

[0001] MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system, and more particularly, to a memory system for processing data in a memory device and a method of operating the memory system.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use memory systems that use memory devices, i. E., Data storage devices. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because there is no mechanical driving part, and the access speed of information is very fast and power consumption is low. As an example of a memory system having such advantages, a data storage device includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

Embodiments of the present invention provide a memory system and a method of operating a memory system that can minimize the complexity and performance degradation of a memory system and maximize utilization efficiency of the memory device to reliably process the data.

A memory system according to embodiments of the present invention includes a plurality of pages including a plurality of memory cells connected to a plurality of word lines and storing data and a plurality of memory blocks including the pages A memory device; And a command execution unit operable to perform a command operation corresponding to a command received from the host and to confirm a parameter for the memory blocks corresponding to the command operation, Correspondingly, a controller for selecting source memory blocks and target memory blocks in the memory blocks, respectively, may be included.

Here, in the memory blocks, the controller selects, as a first source memory block and a first target memory block, memory blocks having a top-level parameter; In the memory blocks, the memory blocks having the lowest parameter may be selected as the second source memory block and the second target memory block.

The controller may swap between the first source memory block and the second target memory block; And swap between the second source memory block and the first target memory block.

In addition, the controller can confirm update parameters for the memory blocks corresponding to a read operation or a program operation in the command operation.

In addition, the controller may identify, in the memory blocks, the first source memory block having the maximum update parameter; In the memory blocks, the first source memory block having the minimum update parameter can be identified.

The controller may check the erase parameters for the memory blocks in accordance with an erase operation in the command operation.

Identifying the first target memory block having the largest erase parameter in the memory blocks; It is possible to identify the first target memory block having the minimum erase parameter in the memory blocks.

The controller records the parameters for the memory blocks in each of the indexes of the memory blocks to generate a list and stores the list in the memory of the controller, In response to the command operation, the parameters recorded in the list can be updated.

The controller may arrange the memory blocks according to the parameters recorded in the list, and then sequentially select the aligned memory blocks as the source memory blocks and the target memory blocks, respectively.

Also, in the aligned memory blocks, hot memory blocks are selected as a first source memory block and a first target memory block; In the aligned memory blocks, cold memory blocks may be selected as a second source memory block and a second target memory block.

A method of operating a memory system in accordance with embodiments of the present invention is a method for operating a plurality of pages each including a plurality of memory cells that are included in a plurality of memory blocks of a memory device and are connected to a plurality of word lines Receiving a command from a host; Performing a command operation corresponding to the command between the controller of the memory device and the memory blocks; Confirming a parameter for the memory blocks corresponding to the command operation; And selecting source memory blocks and target memory blocks in the memory blocks, respectively, corresponding to the parameter.

Wherein the selecting comprises: selecting, in the memory blocks, memory blocks having a top parameter as a first source memory block and a first target memory block; And selecting the memory blocks having the lowest parameter as the second source memory block and the second target memory block in the memory blocks.

Swapping between the first source memory block and the second target memory block; And swapping between the second source memory block and the first target memory block.

The confirming step may include checking an update parameter for the memory blocks corresponding to a read operation or a program operation in the command operation.

In addition, the selecting may include: identifying, in the memory blocks, the first source memory block having the maximum update parameter; And identifying, in the memory blocks, the first source memory block having the minimum update parameter.

The verifying may include checking an erase parameter for the memory blocks corresponding to an erase operation in the command operation.

Also, the selecting may include: identifying the first target memory block having the maximum erase parameter in the memory blocks; And checking the first target memory block having the minimum erase parameter in the memory blocks.

Generating a list by recording each of the parameters for the memory blocks in an index for the memory blocks, respectively; Storing the list in a memory of the controller; And updating the parameter recorded in the list, corresponding to the command operation.

And arranging the memory blocks according to the parameters recorded in the list; The selecting may comprise sequentially selecting the aligned memory blocks as the source memory blocks and the target memory blocks, respectively.

In addition, the selecting may comprise: in the aligned memory blocks, selecting hot memory blocks as a first source memory block and a first target memory block; And selecting the cold memory blocks as the second source memory block and the second target memory block in the aligned memory blocks.

The memory system and the method of operating the memory system according to embodiments of the present invention minimize the complexity and performance degradation of the memory system and maximize the utilization efficiency of the memory device to quickly and reliably process the data.

1 schematically illustrates an example of a data processing system including a memory system in accordance with an embodiment of the present invention;
Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention;
3 schematically shows a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention.
Figures 4-11 schematically illustrate a memory device structure in a memory system according to an embodiment of the present invention.
12 schematically illustrates an example of data processing operations in a memory device in a memory system according to an embodiment of the present invention.
13 schematically illustrates an operation of processing data in a memory system according to an embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation according to the present invention will be described, and the description of other parts will be omitted so as not to disturb the gist of the present invention.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 1, a data processing system 100 includes a host 102 and a memory system 110.

And, the host 102 includes portable electronic devices such as mobile phones, MP3 players, laptop computers, and the like, or electronic devices such as desktop computers, game machines, TVs, projectors and the like.

The memory system 110 also operates in response to requests from the host 102, and in particular stores data accessed by the host 102. In other words, the memory system 110 may be used as the main memory or auxiliary memory of the host 102. [ Here, the memory system 110 may be implemented in any one of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may be a solid state drive (SSD), an MMC, an embedded MMC, an RS-MMC (Reduced Size MMC), a micro- (Universal Flash Storage) device, a Compact Flash (CF) card, a Compact Flash (CF) card, a Compact Flash A memory card, a smart media card, a memory stick, or the like.

In addition, the storage devices implementing the memory system 110 may include a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like, a read only memory (ROM), a mask ROM (MROM) Nonvolatile memory devices such as EPROM (Erasable ROM), EEPROM (Electrically Erasable ROM), FRAM (Ferromagnetic ROM), PRAM (Phase change RAM), MRAM (Magnetic RAM), RRAM .

The memory system 110 also includes a memory device 150 that stores data accessed by the host 102 and a controller 130 that controls data storage in the memory device 150. [

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. In one example, controller 130 and memory device 150 may be integrated into a single semiconductor device to configure an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be dramatically improved.

The controller 130 and the memory device 150 may be integrated into one semiconductor device to form a memory card. For example, the controller 130 and the memory device 150 may be integrated into a single semiconductor device, and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM) (SD), miniSD, microSD, SDHC), universal flash memory (UFS), and the like can be constituted by a memory card (SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro)

As another example, memory system 110 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, Tablet computers, wireless phones, mobile phones, smart phones, e-books, portable multimedia players (PMPs), portable gaming devices, navigation devices navigation device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a smart television, a digital audio recorder A digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a data center, Constituent Storage, an apparatus capable of transmitting and receiving information in a wireless environment, one of various electronic apparatuses constituting a home network, one of various electronic apparatuses constituting a computer network, one of various electronic apparatuses constituting a telematics network, (radio frequency identification) device, or one of various components that constitute a computing system.

Meanwhile, the memory device 150 of the memory system 110 can store data stored even when power is not supplied. In particular, the memory device 150 stores data provided from the host 102 via a write operation, And provides the stored data to the host 102 via the operation. The memory device 150 further includes a plurality of memory blocks 152,154 and 156 each of which includes a plurality of pages and each of the pages further includes a plurality of And a plurality of memory cells to which word lines (WL) are connected. In addition, the memory device 150 may be a non-volatile memory device, for example a flash memory, wherein the flash memory may be a 3D three-dimensional stack structure. Here, the structure of the memory device 150 and the 3D solid stack structure of the memory device 150 will be described in more detail with reference to FIG. 2 to FIG. 11, and a detailed description thereof will be omitted here .

The controller 130 of the memory system 110 then controls the memory device 150 in response to a request from the host 102. [ For example, the controller 130 provides data read from the memory device 150 to the host 102 and stores data provided from the host 102 in the memory device 150, Write, program, erase, and the like of the memory device 150 in accordance with an instruction from the control unit 150. [

More specifically, the controller 130 includes a host interface (Host I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, A power management unit (PMU) 140, a NAND flash controller (NFC) 142, and a memory 144.

In addition, the host interface unit 134 processes commands and data of the host 102 and is connected to a USB (Universal Serial Bus), a Multi-Media Card (MMC), a Peripheral Component Interconnect-Express (PCI-E) , Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI) May be configured to communicate with the host 102 via at least one of the interface protocols.

In addition, when reading data stored in the memory device 150, the ECC unit 138 detects and corrects errors contained in the data read from the memory device 150. [ In other words, the ECC unit 138 performs error correction decoding on the data read from the memory device 150, determines whether or not the error correction decoding has succeeded, outputs an instruction signal according to the determination result, The parity bit generated in the process can be used to correct the error bit of the read data. At this time, if the number of error bits exceeds the correctable error bit threshold value, the ECC unit 138 can not correct the error bit and output an error correction fail signal corresponding to failure to correct the error bit have.

Herein, the ECC unit 138 includes a low density parity check (LDPC) code, a Bose (Chaudhri, Hocquenghem) code, a turbo code, a Reed-Solomon code, a convolution code, ), Coded modulation such as trellis-coded modulation (TCM), block coded modulation (BCM), or the like, may be used to perform error correction, but the present invention is not limited thereto. In addition, the ECC unit 138 may include all of the circuits, systems, or devices for error correction.

The PMU 140 provides and manages the power of the controller 130, that is, the power of the components included in the controller 130. [

The NFC 142 also includes a memory interface 142 that performs interfacing between the controller 130 and the memory device 142 to control the memory device 150 in response to a request from the host 102. [ When the memory device 142 is a flash memory, and in particular when the memory device 142 is a NAND flash memory, the control signal of the memory device 142 is generated and processed according to the control of the processor 134 .

The memory 144 stores data for driving the memory system 110 and the controller 130 into the operation memory of the memory system 110 and the controller 130. [ The memory 144 controls the memory device 150 in response to a request from the host 102 such that the controller 130 is able to control the operation of the memory device 150, The controller 130 provides data to the host 102 and stores the data provided from the host 102 in the memory device 150 for which the controller 130 is responsible for reading, erase, etc., this operation is stored in the memory system 110, that is, data necessary for the controller 130 and the memory device 150 to perform operations.

The memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), or a dynamic random access memory (DRAM). The memory 144 also stores data necessary for performing operations such as data writing and reading between the host 102 and the memory device 150 and data for performing operations such as data writing and reading as described above And includes a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like, for storing such data.

The processor 134 controls all operations of the memory system 110 and controls a write operation or a read operation to the memory device 150 in response to a write request or a read request from the host 102 . Here, the processor 134 drives firmware called a Flash Translation Layer (FTL) to control all operations of the memory system 110. The processor 134 may also be implemented as a microprocessor or a central processing unit (CPU).

The processor 134 also includes a management unit (not shown) for performing bad management of the memory device 150, such as bad block management, A bad block is checked in a plurality of memory blocks included in the device 150, and bad block management is performed to bad process the identified bad block. Bad management, that is, bad block management, is a program failure in a data write, for example, a data program due to the characteristics of NAND when the memory device 150 is a flash memory, for example, a NAND flash memory. Which means that the memory block in which the program failure occurs is bad, and the program failed data is written to the new memory block, that is, programmed. When the memory device 150 has a 3D stereoscopic stack structure, when the block is processed as a bad block in response to a program failure, the use efficiency of the memory device 150 and the reliability of the memory system 100 are rapidly So it is necessary to perform more reliable bad block management. Hereinafter, the memory device in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIG. 2 to FIG.

Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention, Figure 3 schematically illustrates a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention. And FIGS. 4 to 11 are views schematically showing a structure of a memory device in a memory system according to an embodiment of the present invention, and schematically the structure when the memory device is implemented as a three-dimensional nonvolatile memory device Fig.

2, the memory device 150 includes a plurality of memory blocks, such as block 0 (Block 0) 210, block 1 (block 1) 220, block 2 (block 2) 230, and and the block N-1 (BlockN-1) (240) each block comprising a (210 220 230 240), includes a plurality of pages (pages), for example the 2 ^M pages (pages 2 ^M). Here, for convenience of explanation, it is assumed that a plurality of memory blocks each include 2 ^M pages, but a plurality of memories may include M pages each. Each of the pages includes a plurality of memory cells to which a plurality of word lines (WL) are connected.

In addition, the memory device 150 may include a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, Multi Level Cell) memory block or the like. Here, the SLC memory block includes a plurality of pages implemented by memory cells storing one bit of data in one memory cell, and has high data operation performance and high durability. And, the MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (e.g., two or more bits) in one memory cell, and has a larger data storage space than the SLC memory block In other words, it can be highly integrated. Here, an MLC memory block including a plurality of pages implemented by memory cells capable of storing 3-bit data in one memory cell may be divided into a triple level cell (TLC) memory block.

Each of the blocks 210, 220, 230, and 240 stores data provided from the host device through a write operation, and provides the stored data to the host 102 through a read operation.

3, memory block 330 of memory device 300 in memory system 110 includes a plurality of cell strings 340 each coupled to bit lines BL0 to BLm-1 . The cell string 340 of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each memory cell MC0 to MCn-1 may be configured as a multi-level cell (MLC) storing a plurality of bits of data information per cell. Cell strings 340 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

Here, FIG. 3 illustrates a memory block 330 composed of NAND flash memory cells. However, the memory block 330 of the memory device 300 according to the embodiment of the present invention is not limited to the NAND flash memory A NOR-type flash memory, a hybrid flash memory in which two or more types of memory cells are mixed, and a One-NAND flash memory in which a controller is embedded in a memory chip. The operation characteristics of the semiconductor device can be applied not only to a flash memory device in which the charge storage layer is made of a conductive floating gate but also to a charge trap flash (CTF) in which the charge storage layer is made of an insulating film.

The voltage supply unit 310 of the memory device 300 may supply the word line voltages (e.g., program voltage, read voltage, pass voltage, etc.) to be supplied to the respective word lines in accordance with the operation mode, (For example, a well region) in which the voltage supply circuit 310 is formed, and the voltage generation operation of the voltage supply circuit 310 may be performed under the control of a control circuit (not shown). In addition, the voltage supplier 310 may generate a plurality of variable lead voltages to generate a plurality of lead data, and may supply one of the memory blocks (or sectors) of the memory cell array in response to the control of the control circuit Select one of the word lines of the selected memory block, and provide the word line voltage to the selected word line and unselected word lines, respectively.

In addition, the read / write circuit 320 of the memory device 300 is controlled by a control circuit and operates as a sense amplifier or as a write driver depending on the mode of operation . For example, in the case of a verify / normal read operation, the read / write circuit 320 may operate as a sense amplifier for reading data from the memory cell array. In addition, in the case of a program operation, the read / write circuit 320 can operate as a write driver that drives bit lines according to data to be stored in the memory cell array. The read / write circuit 320 may receive data to be written into the cell array from a buffer (not shown) during a program operation, and may drive the bit lines according to the input data. To this end, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324 and 326, respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs) And each page buffer 322, 324, 326 may include a plurality of latches (not shown). Hereinafter, the memory device in the case where the memory device is implemented as a three-dimensional nonvolatile memory device in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIGS. 4 to 11. FIG.

Referring to FIG. 4, the memory device 150 may include a plurality of memory blocks BLK 1 to BLKh, as described above. Here, FIG. 4 is a block diagram showing a memory block of the memory device shown in FIG. 3, wherein each memory block BLK can be implemented in a three-dimensional structure (or vertical structure). For example, each memory block BLK may include structures extending along the first to third directions, e.g., the x-axis direction, the y-axis direction, and the z-axis direction.

Each memory block BLK may include a plurality of NAND strings NS extending along a second direction. A plurality of NAND strings NS may be provided along the first direction and the third direction. Each NAND string NS includes a bit line BL, at least one string select line SSL, at least one ground select line GSL, a plurality of word lines WL, at least one dummy word line DWL ), And a common source line (CSL). That is, each memory block includes a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, a plurality of dummy word lines (DWL), and a plurality of common source lines (CSL).

5 and 6, an arbitrary memory block BLKi in the plurality of memory blocks of the memory device 150 may include structures extending along the first direction to the third direction. Here, FIG. 5 is a view schematically showing the structure when the memory device according to the embodiment of the present invention is implemented as a three-dimensional nonvolatile memory device of a first structure, and FIG. 6 is a cross-sectional view of the memory block BLKi of FIG. 5 along an arbitrary first line I-I '. FIG. 6 is a perspective view showing an arbitrary memory block BLKi implemented by the structure of FIG.

First, a substrate 5111 can be provided. For example, the substrate 5111 may comprise a silicon material doped with a first type impurity. For example, the substrate 5111 may comprise a silicon material doped with a p-type impurity, or may be a p-type well (e.g., a pocket p-well) Lt; / RTI > wells. Hereinafter, for convenience of explanation, it is assumed that the substrate 5111 is p-type silicon, but the substrate 5111 is not limited to p-type silicon.

Then, on the substrate 5111, a plurality of doped regions 5311, 5312, 5313, 5314 extended along the first direction may be provided. For example, the plurality of doped regions 5311, 5312, 5313, 5314 may have a second type different from the substrate 1111. For example, a plurality of doped regions 5311, 5312, 5313, The first to fourth doped regions 5311, 5312, 5313, and 5314 are assumed to be of n-type, but for the sake of convenience of explanation, The doping region to the fourth doping regions 5311, 5312, 5313, 5314 are not limited to being n-type.

In a region on the substrate 5111 corresponding to between the first doped region and the second doped regions 5311 and 5312, a plurality of insulating materials 5112 extending along the first direction are sequentially formed along the second direction Can be provided. For example, the plurality of insulating materials 5112 and the substrate 5111 may be provided at a predetermined distance along the second direction. For example, the plurality of insulating materials 5112 may be provided at a predetermined distance along the second direction, respectively. For example, the insulating materials 5112 may comprise an insulating material such as silicon oxide.

Are sequentially disposed along the first direction in the region on the substrate 5111 corresponding to the first doped region and the second doped regions 5311 and 5312, A plurality of pillars 5113 can be provided. For example, each of the plurality of pillars 5113 may be connected to the substrate 5111 through the insulating materials 5112. For example, each pillar 5113 may be composed of a plurality of materials. For example, the surface layer 1114 of each pillar 1113 may comprise a silicon material doped with a first type. For example, the surface layer 5114 of each pillar 5113 may comprise a doped silicon material of the same type as the substrate 5111. Hereinafter, for convenience of explanation, it is assumed that the surface layer 5114 of each pillar 5113 includes p-type silicon, but the surface layer 5114 of each pillar 5113 is limited to include p-type silicon It does not.

The inner layer 5115 of each pillar 5113 may be composed of an insulating material. For example, the inner layer 5115 of each pillar 5113 may be filled with an insulating material such as silicon oxide.

The insulating film 5116 is provided along the exposed surfaces of the insulating materials 5112, the pillars 5113 and the substrate 5111 in the region between the first doped region and the second doped regions 5311 and 5312 . For example, the thickness of the insulating film 5116 may be smaller than 1/2 of the distance between the insulating materials 5112. That is, between the insulating film 5116 provided on the lower surface of the first insulating material of the insulating materials 5112 and the insulating film 5116 provided on the upper surface of the second insulating material below the first insulating material, An area where a material other than the insulating film 5112 and the insulating film 5116 can be disposed.

In the region between the first doped region and the second doped regions 5311 and 5312, conductive materials 5211, 5221, 5231, 5241, 5251, 5261, 5271, 5281, 5291 may be provided. For example, a conductive material 5211 extending along the first direction between the insulating material 5112 adjacent to the substrate 5111 and the substrate 5111 may be provided. In particular, a conductive material 5211 extending in the first direction may be provided between the insulating film 5116 on the lower surface of the insulating material 5112 adjacent to the substrate 5111 and the substrate 5111.

A conductive material extending along the first direction is provided between the insulating film 5116 on the upper surface of the specific insulating material and the insulating film 5116 on the lower surface of the insulating material disposed on the specific insulating material above the insulating material 5112 . For example, between the insulating materials 5112, a plurality of conductive materials 5221, 5231, 5214, 5251, 5261, 5271, 5281 extending in the first direction may be provided. In addition, a conductive material 5291 extending along the first direction may be provided in the region on the insulating materials 5112. [ For example, the conductive materials 5211, 5221, 5231, 5214, 5251, 5261, 5271, 5281, 5291 extended in the first direction may be metallic materials. For example, the conductive materials 5211, 5221, 5231, 5241, 5251, 5261, 5271, 5281, 5291 extended in the first direction may be a conductive material such as polysilicon.

In the region between the second doped region and the third doped regions 5312 and 5313, the same structure as the structure on the first doped region and the second doped regions 5311 and 5312 may be provided. For example, in the region between the second doped region and the third doped regions 5312 and 5313, a plurality of insulating materials 5112 extending in the first direction, sequentially arranged along the first direction, A plurality of pillars 5113 passing through the plurality of insulating materials 5112, an insulating film 5116 provided on the exposed surfaces of the plurality of insulating materials 5112 and the plurality of pillars 5113, A plurality of conductive materials 5212, 5222, 5232, 5224, 5225, 5262, 5272, 5282, 5292 extending along the first direction may be provided.

In the region between the third doped region and the fourth doped regions 5313 and 5314, the same structure as the structure on the first doped region and the second doped regions 5311 and 5312 may be provided. For example, in a region between the third doped region and the fourth doped regions 5312 and 5313, a plurality of insulating materials 5112 extending in the first direction are sequentially arranged along the first direction, A plurality of pillars 5113 passing through the plurality of insulating materials 5112, an insulating film 5116 provided on the exposed surfaces of the plurality of insulating materials 5112 and the plurality of pillars 5113, A plurality of conductive materials 5213, 5223, 5234, 5253, 5263, 5273, 5283, 5293 extending along one direction may be provided.

Drains 5320 may be provided on the plurality of pillars 5113, respectively. For example, the drains 5320 may be silicon materials doped with a second type. For example, the drains 5320 may be n-type doped silicon materials. Hereinafter, for ease of explanation, it is assumed that the drains 5320 include n-type silicon, but the drains 5320 are not limited to include n-type silicon. For example, the width of each drain 5320 may be greater than the width of the corresponding pillar 5113. For example, each drain 5320 may be provided in the form of a pad on the upper surface of the corresponding pillar 5113.

On the drains 5320, conductive materials 5331, 5332, 5333 extended in the third direction may be provided. The conductive materials 5331, 5332, and 5333 may be sequentially disposed along the first direction. Each of the conductive materials 5331, 5332, and 5333 may be connected to the drains 5320 of the corresponding region. For example, the drains 5320 and the conductive material 5333 extended in the third direction may be connected through contact plugs, respectively. For example, the conductive materials 5331, 5332, 5333 extended in the third direction may be metallic materials. For example, the conductive materials 5331, 5332, 53333 extended in the third direction may be a conductive material such as polysilicon.

5 and 6, each of the pillars 5113 includes a plurality of conductor lines 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending along a first region and an adjacent region of the insulating film 5116, And a string can be formed together with the film. For example, each of the pillars 5113 is connected to the adjacent region of the insulating film 5116 and the adjacent region of the plurality of conductor lines 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending along the first direction, A string NS can be formed. The NAND string NS may comprise a plurality of transistor structures TS.

7, the insulating film 5116 in the transistor structure TS shown in FIG. 6 may include a first sub-insulating film to a third sub-insulating film 5117, 5118, and 5119. Here, FIG. 7 is a cross-sectional view showing the transistor structure TS of FIG.

The p-type silicon 5114 of the pillar 5113 can operate as a body. The first sub-insulating film 5117 adjacent to the pillar 5113 may function as a tunneling insulating film and may include a thermal oxide film.

The second sub-insulating film 5118 can operate as a charge storage film. For example, the second sub-insulating film 5118 can function as a charge trapping layer and can include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like).

The third sub-insulating film 5119 adjacent to the conductive material 5233 can operate as a blocking insulating film. For example, the third sub-insulating film 5119 adjacent to the conductive material 5233 extended in the first direction may be formed as a single layer or a multilayer. The third sub-insulating film 5119 may be a high-k dielectric film having a higher dielectric constant than the first sub-insulating film 5117 and the second sub-insulating films 5118 (e.g., aluminum oxide film, hafnium oxide film, etc.).

Conductive material 5233 may operate as a gate (or control gate). That is, the gate (or control gate 5233), the blocking insulating film 5119, the charge storage film 5118, the tunneling insulating film 5117, and the body 5114 can form a transistor (or a memory cell transistor structure) have. For example, the first sub-insulating film to the third sub-insulating films 5117, 5118, and 5119 may constitute an ONO (oxide-nitride-oxide). Hereinafter, for convenience of explanation, the p-type silicon 5114 of the pillar 5113 is referred to as a body in the second direction.

The memory block BLKi may include a plurality of pillars 5113. That is, the memory block BLKi may include a plurality of NAND strings NS. More specifically, the memory block BLKi may include a plurality of NAND strings NS extending in a second direction (or a direction perpendicular to the substrate).

Each NAND string NS may include a plurality of transistor structures TS disposed along a second direction. At least one of the plurality of transistor structures TS of each NAND string NS may operate as a string selection transistor (SST). At least one of the plurality of transistor structures TS of each NAND string NS may operate as a ground selection transistor (GST).

The gates (or control gates) may correspond to the conductive materials 5211 to 5291, 5212 to 5292, and 5213 to 5293 extended in the first direction. That is, the gates (or control gates) extend in a first direction to form word lines and at least two select lines (e.g., at least one string select line SSL and at least one ground select line GSL).

The conductive materials 5331, 5332, 5333 extended in the third direction may be connected to one end of the NAND strings NS. For example, the conductive materials 5331, 5332, 5333 extended in the third direction may operate as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings NS may be connected to one bit line BL.

Second type doped regions 5311, 5312, 5313, 5314 extended in the first direction may be provided at the other end of the NAND strings NS. The second type doped regions 5311, 5312, 5313, 5314 extended in the first direction may operate as common source lines CSL.

That is, the memory block BLKi includes a plurality of NAND strings NS extending in a direction perpendicular to the substrate 5111 (second direction), and a plurality of NAND strings NAND flash memory block (e.g., charge trapping type) to which the NAND flash memory is connected.

5 to 7, conductor lines 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending in the first direction are described as being provided in nine layers, conductor lines extending in the first direction (5211 to 5291, 5212 to 5292, and 5213 to 5293) are provided in nine layers. For example, conductor lines extending in a first direction may be provided in eight layers, sixteen layers, or a plurality of layers. That is, in one NAND string NS, the number of transistors may be eight, sixteen, or plural.

5 to 7, three NAND strings NS are connected to one bit line BL. However, three NAND strings NS may be connected to one bit line BL, . For example, in the memory block BLKi, m NAND strings NS may be connected to one bit line BL. At this time, the number of conductive materials (5211 to 5291, 5212 to 5292, and 5213 to 5293) extending in the first direction by the number of NAND strings (NS) connected to one bit line (BL) The number of lines 5311, 5312, 5313, 5314 can also be adjusted.

5 to 7, three NAND strings NS are connected to one conductive material extending in the first direction. However, in the case where one conductive material extended in the first direction has three NAND strings NS are connected to each other. For example, n conductive n-strings NS may be connected to one conductive material extending in a first direction. At this time, the number of bit lines 5331, 5332, 5333 can be adjusted by the number of NAND strings NS connected to one conductive material extending in the first direction.

8, in any block BLKi implemented with the first structure in the plurality of blocks of the memory device 150, NAND strings (not shown) are connected between the first bit line BL1 and the common source line CSL, (NS11 to NS31) may be provided. Here, FIG. 8 is a circuit diagram showing an equivalent circuit of the memory block BLKi implemented by the first structure described in FIGS. 5 to 7. FIG. The first bit line BL1 may correspond to the conductive material 5331 extended in the third direction. NAND strings NS12, NS22, NS32 may be provided between the second bit line BL2 and the common source line CSL. And the second bit line BL2 may correspond to the conductive material 5332 extending in the third direction. Between the third bit line BL3 and the common source line CSL, NAND strings NS13, NS23, and NS33 may be provided. And the third bit line BL3 may correspond to the conductive material 5333 extending in the third direction.

The string selection transistor SST of each NAND string NS may be connected to the corresponding bit line BL. The ground selection transistor GST of each NAND string NS can be connected to the common source line CSL. Memory cells MC may be provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS.

Hereinafter, for convenience of explanation, NAND strings NS may be defined in units of a row and a column, and NAND strings NS connected in common to one bit line may be defined as one column As will be described below. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 may correspond to the first column, and the NAND strings NS12 to NS32 connected to the second bit line BL2 may correspond to the second column And the NAND strings NS13 to NS33 connected to the third bit line BL3 may correspond to the third column. The NAND strings NS connected to one string select line (SSL) can form one row. For example, the NAND strings NS11 through NS13 connected to the first string selection line SSL1 may form a first row, the NAND strings NS21 through NS23 connected to the second string selection line SSL2, And the NAND strings NS31 to NS33 connected to the third string selection line SSL3 may form the third row.

Further, in each NAND string NS, a height can be defined. For example, in each NAND string NS, the height of the memory cell MC1 adjacent to the ground selection transistor GST is one. In each NAND string NS, the height of the memory cell may increase as the string selection transistor SST is adjacent to the string selection transistor SST. In each NAND string NS, the height of the memory cell MC7 adjacent to the string selection transistor SST is seven.

Then, the string selection transistors SST of the NAND strings NS in the same row can share the string selection line SSL. The string selection transistors SST of the NAND strings NS of the different rows can be connected to the different string selection lines SSL1, SSL2 and SSL3, respectively.

In addition, memory cells at the same height of the NAND strings NS in the same row can share the word line WL. That is, at the same height, the word lines WL connected to the memory cells MC of the NAND strings NS of different rows can be connected in common. The dummy memory cells DMC of the same height of the NAND strings NS in the same row can share the dummy word line DWL. That is, at the same height, the dummy word lines DWL connected to the dummy memory cells DMC of the NAND strings NS of the different rows can be connected in common.

For example, the word lines WL or the dummy word lines DWL may be connected in common in the layer provided with the conductive materials 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending in the first direction . For example, the conductive materials 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending in the first direction may be connected to the upper layer through a contact. The conductive materials 5211 to 5291, 5212 to 5292, and 5213 to 5293 extending in the first direction in the upper layer may be connected in common. That is, the ground selection transistors GST of the NAND strings NS in the same row can share the ground selection line GSL. And, the ground selection transistors GST of the NAND strings NS of the different rows can share the ground selection line GSL. In other words, the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 can be commonly connected to the ground selection line GSL.

The common source line CSL may be connected in common to the NAND strings NS. For example, in the active region on the substrate 5111, the first to fourth doped regions 5311, 5312, 5313, 5314 may be connected. For example, the first to fourth doped regions 5311, 5312, 5313, and 5314 may be connected to the upper layer through a contact, and the first doped region to the fourth doped region 5311 , 5312, 5313 and 5314 can be connected in common.

That is, as shown in FIG. 8, the word lines WL of the same depth can be connected in common. Thus, when a particular word line WL is selected, all NAND strings NS connected to a particular word line WL can be selected. NAND strings NS in different rows may be connected to different string select lines SSL. Thus, by selecting the string selection lines SSL1 to SSL3, the NAND strings NS of unselected rows among the NAND strings NS connected to the same word line WL are selected from the bit lines BL1 to BL3 Can be separated. That is, by selecting the string selection lines SSL1 to SSL3, a row of NAND strings NS can be selected. Then, by selecting the bit lines BL1 to BL3, the NAND strings NS of the selected row can be selected in units of columns.

In each NAND string NS, a dummy memory cell DMC may be provided. The first to third memory cells MC1 to MC3 may be provided between the dummy memory cell DMC and the ground selection line GST.

The fourth to sixth memory cells MC4 to MC6 may be provided between the dummy memory cell DMC and the string selection line SST. Here, the memory cells MC of each NAND string NS can be divided into memory cell groups by the dummy memory cells DMC, and the memory cells MC of the divided memory cell groups adjacent to the ground selection transistor GST (For example, MC1 to MC3) may be referred to as a lower memory cell group, and memory cells (for example, MC4 to MC6) adjacent to the string selection transistor SST among the divided memory cell groups may be referred to as an upper memory cell Group. Hereinafter, with reference to FIGS. 9 to 11, the memory device according to the embodiment of the present invention will be described in more detail when the memory device is implemented as a three-dimensional nonvolatile memory device having a structure different from that of the first structure do.

9 and 10, an arbitrary memory block BLKj implemented in the second structure in the plurality of memory blocks of the memory device 150 includes structures extended along the first direction to the third direction can do. 9 schematically shows a structure in which the memory device according to the embodiment of the present invention is implemented as a three-dimensional nonvolatile memory device of a second structure different from the first structure described in FIGS. 5 to 8 9 is a perspective view showing an arbitrary memory block BLKj implemented by a second structure in the plurality of memory blocks of FIG. 4, FIG. 10 is a perspective view of a memory block BLKj of FIG. - VII ').

First, a substrate 6311 may be provided. For example, the substrate 6311 may comprise a silicon material doped with a first type impurity. For example, the substrate 6311 may comprise a silicon material doped with a p-type impurity, or may be a p-type well (e. G., A pocket p-well) Lt; / RTI > wells. Hereinafter, for convenience of explanation, the substrate 6311 is assumed to be p-type silicon, but the substrate 6311 is not limited to p-type silicon.

Then, on the substrate 6311, first to fourth conductive materials 6321, 6322, 6323, and 6324 extending in the x-axis direction and the y-axis direction are provided. Here, the first to fourth conductive materials 6321, 6322, 6323, and 6324 are provided at a specific distance along the z-axis direction.

Further, fifth to eighth conductive materials 6325, 6326, 6327, and 6328 extending in the x-axis direction and the y-axis are provided on the substrate 6311. Here, the fifth to eighth conductive materials 6325, 6326, 6327, and 6328 are provided at a specific distance along the z-axis direction. The fifth to eighth conductive materials 6325, 6326, 6327, and 6328 are spaced apart from the first to fourth conductive materials 6321, 6322, 6323, and 6324 along the y- / RTI >

In addition, a plurality of lower pillars penetrating the first to fourth conductive materials 6321, 6322, 6323, and 6324 are provided. Each lower pillar DP extends along the z-axis direction. Also, a plurality of upper pillars are provided that pass through the fifth to eighth conductive materials 6325, 6326, 6327, and 6328. Each upper pillar UP extends along the z-axis direction.

Each of the lower pillars DP and upper pillars UP includes an inner material 6361, an intermediate layer 6362, and a surface layer 6363. Here, as described in FIGS. 5 and 6, the intermediate layer 6362 will operate as a channel of the cell transistor. The surface layer 6363 will include a blocking insulating film, a charge storage film, and a tunneling insulating film.

The lower pillar DP and the upper pillar UP are connected via a pipe gate PG. The pipe gate PG may be disposed within the substrate 6311, and in one example, the pipe gate PG may include the same materials as the lower pillars DP and upper pillars UP.

On top of the lower pillar DP is provided a second type of doping material 6312 extending in the x-axis and y-axis directions. For example, the second type of doping material 6312 may comprise an n-type silicon material. The second type of doping material 6312 operates as a common source line CSL.

A drain 6340 is provided on the upper portion of the upper pillar UP. For example, the drain 6340 may comprise an n-type silicon material. A first upper conductive material and second upper conductive materials 6351 and 6352 are provided on the upper portions of the drains in the y-axis direction.

The first upper conductive material and the second upper conductive materials 6351, 6352 are provided spaced along the x-axis direction. For example, the first and second top conductive materials 6351, 6352 can be formed as a metal, and in one embodiment, the first and second top conductive materials 6351, And may be connected through contact plugs. The first upper conductive material and the second upper conductive materials 6351 and 6352 operate as the first bit line and the second bit line BL1 and BL2, respectively.

The first conductive material 6321 operates as a source select line SSL and the second conductive material 6322 operates as a first dummy word line DWL1 and the third and fourth conductive materials 6323 And 6324 operate as the first main word line and the second main word lines MWL1 and MWL2, respectively. The fifth conductive material and the sixth conductive materials 6325 and 6326 operate as the third main word line and the fourth main word lines MWL3 and MWL4 respectively and the seventh conductive material 6327 acts as the second Dummy word line DWL2, and the eighth conductive material 6328 operates as a drain select line (DSL).

And the first to fourth conductive materials 6321, 6322, 6323, and 6324 adjacent to the lower pillar DP and the lower pillar DP constitute a lower string. The upper pillar UP and the fifth to eighth conductive materials 6325, 6326, 6327 and 6328 adjacent to the upper pillar UP constitute an upper string. The lower string and upper string are connected via a pipe gate (PG). One end of the lower string is coupled to a second type of doping material 6312 that operates as a common source line (CSL). One end of the upper string is connected to the corresponding bit line via a drain 6320. [ One lower string and one upper string will constitute one cell string connected between the second type of doping material 6312 and the bit line.

That is, the lower string will include a source select transistor (SST), a first dummy memory cell (DMC1), and a first main memory cell and a second main memory cell (MMC1, MMC2). The upper string will include a third main memory cell and fourth main memory cells MMC3 and MMC4, a second dummy memory cell DMC2, and a drain select transistor DST.

9 and 10, the upper stream and the lower string may form a NAND string NS, and the NAND string NS may include a plurality of transistor structures TS. Here, the transistor structure included in the NAND stream in FIGS. 9 and 10 has been described in detail with reference to FIG. 7, and a detailed description thereof will be omitted here.

11, in an arbitrary block BLKj implemented in the second structure in the plurality of blocks of the memory device 150, one block and one block BLKj, as described in FIGS. 9 and 10, One cell string implemented by connecting the lower string through the pipe gate PG may be provided as a plurality of pairs each. Here, FIG. 11 is a circuit diagram showing an equivalent circuit of a memory block BLKj implemented with the second structure described in FIGS. 9 and 10, and for convenience of explanation, any block BLKj implemented in the second structure is shown. Only a first string and a second string constituting a pair are shown.

That is, in any block BLKj implemented with the second structure, the memory cells stacked along the first channel CH1, e.g., at least one source select gate and at least one drain select gate, And the memory cells stacked along the second channel CH2, such as at least one source select gate and at least one drain select gate, implement the second string ST2.

The first string ST1 and the second string ST2 are connected to the same drain select line DSL and the same source select line SSL and the first string ST1 is connected to the first bit line BL1 and the second string ST2 is connected to the second bit line BL2.

11, the case where the first string ST1 and the second string ST2 are connected to the same drain selection line DSL and the same source selection line SSL has been described as an example, , The first string ST1 and the second string ST2 are connected to the same source select line SSL and the same bit line BL so that the first string ST1 is connected to the first drain select line DSL1 And the second string ST2 is connected to the second drain select line DSL2 or the first string ST1 and the second string ST2 are connected to the same drain select line DSL and the same bit line BL The first string ST1 may be connected to the first source selection line SSL1 and the second string ST2 may be connected to the second source selection line SDSL2. Hereinafter, the data processing to the memory device in the memory system according to the embodiment of the present invention will be described in detail with reference to FIGS. 12 and 13, particularly the data processing operation when programming and erasing data to the memory device Will be described more specifically.

12 schematically illustrates an example of a data processing operation in a memory device in a memory system according to an embodiment of the present invention. Hereinafter, for convenience of explanation, data corresponding to a program command is stored in a memory (not shown) of the controller 130 in accordance with a program command and an erase command received from the host 102 in the memory system 110 shown in Fig. Cache in the buffer / cache included in the memory 144, then programs the data stored in the buffer / cache in the corresponding memory blocks of the memory device 150, Data processing in the case of performing an erase operation on blocks will be described as an example.

Here, the memory blocks of the memory device 150 each have an erase cycle (EC), which is each limited, so that the memory blocks of the memory device 150 are controlled according to the erase command The erase operation can be performed. If the erase operation is performed in a specific memory block exceeding the limited EC, the specific memory block can be processed as a bad block which can no longer be used. That is, the limited EC represents the maximum cycle that can be erased for the memory blocks of the memory device 150, and in an embodiment of the present invention, the memory blocks of the memory device 150 are evenly erased within the limited EC For example, a Wear Leveling (WL) operation, in order to perform the operation of the memory device 150. Hereinafter, the ECs of the memory blocks of the memory device 150 The wear leveling operation according to the present invention will be described more concretely.

For convenience of explanation, the command data corresponding to the command received from the host 102 in the memory system 110 shown in Fig. 1, for example, the command corresponding to the write command received from the host 102 Write data to the plurality of memory blocks included in the memory device 150, that is, programs the data stored in the buffer / cache, to the plurality of memory blocks included in the memory device 150 Also includes a plurality of memory devices 150 in which data is programmed for memory blocks of the memory device 150 in which the data is stored, A description will be given of an operation of processing between memory blocks of FIG.

Here, in the embodiment of the present invention, the memory blocks of the memory device 150 are programmed and stored with write data corresponding to the write command received from the host 102, as described above, Each include a plurality of pages, and write data is programmed and stored in the pages of the memory block. At this time, when a write command is received from the host 102 for the pages of the memory block in which the write data has been programmed, a write command corresponding to the write command is written to other pages of the memory block, Data is programmed. Here, when a write command for write data stored in pages of previous memory blocks is received and the write data is programmed into pages of another memory block, the write data stored in the pages of the previous memory blocks are invalid data , And the pages of the previous memory blocks become an invalid page. In A, if the program update to the memory blocks of the memory device 150 in which the data is programmed occurs, or if invalid pages are included in the memory blocks in accordance with the program update, the utilization efficiency of the memory device 150 is further maximized The operation of processing between memory blocks of the memory device 150 will be described in more detail as an example.

In the following description, the controller 130 performs the data processing operation in the memory system for convenience of explanation. However, as described above, the processor 134 included in the controller 130, Through the FTL, for example, data processing and processing between memory blocks of the memory device 150 may be performed. In the embodiment of the present invention to be described later, the controller 130 stores the write data corresponding to the write command received from the host 102 in the buffer included in the memory 144 of the controller 130, In other words, the data stored in the buffer is programmed into an arbitrary memory block in a plurality of memory blocks included in the memory device 150, Memory blocks of the memory device 150 by performing an erase operation on the memory blocks of the memory device 150, taking into account the ECs for the memory blocks, for example, the memory blocks, For example, swapping between memory blocks to perform wear leveling, in other words, according to the EC of the memory blocks, Leveling operation will be described as an example.

Here, in the embodiment of the present invention, in consideration of the erase parameter updated in accordance with the parameter for the memory blocks, for example, the erase operation of the memory blocks in accordance with the erase command, that is, EC, A program / erase cycle or an erase / write (E / W) cycle for the memory blocks is described as an example. However, The present invention can also be applied to a case where a wear leveling operation is performed on memory blocks in consideration of a cycle.

In particular, in an embodiment of the present invention, the memory blocks of the memory device 150 may be accessed via a parameter list of the memory blocks included in the memory device 150, i. E. The data processing in the case of performing the wear leveling for the memory blocks in consideration of the EC will be described in more detail. That is, in the embodiment of the present invention to be described later, in consideration of EC for the memory blocks included in the memory device 150, a source memory block and a target memory block are selected in the memory blocks, Wear leveling is performed by swapping between the source memory block and the target memory block.

In the following description, the controller 130 performs the data processing operation in the memory system for convenience of explanation. However, as described above, the processor 134 included in the controller 130, After verifying program updates to memory blocks of memory device 150, e.g., via FTL, through data processing, i.e., through FTL, to account for program updates in memory blocks of memory device 150, (E.g., swapping between memory blocks to perform wear leveling, i. E., Program updating of memory blocks) to memory blocks of memory device 150 The case where leveling is performed will be described as an example.

In other words, in the embodiment of the present invention, the controller 130 stores the write data corresponding to the write command received from the host 102 in the buffer included in the memory 144 of the controller 130, For example, a program operation to a plurality of pages of an arbitrary memory block in a plurality of memory blocks included in the memory device 150 and stores the data in the first page of the first memory block. When the controller 130 receives a write command for the pages of the first memory block from the host 102, the controller 130 performs a program, i.e., a program update, on the pages of the first memory block in which data is stored, At this time, the memory blocks of the memory device 150 are processed, for example, by swapping between the memory blocks in consideration of the parameters for the memory blocks, for example, program update parameters for the memory blocks. , That is, a case where the memory blocks of the memory device 150 are subjected to wear leveling according to program update parameters of the memory blocks will be described as an example.

Here, in the embodiment of the present invention, a software leveling operation is performed on memory blocks in consideration of a program update parameter updated by performing a program operation of memory blocks in accordance with a parameter, for example, a write command received from the host 102 The update parameter for the memory blocks of the memory device 150 that performs the update of the command operation with the controller 130 in accordance with the command operation corresponding to the command received from the host 102 will be described as an example, The present invention can be applied to a case where a wear leveling operation is performed on memory blocks.

That is, in the embodiment of the present invention, the controller 130 performs a read operation or a program operation corresponding to the read command or the write command received from the host 102 in the memory blocks of the memory device 150, A read command or a write command for any memory blocks that have performed a read operation or a program operation from the host 102 and performs a read operation or a program operation for arbitrary memory blocks Leveling of the memory blocks of the memory device 150 is performed in consideration of the read update parameter or the program update parameter as the update parameter when performing the read update operation or the program update operation. Here, the controller 130 sets a parameter, for example, a read update parameter or a program update parameter, for the memory blocks of the memory device 150, in accordance with a read operation or a program operation for the memory blocks of the memory device 150 , And updates it. Controller 130 may be operable to provide map data according to a read operation or a program operation to memory blocks of memory device 150, that is, logical / physical (L2P) : Physical to Logical) update the read update parameter or the program update parameter for the memory blocks of the memory device 150 at the time of updating the map data.

In particular, in the embodiment of the present invention to be described later, the update parameter for the memory blocks of the memory device 150 that performs the command operation corresponding to the command received from the host 102, that is, the read update parameter or the program update parameter After confirming the read update parameter or the program update parameter for the memory blocks of the memory device 150 through a list in which the memory block 150 is written, for example, an update list, The source memory block and the target memory block are selected, and then the source memory block and the target memory block are swapped to perform the wear leveling. 12, a command operation corresponding to the command received from the host 102, for example, an erase operation corresponding to the erase command, and a read operation or a program operation corresponding to the read command or the write command, After performing for the memory blocks of memory device 150, a parameter for the memory blocks of memory device 150, e.g., EC of memory blocks corresponding to the erase operation, and a memory corresponding to the read or program operation The operation of performing the wear leveling by swapping among the memory blocks of the memory device 150 considering the update parameters of the blocks will be described in more detail.

12, the controller 130 stores the write data corresponding to the write command received from the host 102 in the buffer included in the memory 144 of the controller 130, The stored write data is stored in a plurality of memory blocks included in the memory device 150 such as block 0 (Block 0) 1250, block 1 1255, block 2 1260, block 3 A block 61212, a block 41270, a block 51275, a block 61280, and a block 7125, And stores it.

The controller 130 also supplies the read data corresponding to the read command received from the host 102 to a plurality of memory blocks included in the memory device 150 such as block 0 (Block 0) 1250, block 1 (Block 1) 1255, Block 2 1260, Block 3 1265, Block 4 1270, Block 5 1275, Block 6 1280 And the read data stored in the buffer is supplied to the host 102 after reading from the corresponding arbitrary block in the block 7 (Block 7) 1285 and storing it in the buffer included in the memory 144 of the controller 130 do.

Herein, a plurality of memory blocks included in the memory device 150, such as block 0 1250, block 1 1255, block 2 1260, block 3 1265, block 4 1270, block 5 The controller 130 in the embodiment of the present invention includes a plurality of pages as described above at block 1280 and blocks 1280 and 7125, In other words, data corresponding to the command operation may be stored in the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, Such as a program operation or a read operation, corresponding to the command operation when reading from the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, After confirming the program update parameter or the read update parameter corresponding to the operation, Record the meter in the first list, for example, update list 1214.

In particular, the controller 130 is configured to store memory blocks 1212, 1255, 1260, 1265, 1270, 1275, 1280, 1250, 1255, 1260, 1265, 1270, 1275, 1280, 1285) in the update list 1214, stores them in the memory 144 of the controller 130, The updated parameters are updated in response to command operations, such as read operations or program operations, for the memory blocks 1250,1255, 1260,1265, 1270,1275, 1280,1285. The controller 130 determines whether or not the memory blocks 1250, 1255, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250 1280, 1285, 1270, 1275, 1280, and 1285) recorded in the update list 1214. The memory blocks 1250, 1255, 1260, The source memory block and the target memory block are selected in the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 in consideration of the star update parameter, and then the source memory block and the target memory block are swapped .

The controller 130 then writes the write data corresponding to the write command received from the host 102 to the memory blocks of the memory device 150 such as block 0 (1250), block 1 (1255), block 2 1260, block 3 1265, block 4 1270, block 5 1275, block 6 1280 and block 7 1285 after storing the erase command received from the host 102 And performs erase operation on an arbitrary memory block in a plurality of memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the memory device 150, In the erase list 1216, that is, the EC for an arbitrary memory block in which the erase operation has been performed is written to the erase list 1216. [

In particular, the controller 130 may store the memory blocks 1250, 1255, 1260, 1250, 1250, EC 1212, 1260, 1265, 1270, 1275, 1280, and 1285 in the memory 144 of the controller 130, and stores the update parameters 1212 in the update list 1216, Is updated corresponding to the erase operation for the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285. The controller 130 then determines the memory blocks 1250, 1255, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250, 1250 1250, 1260, 1260, 1265, 1270, 1275, 1280, 1285) recorded in the erase list 1214. The memory blocks 1250, 1260, 1260, 1265, 1270, 1275, 1280, 1285 ), The source memory block and the target memory block are selected in the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285, and then the source memory block and the target memory block are swapped .

More specifically, the controller 130 includes a plurality of memory blocks included in the memory device 150, such as block 0 1250, block 1 1255, block 2 1260, block 3 1265, When receiving a command from the host 102 for a block 4 1270, a block 5 1275, a block 6 1280 and a block 7 1285, for example, when receiving a read command or a write command from the host 102 A command operation corresponding to the read command or the write command in the memory blocks 1502, 1255, 1260, 1265, 1270, 1260, 1280, and 1285 of the memory device 150, that is, And then performs a read operation or a program operation with respect to any of the memory blocks. In accordance with the read operation or the program operation, an update parameter, for example, a read update parameter or a program update The site parameters, is recorded in the update list 1214.

That is, the controller 130 determines whether or not the block 0 (1250), block 1 (1255), block 2 (1260), block 3 (1265), block 4 (Block 1250) corresponding to the execution of the read operation or the program operation after performing the read operation or the program operation for the block 1270, the block 5 1275, the block 6 1280, and the block 7 1285, A read update parameter or program for block 1 1255, block 2 1260, block 3 1265, block 4 1270, block 5 1275, block 6 1280, The update parameters are stored in block 0 (1250), block 1 1255, block 2 1260, block 3 1265, block 4 1270, block 5 1275, block 6 1280, And stores the update list 1214 in the buffer 1200 included in the memory 144 of the controller 130. The update list 1214 is stored in the buffer 1200 included in the memory 144 of the controller 130. [

For example, in the update list 1214, the update parameter is '180' for the index 1212 '0' of the block 0 1250, the update parameter is '1' for the index 1212 of the block 1 1255, Update parameter is '110' for the index 1212 '2' of the block 2 1260 ',' update parameter is '255' for the index 1212 '2' of the block 2 1260, The update parameter is '125' for the index 1212 '4' of the block 512 (1270), the update parameter is '22' for the index 1212 '5' The update parameter is '68' for '6', and the update parameter is '49' for the index 1212 '7' of block 7 (1285). Here, the controller 130 can manage and update the update parameters recorded in the update list 1214 according to MRU (Most Recently Used) / LRU (Least Recently Used).

The controller 130 also includes a plurality of memory blocks included in the memory device 150 such as block 0 1250, block 1 1255, block 2 1260, block 3 1265, block 4 The host device 102 receives the erase command from the host 102 and the memory device 150 receives the erase command from the host 102. When receiving the erase command from the host 102, The memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 of the memory block 1224, after confirming any memory blocks that perform the command operation corresponding to the erase command, And writes an erase parameter, for example EC, to any memory blocks in the erase list 1216, corresponding to this erase operation.

That is, in response to the erase command received from the host 102, the controller 130 sets the block 0 (block 1250), block 1 1255, block 2 1260, block 3 1265, block 4 1270 1250, and 1255 corresponding to the execution of the erase operation after performing the erase operation on the block 5125, 61280, and 7125, 1250, and Block 1 1250 for the block 2 1260, the block 3 1265, the block 4 1270, the block 5 1275, the block 6 1280, and the block 7 1285, By the index 1212 of the block 1255, the block 2 1260, the block 3 1265, the block 4 1270, the block 5 1275, the block 6 1280 and the block 7 1285, List 1216 and stores it in the buffer 1200 included in the memory 144 of the controller 1216 in the erase list 1216.

For example, EC is '260' for the index 1212 '0' of the block 0 1250 and EC is '450' for the index 1212 '1' of the block 1 1255 in the erase list 1216 EC is '95' for the index 1212 '2' of the block 2 (1260), 'EC' is '130' for the index 1212 '2' of the block 2 1260, EC is '100' for the index 1212 '5' of the block 12 (1275), 'EC' is '160' for the index 1212 '4' , And the update parameter is '85' for the index 1212 '7' of the block 7 (1285) and the EC is '20', respectively.

Controller 130 then determines whether block 0 1250, block 1 1255, block 2 1260, block 3 1265, block 4 1270, block 5 1275, Block 1250, block 1 1255, block 2 1260, block 3 1265, and block 4 1270 when performing wear leveling for block 6 1280 and block 7 1285, , The update parameter for each memory block in the update list 1214 stored in the buffer 1200, and the update parameter for each memory block in the update list 1214, for example, by checking parameters for the block 5125, block 61280, and block 7 1285, And wear leveling in consideration of the EC for each memory block in the erase list 1216 stored in the buffer 1200.

For example, the controller 130 checks the update parameter of the update list 1214 stored in the buffer 1200 to determine whether the memory blocks 1250, 1255, 1260 , 1265, 1270, 1275, 1280, 1285), source memory blocks are selected. In particular, the controller 130 may be configured to sort the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, 1285 included in the memory device 150 according to the update parameters of the update list 1214 The memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the aligned memory device 150 sequentially update the source memory blocks in accordance with the update parameters of the update list 1214. [ Select. Here, the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the aligned memory device 150 are provided with a frequency / number / aging / That is, sequentially arranged data according to the frequency or number of times of command operation or aging.

In one example, the controller 130 selects a memory block having the highest update parameter and a memory block having the lowest update parameter as the source memory blocks. In other words, the controller 130 sequentially checks the memory blocks having the highest update parameter from the hot memory blocks, identifies the memory block having the highest update parameter as the highest hot memory block, The memory block having the parameter is selected as the first source memory block. In addition, the controller 130 sequentially identifies the memory blocks having the lowest update parameter as cold memory blocks, identifies the memory block having the lowest update parameter as the highest-order cold memory block, Is selected as the second source memory block.

Here, the controller 130 identifies the block 2 (1260) having an update parameter of '255' in the update list 1214 stored in the buffer 1200 as the highest hot memory block, and updates the block 2 (1260) Select as source memory block. The controller 130 checks block 5 (1275) whose update parameter is '22' in the update list 1214 stored in the buffer 1200 as the highest-order cold memory block and sets block 5 (1275) Select as source memory block.

The controller 130 also checks the EC of the erase list 1216 stored in the buffer 1200 to determine whether the memory blocks 1250, 1255, 1260, 1265, 1270, 1280, 1285), the target memory blocks are selected. In particular, the controller 130 may be configured to align the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, 1285 included in the memory device 150 according to the EC of the erase list 1216 In the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the aligned memory device 150, the target memory blocks Select. Here, the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the aligned memory device 150 are provided with a frequency / number / aging / That is, sequentially arranged data according to the frequency or number of times of command operation or aging are respectively stored.

In one example, the controller 130 selects a memory block having the highest EC and a memory block having the lowest EC as target memory blocks. In other words, the controller 130 sequentially checks the memory blocks having the highest EC from the hot memory blocks, identifies the memory block having the highest update parameter as the highest hot memory block, Block is selected as the first target memory block. In addition, the controller 130 identifies the memory block having the lowest update parameter sequentially from the memory blocks having the lowest update parameter, identifies the memory block having the lowest update parameter as the highest-order cold memory block, Block is selected as the second target memory block.

Here, the controller 130 identifies block 1 1255 with EC '450' as the highest hot memory block in the erase list 1216 stored in the buffer 1200, and sets block 1 1255 as the first hot memory block Select it as the target memory block. The controller 130 identifies block 6 (1280) with EC '20' as the highest-order cold memory block in the erase list 1216 stored in the buffer 1200, and sets block 6 (1280) Select it as the target memory block.

The controller 130 then takes EC into account in the source memory blocks selected in consideration of the update parameter in the update list 1214 stored in the buffer 1200 and the erase list 1216 stored in the buffer 1200 And sweeps the selected target memory blocks to perform wear leveling on the memory blocks 1250, 1255, 1260, 1265, 1270, 1275, 1280, and 1285 included in the memory device 150.

More specifically, the controller 130 stores in the update list 1214 stored in the buffer 1200, a memory block having the highest update parameter in accordance with the update parameter, that is, a first source memory block, In the erase list 1216, a memory block having the lowest erase parameter according to EC is swapped between the second target memory blocks to perform the wear leveling. That is, in accordance with the highest update parameter, the controller 130 sets a first source memory block, for example, block 2 (1260) that is a hot memory block, and a second target memory block, e.g., block 6 (1280), and wear leveling is performed.

The controller 130 further includes a memory block having the lowest update parameter according to the update parameter in the update list 1214 stored in the buffer 1200, that is, a second source memory block, and an erase list 1216) performs a wear leveling by swapping a memory block having the most significant erase parameter according to EC, that is, between first target memory blocks. That is, the controller 130 sets the second source memory block, e.g., block 5 (1275), which is a cold memory block according to the lowest update parameter, and the first target memory block, e.g., block 1 (1255), and wear leveling is performed.

That is, in the embodiment of the present invention, parameters for memory blocks included in the memory device 150, e.g., parameters for memory blocks that perform command operations in accordance with commands received from the host 102, After determining the parameter or program update parameter and the erase parameter, the source memory blocks are sequentially selected according to the read update parameter or the program update parameter in the memory blocks, for example, the memory blocks having the highest update parameter and the lowest update parameter, Blocks, and sequentially selects the target memory blocks in accordance with the erase parameter in the memory blocks, for example, the memory blocks having the most significant erase parameter and the least significant erase parameter are selected as the target memory blocks And, to swap the source and target memory block between memory blocks to perform wear leveling. Accordingly, in the embodiment of the present invention, the wear leveling of the memory blocks of the memory device 150 is more efficiently performed, and in particular, the hot data due to the frequency / number / aging of the read / write / Data is stored in the memory block having the lowest-order error parameter, and the cold data due to the frequency / number / aging of the read / write / erase is stored in the memory block having the most significant erase parameter, , The use efficiency of the memory blocks included in the memory device 150 can be maximized. Hereinafter, the operation of processing data in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIG.

13 is a diagram schematically illustrating an operation process of processing data in a memory system according to an embodiment of the present invention.

Referring to FIG. 13, in step 1310, the memory system stores, in step 1310, a list in which parameters are recorded, for example, an update list in which update parameters for memory blocks are recorded, Check the error parameter, that is, the erase list in which the EC is recorded.

Then, in step 1320, in the memory blocks of the memory device, in the update list and the erase list, a source for performing a software level for the memory blocks of the memory device, considering update parameters and ECs for the memory blocks Select memory blocks and target memory blocks.

Then, in step 1330, the software leveling of the memory blocks of the memory device is performed, in other words, the selected source memory blocks and the target memory blocks are swapped in consideration of the update parameter and the EC, And performs wear leveling on the data.

Here, considering the parameters for the memory blocks of the memory device, that is, the update parameter and the erase parameter for the memory blocks, the parameter check for the memory blocks, and the parameters of the memory blocks, And the execution of the wear level for the memory blocks after selecting the target memory blocks have been described in detail with reference to FIG. 12, and a detailed description thereof will be omitted here.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims

A memory device including a plurality of pages including a plurality of memory cells connected to a plurality of word lines and storing data, and a plurality of memory blocks including the pages; And
And a command operation corresponding to a command received from the host, and after confirming a parameter for the memory blocks corresponding to the command operation, And a controller for selecting source memory blocks and target memory blocks in the memory blocks, respectively,
Memory system.

The method according to claim 1,
The controller comprising:
Selecting, in the memory blocks, the memory blocks having the highest parameter as the first source memory block and the first target memory block;
In the memory blocks, the memory blocks having the lowest parameter are selected as the second source memory block and the second target memory block.
Memory system.

3. The method of claim 2,
The controller comprising:
Swapping between the first source memory block and the second target memory block;
And swapping between the second source memory block and the first target memory block,
Memory system.

3. The method of claim 2,
Wherein the controller confirms an update parameter for the memory blocks corresponding to a read operation or a program operation in the command operation,
Memory system.

5. The method of claim 4,
The controller comprising:
Identifying, in the memory blocks, the first source memory block having the maximum update parameter;
Identifying, in the memory blocks, the first source memory block having the minimum update parameter;
Memory system.

3. The method of claim 2,
Wherein the controller is configured to determine an erase parameter for the memory blocks corresponding to an erase operation in the command operation,
Memory system.

The method according to claim 6,
The controller comprising:
Identifying the first target memory block having the largest erase parameter in the memory blocks;
Determining the first target memory block having the minimum erase parameter in the memory blocks,
Memory system.

The method according to claim 1,
Wherein the controller writes the parameters for the memory blocks for each index of the memory blocks to generate a list and stores the list in the memory of the controller, Updating the parameters recorded in the list,
Memory system.

9. The method of claim 8,
Wherein the controller sequentially arranges the memory blocks according to the parameters recorded in the list and sequentially selects the aligned memory blocks as the source memory blocks and the target memory blocks,
Memory system.

10. The method of claim 9,
The controller comprising:
In the aligned memory blocks, hot memory blocks are selected as a first source memory block and a first target memory block;
In the aligned memory blocks, cold memory blocks are selected as a second source memory block and a second target memory block.
Memory system.

Receiving a command from a host for a plurality of pages each of which is contained in a plurality of memory blocks of a memory device and includes a plurality of memory cells connected to a plurality of word lines, ;
Performing a command operation corresponding to the command between the controller of the memory device and the memory blocks;
Identifying a parameter for the memory blocks corresponding to the command operation; And
And selecting source memory blocks and target memory blocks in the memory blocks, respectively, corresponding to the parameter.
A method of operating a memory system.

12. The method of claim 11,
Wherein the selecting comprises:
Selecting, in the memory blocks, memory blocks having a top parameter as a first source memory block and a first target memory block; And
Selecting memory blocks having the lowest parameters as the second source memory block and the second target memory block in the memory blocks,
A method of operating a memory system.

13. The method of claim 12,
Swapping between the first source memory block and the second target memory block; And
And swapping between the second source memory block and the first target memory block.
A method of operating a memory system.

13. The method of claim 12,
Wherein the verifying step comprises verifying an update parameter for the memory blocks corresponding to a read operation or a program operation in the command operation.
A method of operating a memory system.

15. The method of claim 14,
Wherein the selecting comprises:
Identifying, in the memory blocks, the first source memory block having the maximum update parameter; And
Further comprising: identifying, in the memory blocks, the first source memory block having the minimum update parameter;
A method of operating a memory system.

13. The method of claim 12,
Wherein the verifying step comprises:
Determining an erase parameter for the memory blocks, corresponding to an erase operation in the command operation;
A method of operating a memory system.

17. The method of claim 16,
Wherein the selecting comprises:
Identifying the first target memory block having the largest erase parameter in the memory blocks; And
Further comprising identifying the first target memory block having the minimum erase parameter in the memory blocks,
A method of operating a memory system.

12. The method of claim 11,
Generating a list by recording the parameter for each of the memory blocks according to an index for the memory blocks, respectively;
Storing the list in a memory of the controller; And
And updating the parameters recorded in the list in response to the command operation.
A method of operating a memory system.

19. The method of claim 18,
And arranging the memory blocks according to the parameters recorded in the list;
Wherein the selecting comprises:
And sequentially selecting the aligned memory blocks as the source memory blocks and the target memory blocks, respectively,
A method of operating a memory system.

20. The method of claim 19,
Wherein the selecting comprises:
In the aligned memory blocks, selecting hot memory blocks as a first source memory block and a first target memory block; And
Selecting cold memory blocks as a second source memory block and a second target memory block in the aligned memory blocks,
A method of operating a memory system.