KR20170064977A - System and Method for constructing a Bounding Volume Hierarchy Tree - Google Patents

Abstract

A method and system for constructing a BVH tree based on a plurality of 3D tiles converted from a plurality of 2D tiles.

Description

System and Method for Constructing a Bounding Volume Hierarchy Tree [

The present disclosure relates to a method and system for constructing a BVH tree.

Hierarchical structures, such as logical tree structures, are known in various technical fields and can be used to construct information in a logical form to facilitate the storage and retrieval of information. In a typical implementation, the top node or " root " of the logical tree may contain the most general information, and the descendant nodes of the logical tree (e.g., child nodes or grandchild nodes) . It is desirable to search the logical tree through the shortest path in the shortest time to store and retrieve information.

In graphics processing and rendering, ray tracing refers to an area that uses hierarchical structures to organize information. Ray tracing can be a promising technology to enhance the visual experience of graphics applications. Ray tracing includes a technique for determining the visibility of an object (e.g., a geometric primitive) from a given point in space (e.g., eye, camera viewpoint). The primitives of a particular scene to be rendered are generally located within the nodes, and the nodes may be organized in a hierarchical tree. Ray tracing may include a first operation of "node search" to search for nodes of the tree in a particular way in an attempt to find nodes with primitives, and to provide a particular visual effect, one or more primitives Quot; primitive crossing "in which the light rays intersect with each other.

In contrast to node search and primitive intersection, a hierarchical structure may be configured to organize objects efficiently, and a hierarchical structure may be defined by a higher level node (e.g., a parent node) with two or more lower level nodes Node). A child node can define successively smaller space and contain fewer objects in succession than a parent node. The partitioning scheme can be repeated for each of the child nodes, and each child node can be divided into two or more grandchild nodes. Each grandchild node can define successively smaller spaces and contain fewer objects in succession than child nodes.

Ray tracing technology can provide high quality graphics rendering, but due to the high computational cost and requirements, ray tracing has been limited to offline rendering. With recent advances in computational power available, ray tracing has been described as possible at a reciprocal frame rate, even on a mobile platform. It is even possible to integrate into commercial mobile products in the form of hybrid rendering. For graphics rendering, hybrid rendering can mean the use of rasterization and ray tracing techniques. Conventional systems of ray tracing used accelerated structures such as a BVH tree (Bounded Volume Hierarchy tree) and a KD tree (K-dimensional tree). In conventional systems, structures such as BVH may be created utilizing a CPU or the like. However, attempts have been made to create structures utilizing a parallel processor architecture (e.g., a GPU).

And to provide a method and system for constructing a BVH tree.

The technical problem to be solved by this embodiment is not limited to the above-mentioned technical problems, and other technical problems can be deduced from the following embodiments.

According to an aspect, a method of constructing a BVH tree comprises: generating a plurality of 2D (two dimensional) tiles comprising a plurality of primitives; Converting each of the 2D tiles into a plurality of 3D tiles; And constructing a BVH tree based on the plurality of 3D tiles.

According to another aspect, a method of constructing a BVH tree comprises: receiving a leaf node corresponding to an upper layer of a BVH tree; Generating a parent node, corresponding to a leaf node, associated with a parent node identifier; Determining availability of a parent node identifier in the BVH cache; And configuring a lower layer of the BVH tree based on the availability of the parent node identifier.

According to another aspect, a system for constructing a BVH tree (Bounded Volume Hierarchy tree) comprises generating a plurality of 2D tiles comprising a plurality of primitives, converting each of the 2D tiles into a plurality of 3D tiles ; And a Graphics Processing Unit (GPU) comprising a BVH unit that constitutes a BVH tree, based on the plurality of 3D tiles.

According to another aspect, a system comprising a BVH tree (Bounded Volume Hierarchy tree) receives a leaf node corresponding to an upper layer of the BVH tree and generates a parent node associated with the parent node identifier corresponding to the leaf node , And a graphics processing unit (GPU) that includes a BVH unit that determines the availability of a parent node identifier in the BVH cache and configures a lower layer of the BVH tree based on the availability of the parent node identifier.

According to another aspect, there is provided a computer-readable recording medium on which a program for implementing the above-described method is recorded.

Figure 1 shows a system for constructing a BVH tree, according to one embodiment.
2 discloses various components of a GPU according to one embodiment.
FIG. 3 illustrates a process performed during a binning pass for the generation of 2D tiles, in accordance with one embodiment.
4 shows a hardware structure that constitutes a BVH tree, according to one embodiment.
Figure 5 discloses a lower tree conduction pipeline for constructing a lower layer of a BVH tree, according to one embodiment.
6 illustrates a method for constructing a BVH tree according to one embodiment.
7 illustrates a method of constructing a leaf node corresponding to an upper layer of a BVH tree, according to an embodiment.
Figures 8 and 9 illustrate a method for constructing a lower layer of a BVH tree, according to one embodiment.
10 illustrates a computing environment for implementing a method for parallel coding of slice segments, in accordance with one embodiment.

Although the terms used in the present embodiments have been selected in consideration of the functions in the present embodiments and are currently available in common terms, they may vary depending on the intention or the precedent of the technician working in the art, the emergence of new technology . Also, in certain cases, there are arbitrarily selected terms, and in this case, the meaning will be described in detail in the description part of the embodiment. Therefore, the terms used in the embodiments should be defined based on the meaning of the terms, not on the names of simple terms, and on the contents of the embodiments throughout.

In the descriptions of the embodiments, when a part is connected to another part, it includes not only a case where the part is directly connected but also a case where the part is electrically connected with another part in between . Also, when a component includes an element, it is understood that the element may include other elements, not the exclusion of any other element unless specifically stated otherwise. The term " ... ", "module ", as used in the embodiments, means a unit for processing at least one function or operation, and may be implemented in hardware or software, or a combination of hardware and software Can be implemented.

It should be noted that the terms such as "comprising" or "comprising ", as used in these embodiments, should not be construed as necessarily including the various components or stages described in the specification, Some steps may not be included, or may be interpreted to include additional components or steps.

The following description of the embodiments should not be construed as limiting the scope of the present invention and should be construed as being within the scope of the embodiments of the present invention.

Unlike conventional systems and methods, the method according to the present disclosure can be used to optimize a BVH (Bounded Volume Hierarchy tree) construction using a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU) . According to the present disclosure, a BVH configuration can be distributed to a CPU, a GPU, and an accelerator to reuse computation and memory reads / writes used in tile-based mobile GPUs. According to one embodiment, a hierarchical linear BVH (HVL) technique may be used to construct a two-layer BVH tree that includes upper layers and lower layers. The upper layer of the BVH tree may be configured using SAH (Surface Area Heuristic), and the lower layer may be configured using LBVH (Linear BVH). According to one embodiment, the structure of an accelerator operated according to a compute shader of a GPU may be provided to construct a lower layer of the BVH tree.

The method and system according to the present disclosure may utilize cache based fixed function hardware to construct a BVH tree. According to one embodiment, the BVH tree may be configured using cache-based fixed functionality hardware. Unlike the conventional method, in order to construct the BVH tree, the cache-based fixed function hardware may sequentially receive a plurality of 3D (3 Dimensional) tiles. Thus, the BVH tree configuration and the bounding volume update can be performed in cache-based fixed functionality hardware. In addition, cache based fixed functionality hardware according to this disclosure may utilize "Fast and Simple Agglomerative LBVH" to improve LBVH configuration.

Unlike the conventional method, the method and system according to the present disclosure is based on hybrid rendering, in which the BVH tree configuration (i.e., subtree generation and parent tree generation) is performed in parallel with a rasterization pass, ), We can provide another pipeline for BVH tree construction. According to one embodiment, the upper layer of the BVH tree may be configured in CPU or GPU shader cores. The lower layers of the BVH tree can be configured in the GPU using cache-based fixed hardware. Thus, the pipeline according to the present disclosure can utilize cache-based fixed functionality hardware within the CPU and GPU for efficient execution of the BVH configuration in the context of hybrid rendering, for tile-based mobile GPU architectures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Exemplary embodiments will now be described in detail with reference to the accompanying drawings.

Figure 1 shows a system 100 for constructing a BVH tree, according to one embodiment. System 100 represents a pipeline that constitutes a BVH tree for hybrid rendering. According to one embodiment, the system 100 may include a GPU 102, a CPU 104, and a storage 106. GPU 102 may include a binning pass 108, a rasterization pass 110, and a ray tracing pass 112.

CPU 104 may perform one or more steps to configure the BVH tree. The CPU 104 may independently configure the BVH tree, or the CPU 104 may configure the BVH tree with the GPU 102. In generating the BVH tree, a portion of the BVH tree may be configured in the CPU 104 and another portion of the BVH tree may be configured in the GPU 102. [ According to one embodiment, an upper tree creation may be performed at the GPU 102 or the CPU 104.

The storage 106 may be configured to store one or more primitives in the image. In accordance with one embodiment, GPU 102 and CPU 104 may communicate with storage 106 to obtain one or more primitives. The storage 106 may include one or more computer-readable storage media. The storage 106 may include non-volatile storage elements. Examples of non-volatile storage elements include, but are not limited to, magnetic hard disks, optical discs, floppy discs, flash memories, electrically programmable memories (EPROM) And electrically erasable and programmable memories (EEPROM) types. Additionally, according to one example, storage 106 may be a non-transitory storage medium. The term "non-transitory" may mean that it is not implemented in a carrier wave or a propagated signal. However, the term non-temporal can not be construed as meaning that the storage unit 106 is not movable. In some examples, the storage 10 may be configured to store a significant amount of information over memory. In certain embodiments, the non-volatile storage medium may store data that varies over time (e.g., RAM (Random Access Memory) or cache).

According to one embodiment, although not shown in FIG. 1, the binning pass 108 may include various components to create a plurality of 2D tiles. In binning pass 108, a plurality of primitives may be received as input. Based on the location of the vertices of a plurality of primitives, as each primitive is classified into different bins, a plurality of 2D tiles can be generated. Thus, the input of the binning pass 108 may comprise a plurality of primitives, and the output of the binning pass 108 may comprise a plurality of 2D tiles. The various components of the binning pass 108 will now be described with reference to FIG.

A plurality of 2D tiles generated through the binning pass 108 may be used in the rasterization pass 110. The rasterization pass 110 may generate data used by a ray generation block (not shown) to generate rays for the ray tracing path 112.

The output of the binning pass 108, which may include a plurality of 2D tiles, may be provided as input to the BVH tree generation. In the subtree creation and parent tree creation, each 2D tile can be converted into a plurality of 3D tiles. According to one embodiment, a BVH tree (i.e., a subtree and a super-tree) may be generated based on a plurality of 3D tiles.

According to one embodiment, a plurality of 3D tiles may be sequentially received from the binning pass 108 to construct a BVH tree. The upper layer of the BVH tree may be configured in the CPU 104 or the GPU shader core. The lower layer of the BVH tree can be configured in the GPU using cache based fixed function hardware.

In accordance with one embodiment, each 3D tile can be converted to a lower layer of the BVH tree using cache-based fixed functionality hardware. The cache-based fixed function hardware will be described in FIG.

According to one embodiment, candidate primitives may be received from one or more 3D tiles, and leaf notes may be constructed based on candidate primitives. The leaf node may correspond to an upper layer of the BVH tree.

Thus, the BVH tree generation may include subtree generation and parent tree generation, and for image generation, the generated BVH tree may be used by the ray tracing path 112. Unlike conventional systems and methods, the BVH tree may be configured using GPU 102 and CPU 104. [ In accordance with the method proposed herein, the BVH configuration may be distributed to the GPU 102 and the CPU 104. [ Unlike conventional systems, BVH generation may be performed in parallel with the rasterization pass 110.

The system 100 shown in FIG. 1 is only shown in the components associated with this embodiment. Therefore, it will be understood by those skilled in the art that other general-purpose components other than the components shown in FIG. 1 may be further included. In addition, GPUs 102 within system 100 may include units or sub-units capable of communicating with each other. Similarly, the functions of one or more units may be integrated by a single unit and may be distributed to different units in different ways.

FIG. 2 discloses various components of the GPU 102 in accordance with one embodiment. According to one embodiment, the GPU 102 may include a binning unit 202, a BVH unit 204, a rasterization unit 206, and a ray tracing unit 208.

According to one embodiment, the binning unit 202 may be configured to generate a plurality of 2D tiles. The binning unit 202 may be configured to receive a plurality of primitives. The binning unit 202 may be configured to classify each primitive into different bins based on the location of the vertices of each primitive to generate a plurality of 2D tiles. Each 2D tile may contain information of a plurality of primitives belonging to a tile. In addition, the binning unit 202 may be configured to convert each 2D tile of the plurality of 2D tiles into a plurality of 3D tiles.

The BVH unit 204 may be configured to perform one or more steps to configure the BVH tree. The BVH tree may be configured based on a plurality of 3D tiles received from the binning unit 202. [ The BVH unit 204 may comprise various components for constructing a BVH tree. Various components of the BVH unit 204 will be described with reference to FIG.

According to one embodiment, the BVH unit 204 may be configured to sequentially receive a plurality of 3D tiles to construct a BVH tree. The BVH unit 204 may be configured to receive candidate primitives from one or more 3D tiles. The BVH unit 204 may be configured to construct a leaf node corresponding to an upper layer of the BVH tree based on the received candidate primitive. The BVH unit 204 may be configured to generate a parent node corresponding to the leaf node. Each parent node may be associated with a parent node identifier. The BVH unit 204 may be configured to determine the availability of the parent node identifier in the BVH cache. In addition, the BVH unit 204 may be configured to configure the lower layer of the BVH tree based on the availability of the parent node identifiers.

According to one embodiment, the rasterization unit 206 may be configured to generate data used for ray generation for the ray tracing path 112.

According to one embodiment, the ray tracing unit 208 may be configured to generate an image. The image may be generated using a BVH tree configured by BVH unit 204. [ Ray tracing unit 208 may be configured to receive the BVH tree from BVH unit 204. [

The GPU 102 shown in Fig. 2 shows only the components related to the present embodiment. Accordingly, it will be understood by those skilled in the art that other general-purpose components other than the components shown in FIG. 2 may be further included. In addition, GPUs 102 within system 100 may include units or sub-units capable of communicating with each other. Similarly, the functions of one or more units may be integrated by a single unit and may be distributed to different units in different ways.

FIG. 3 illustrates a process performed during a binning pass for the generation of 2D tiles, in accordance with one embodiment. According to one embodiment, the binning pass 108 may include an attribute fetch unit 302, a vertex shader unit 304, a primitive transformation block 306, and a binning unit 202. Figure 3 illustrates various steps in the binning pass 108 of the tile-based rendering.

According to one embodiment, the attribute fetch unit 302 may be configured to fetch the attributes of the vertices from the store 106.

According to one embodiment, the vertex shader unit 304 may be configured to transform the three-dimensional position of each vertex of the primitive in virtual space into two-dimensional coordinates. The vertex shader unit 304 can be configured to manipulate various properties such as location, color, texture coordinates of primitives, but can not create new vertices for primitives.

According to one embodiment, the primitive transformation block 306 may be configured to transform a plurality of primitives into tiles.

In binning pass 108, a plurality of primitives (e.g., triangles) may be received from the vertex shader unit 304.

According to one embodiment, the binning unit 202 may be configured to receive a plurality of primitives. In addition, the binning unit 202 can be configured to generate a plurality of 2D tiles by classifying each primitive into different bins based on the location of the vertices of the plurality of primitives. Each 2D tile of the generated plurality of 2D tiles may include information of primitives included in the 2D tile.

4 shows a hardware structure that constitutes a BVH tree, according to one embodiment. According to one embodiment, the BVH unit 204 may include cache based fixed functionality hardware. The cache based fixed function hardware includes an address calculation unit 402, a BVH cache 404, an L2 cache 406, a dynamic random access memory (DRAM) 408, and a bounding box merge 410 can do. The address calculation unit 402 and the bounding box merging unit 410 may be fixed function hardware.

According to one embodiment, the BVH cache 404 may include tags 404a, data 404b, bitmap 404c, and Miss State Handle Register (MSHR) 404d.

A plurality of primitives may be provided to the cache-based fixed functionality hardware. According to one embodiment, a plurality of primitives may be classified using Morton codes. BVH unit 204 may be configured to receive candidate primitives from one or more 3D tiles. According to one embodiment, a plurality of 3D tiles may be obtained by the BVH unit 204. [ The various steps of obtaining a plurality of 3D tiles will be described with reference to FIG.

According to one embodiment, a leaf node may be configured based on a candidate primitive. The configured leaf node may correspond to an upper layer of the BVH tree. Thus, each primitive can be configured as a leaf node in the BVH unit 204.

4, when the leaf node L is received, the address calculation unit 402 calculates the address of the leaf node using the base address and the offset, based on the position of the leaf node in the BVH tree / RTI > After the address computation of the leaf node, the address computation unit 402 may be configured to communicate an L2 write request (L2 write request) to the L2 cache 406 according to the computed leaf node address. The address calculation unit 402 may also send the leaf node to the BVH cache 404 to create a parent node corresponding to the leaf node. According to one embodiment, each parent node may be uniquely identified with a leaf node and a corresponding parent node identifier. The address calculation unit 402 may also receive the intermediate node I from the bounding box merger 410 and forward it to the BVH cache 404 until the last node is created.

According to one embodiment, the availability of the parent node in the BVH cache 404 may be determined by querying the BVH cache 404 with the parent node identifier.

According to one embodiment, the availability of the parent node identifier in the BVH cache 404 may be determined based on a bit vector. The bit vector may be determined to ascertain the availability of the parent node in the BVH cache 404. If a bit vector is set, it may indicate that the first child node of the parent node is available in the L2 cache 406 (e.g., if the bit vector is set to one). In other words, when the bit vector is set, the first child node corresponding to the parent node may be evicted from the BVH cache 404 to the L2 cache 406 before the arrival of the second child node corresponding to the parent node. Thus, the BVH cache 404 may forward a read request for the parent node to the L2 cache 406, and an entry may be generated at the MSHR 404d.

After fetching the first child node from the BVH cache 404, the leaf node may be declared as the second child node corresponding to the parent node. Also, the BVH cache 404 may send the first child node and the second child node to the bounding box merger 410. The bounding box merging unit 410 may receive the first child node and the second child node corresponding to the parent node.

If the bit vector corresponding to the parent node is not set, two scenarios may be possible. Looking at the first scenario, it can be verified whether the parent node identifier is available in the BVH cache 404. If the parent node identifier is available in the BVH cache 404, the first child node corresponding to the parent node may be fetched from the BVH cache 404. After fetching the first child node from the BVH cache 404, the leaf node may be declared as the second child node corresponding to the parent node. Also, the BVH cache 404 may send the first child node and the second child node to the bounding box merger 410. The bounding box merging unit 410 may receive the first child node and the second child node corresponding to the parent node.

Looking at the second scenario, it can be verified whether the parent node identifier is available in the BVH cache 404. If the parent node identifier is not available in the BVH cache 404, the leaf node may be declared as the first child node corresponding to the parent node. In addition, the BVH cache 404 may store information of the first child node corresponding to the parent node. According to one embodiment, an entry may be made in the BVH cache 404 for the parent node. If all entries are exhausted in the cache, eviction in the BVH cache 404 may occur.

In addition, the DRAM 408 may include an array of leaf nodes and each of the intermediate nodes for each tile. By way of example, DRAM 408 may include an array of leaf nodes and intermediate nodes, respectively, for tile T0, and an array of leaf nodes and intermediate nodes for tile T1.

Figure 5 discloses a lower tree conduction pipeline for constructing a lower layer of a BVH tree, according to one embodiment. The binning data (which may include a plurality of 2D tiles) generated in the binning pass 108 may be used to construct a lower layer of the BVH tree. The pipeline for constructing the lower layer of the BVH tree is shown in Fig. From Fig. 5, a plurality of 2D tiles can be obtained from the binning unit 202, and a plurality of 2D tiles in the BVH unit 204 can be converted into a plurality of 3D tiles.

Referring to FIG. 5, a plurality of 2D tiles may be obtained from each bin. After obtaining the primitives for the 2D tiles and performing the vertex shading and primitive assembly steps (required in rasterization), a compute shader can be executed, so that all primitives are based on the Morton code Can be classified. The Z binning unit may then switch a plurality of 2D tiles according to Z to output a plurality of 3D tiles. These 3D tiles may be provided as input to cache-based fixed functionality hardware to construct a BVH tree.

6 illustrates a method for constructing a BVH tree according to one embodiment. According to one embodiment, at step 602, the method 600 may comprise receiving a plurality of primitives. The binning unit 202 may receive a plurality of primitives. In step 604, the method 600 may include classifying each primitive to generate a plurality of 2D tiles. The binning unit 202 may classify each primitive to produce a plurality of 2D tiles.

In step 606, the method 600 may include the step of converting each 2D tile into a plurality of 3D tiles. The binning unit 202 or BVH unit 204 may convert each 2D tile into a plurality of 3D tiles. In step 608, the method 600 may comprise constructing a BVH tree based on a plurality of 3D tiles. The steps in method 600 may be performed in a different order other than the order shown in FIG. 6, or may be performed simultaneously. Also, in accordance with some embodiments, some steps of FIG. 6 may be modified or omitted to the extent that they do not depart from the scope of the present invention.

7 illustrates a method of constructing a leaf node corresponding to an upper layer of a BVH tree, according to an embodiment. In step 702, the method 700 may include receiving a plurality of primitives. The binning unit 202 may receive a plurality of primitives. In step 704, the method 700 may include classifying each primitive to generate a plurality of 2D tiles. The binning unit 202 may classify each primitive to produce a plurality of 2D tiles.

In step 706, the method 700 may include transforming each 2D tile into a plurality of 3D tiles. The binning unit 202 or the BVH unit 204 may convert each 2D tile into a plurality of 3D tiles. In step 708, the method 700 may include receiving a candidate primitive from one or more 3D tiles. BVH unit 204 may receive a candidate primitive from one or more 3D tiles. In step 710, the method 700 may comprise constructing a leaf node corresponding to an upper layer of the BVH tree based on the candidate primitive. The BVH unit 204 may configure a leaf node corresponding to an upper layer of the BVH tree based on the candidate primitive. Each step in method 700 may be performed in a different order other than the order shown in FIG. 7, or may be performed simultaneously. Also, in accordance with some embodiments, some steps of FIG. 7 may be modified or omitted to the extent that they do not depart from the scope of the present invention.

Figures 8 and 9 illustrate a method for constructing a lower layer of a BVH tree, according to one embodiment.

First, in Figure 8, at step 802, the method 800 may include receiving a leaf node corresponding to an upper layer of the BVH tree. The BVH unit 204 may receive a leaf node corresponding to an upper layer of the BVH tree.

In step 804, the method 800 may include generating a parent node corresponding to the leaf node. The BVH unit 204 may generate a parent node corresponding to the leaf node. Each generated parent node may be associated with a parent node identifier. At step 806, the method 800 may allow determining the availability of the parent node identifier in the BVH cache 404. The BVH unit 204 may determine the availability of the parent node identifier in the BVH cache 404. In accordance with one embodiment, the availability of the parent node identifier in the BVH cache 404 may be determined by determining or verifying the bit vector.

In step 808, the method 800 may include determining whether a bit vector is set. The BVH unit 204 may determine whether a bit vector has been set. If it is determined that the bit vector is set, at step 810, the method 800 may include fetching information of the first child node corresponding to the parent node from the BVH cache 404. The BVH unit 204 may fetch the information of the first child node corresponding to the parent node from the BVH cache 404. In step 812, the method 800 may declare the leaf node as the second child node corresponding to the parent node. The BVH unit 204 may declare the leaf node as the second child node corresponding to the parent node. In step 814, the method 800 may include merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. The BVH unit 204 may merge the bounding box corresponding to the first child node and the bounding box corresponding to the second child node.

If the bit vector is not set in step 808, then in step 816, the method 800 may include determining whether the parent node identifier is available in the BVH cache 404. The BVH unit 204 may determine whether the parent node identifier is available within the BVH cache 404. At step 818, the method 800 may include fetching information of the first child node corresponding to the parent node from the BVH cache 404. The BVH unit 204 may fetch the information of the first child node corresponding to the parent node from the BVH cache 404. In step 820, the method 800 may include declaring a leaf node as a second child node corresponding to a parent node. The BVH unit 204 may declare the leaf node as the second child node corresponding to the parent node. At step 822, the method 800 may include merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. The BVH unit 204 may merge the bounding box corresponding to the first child node and the bounding box corresponding to the second child node.

In step 816, if the parent node identifier is not available in the BVH cache 404, referring to FIG. 9, in step 824, the method 800 determines whether the BVH cache 404 has an invalid entry Step < / RTI > The BVH unit 204 may determine whether the BVH cache 404 has an invalid entry. If the BVH cache has an invalid entry, then at step 826, the method 800 may declare the leaf node as the first child node corresponding to the parent node. The BVH unit 204 may declare the leaf node as the first child node corresponding to the parent node. In step 828, the method 800 may include storing the information of the first child node in the BVH cache 404. The BVH unit 204 may store the information of the first child node in the BVH cache 404.

At step 824, if the BVH cache 404 does not have an invalid entry, the method 800 may include using a policy to drive out the cache line and mark the entry on the bit line . The BVH unit 204 may use a policy to drive out the cache line and mark the entry on the bit line.

Each step in the method 800 may be performed in a different order other than the order shown in Figs. 8 and 9, or may be performed at the same time. Also, in accordance with some embodiments, some steps of FIGS. 8 and 9 may be modified or omitted to the extent that they do not depart from the scope of the present invention.

10 illustrates a computing environment for implementing a method for parallel coding of slice segments, in accordance with one embodiment. 9, a computing environment 902 includes at least one processing unit 908, a memory 910, a storage 912, a plurality of processing units (not shown) Networking devices 916 and a plurality of input / output devices 914. [ The processing unit 908 may process algorithm instructions. The processing unit 908 may receive instructions from the control unit 904 to perform processing. In addition, logic and arithmetic operations involved in the execution of the instructions may be computed by the ALU 906. [

The overall computing environment 902 may be comprised of a number of homogeneous and / or heterogeneous cores, a number of different CPUs, special media, and other accelerators. The processing unit 908 may process the instructions of the algorithm. In addition, the plurality of processing units 908 may be located on a single chip or multiple chips.

An algorithm consisting of the instructions and codes required for execution may be stored in at least one of memory 910 and storage 912. The instructions may be fetched from the memory 910 or storage 912 and executed by the processing unit 908. [

In the case of a hardware implementation, various networking devices 916 or external input / output devices 914 may be connected in a computing environment to support implementation through networking units and input / output device units.

Embodiments in accordance with the present disclosure may be implemented through at least one software program that performs network management functions that operate on and control the at least one hardware devices. Elements may be at least one hardware device in Figures 1 and 10, or a block that may be a combination of a hardware device and a software module.

The apparatus according to the above embodiments may include a processor, a memory for storing and executing program data, a permanent storage such as a disk drive, a communication port for communicating with an external device, a touch panel, a key, The same user interface device, and the like. Methods implemented with software modules or algorithms may be stored on a computer readable recording medium as computer readable codes or program instructions executable on the processor. Here, the computer-readable recording medium may be a magnetic storage medium such as a read-only memory (ROM), a random-access memory (RAM), a floppy disk, a hard disk, ), And a DVD (Digital Versatile Disc). The computer-readable recording medium may be distributed over networked computer systems so that computer readable code can be stored and executed in a distributed manner. The medium is readable by a computer, stored in a memory, and executable on a processor.

This embodiment may be represented by functional block configurations and various processing steps. These functional blocks may be implemented in a wide variety of hardware and / or software configurations that perform particular functions. For example, embodiments may include integrated circuit components such as memory, processing, logic, look-up tables, etc., that may perform various functions by control of one or more microprocessors or other control devices Can be employed. Similar to how components may be implemented with software programming or software components, the present embodiments may be implemented in a variety of ways, including C, C ++, Java (" Java), an assembler, and the like. Functional aspects may be implemented with algorithms running on one or more processors. In addition, the present embodiment can employ conventional techniques for electronic environment setting, signal processing, and / or data processing. Terms such as "mechanism", "element", "means", "configuration" may be used broadly and are not limited to mechanical and physical configurations. The term may include the meaning of a series of routines of software in conjunction with a processor or the like.

The specific implementations described in this embodiment are illustrative and do not in any way limit the scope of the invention. For brevity of description, descriptions of conventional electronic configurations, control systems, software, and other functional aspects of such systems may be omitted. Also, the connections or connecting members of the lines between the components shown in the figures are illustrative of functional connections and / or physical or circuit connections, which may be replaced or additionally provided by a variety of functional connections, physical Connection, or circuit connections.

In this specification (particularly in the claims), the use of the terms "above" and similar indication words may refer to both singular and plural. In addition, when a range is described, it includes the individual values belonging to the above range (unless there is a description to the contrary), and the individual values constituting the above range are described in the detailed description. Finally, if there is no explicit description or contradiction to the steps constituting the method, the steps may be performed in an appropriate order. It is not necessarily limited to the description order of the above steps. The use of all examples or exemplary terms (e. G., The like) is merely intended to be illustrative of technical ideas and is not to be limited in scope by the examples or the illustrative terminology, except as by the appended claims. It will also be appreciated by those skilled in the art that various modifications, combinations, and alterations may be made depending on design criteria and factors within the scope of the appended claims or equivalents thereof.

Claims (26)

A method for constructing a BVH tree (Bounded Volume Hierarchy tree)
Creating a plurality of 2D dimensional tiles comprising a plurality of primitives;
Converting each of the 2D tiles into a plurality of 3D tiles; And
And constructing the BVH tree based on the plurality of 3D tiles. The method according to claim 1,
Wherein the plurality of 3D tiles are received sequentially to construct the BVH tree. The method according to claim 1,
Wherein the generating comprises:
Receiving the plurality of primitives; And
And classifying each of the plurality of primitives into different bins based on a location of vertices of the plurality of primitives to generate the plurality of 2D tiles. The method according to claim 1,
Wherein the configuring comprises:
Receiving a candidate primitive from at least one 3D tile;
Constructing a leaf node corresponding to an upper layer of the BVH tree based on the candidate primitive;
Generating a parent node, associated with a parent node identifier, corresponding to the leaf node;
Determining availability of the parent node identifier in the BVH cache; And
And configuring a lower layer of the BVH tree based on availability of the parent node identifier. 5. The method of claim 4,
Wherein configuring the lower layer comprises:
Determining whether a bit vector indicating the availability of the parent node identifier is set;
Fetching information of a first child node corresponding to the parent node from the BVH cache when the bit vector is set;
Declaring the leaf node as a second child node corresponding to the parent node; And
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 5. The method of claim 4,
Wherein configuring the lower layer comprises:
Determining whether a bit vector is not set;
Determining if the parent node identifier is available in the BVH cache if the bit vector is not set;
Fetching information of a first child node corresponding to the parent node from the BVH cache if the parent node identifier is available;
Declaring the leaf node as a second child node corresponding to the parent node; And
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 5. The method of claim 4,
Wherein configuring the lower layer comprises:
Determining whether a bit vector is set;
If the bit vector is not set, determining whether the parent node identifier is available in the BVH cache;
If the parent node identifier is not available, declaring a first child node corresponding to the parent node as the leaf node; And
And storing information of the first child node in the BVH cache. A method for constructing a BVH tree (Bounded Volume Hierarchy tree)
Receiving a leaf node corresponding to an upper layer of the BVH tree;
Generating a parent node, corresponding to the leaf node, associated with a parent node identifier;
Determining availability of the parent node identifier in the BVH cache; And
And constructing a lower layer of the BVH tree based on availability of the parent node identifier. 9. The method of claim 8,
Determining whether a bit vector indicating the availability of the parent node identifier is set;
Fetching information of a first child node corresponding to the parent node from the BVH cache when the bit vector is set;
Declaring the leaf node as a second child node corresponding to the parent node; And
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 9. The method of claim 8,
Wherein the configuring comprises:
Determining whether a bit vector is set;
If the bit vector is not set, determining whether the parent node identifier is available in the BVH cache;
Fetching information of a first child node corresponding to the parent node from the BVH cache if the parent node identifier is available;
Declaring the leaf node as a second child node corresponding to the parent node; And
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 9. The method of claim 8,
Wherein the configuring comprises:
Determining whether a bit vector is set;
Determining if the parent node identifier is available in the BVH cache if the bit vector is not set;
If the parent node identifier is not available, declaring a first child node corresponding to the parent node as the leaf node;
And storing information of the first child node in the BVH cache. 9. The method of claim 8,
Wherein the leaf nodes are received sequentially to construct the BVH tree. A system for constructing a BVH tree (Bounded Volume Hierarchy tree)
A binning unit for generating a plurality of 2D tiles including a plurality of primitives and converting each of the 2D tiles into a plurality of 3D tiles; And a GPU (Graphics Processing Unit) comprising BVH units that make up the BVH tree, based on the plurality of 3D tiles. 14. The method of claim 13,
Wherein the plurality of 3D tiles are sequentially received to construct the BVH tree. 14. The method of claim 13,
The binning unit includes:
Receiving the plurality of primitives,
And classifying each of the plurality of primitives into different bins based on a location of vertices of the plurality of primitives to generate the plurality of 2D tiles. 14. The method of claim 13,
The BVH unit includes:
Receiving a candidate primitive from at least one 3D tile,
Constructing a leaf node corresponding to an upper layer of the BVH tree based on the candidate primitive,
Generating a parent node, associated with a parent node identifier, corresponding to the leaf node,
Determining availability of the parent node identifier in the BVH cache,
And configuring a lower layer of the BVH tree based on availability of the parent node identifier. 17. The method of claim 16,
The BVH unit includes:
Determining whether a bit vector indicating the availability of the parent node identifier is set,
Fetching information of a first child node corresponding to the parent node from the BVH cache when the bit vector is set,
Declaring the leaf node as a second child node corresponding to the parent node,
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 17. The method of claim 16,
The BVH unit includes:
It is determined whether or not a bit vector is set,
If the bit vector is not set, determining whether the parent node identifier is available in the BVH cache,
Fetching information of a first child node corresponding to the parent node from the BVH cache when the parent node identifier is available,
Declaring the leaf node as a second child node corresponding to the parent node,
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 17. The method of claim 16,
The BVH unit includes:
It is determined whether or not a bit vector is set,
Determining whether the parent node identifier is not available in the BVH cache if the bit vector is not set;
If the parent node identifier is not available, declaring a first child node corresponding to the parent node as the leaf node,
And stores information of the first child node in the BVH cache. A system for constructing a BVH tree (Bounded Volume Hierarchy tree)
Receiving a leaf node corresponding to an upper layer of the BVH tree, generating a parent node associated with the parent node identifier corresponding to the leaf node, determining availability of the parent node identifier in the BVH cache, And a Graphics Processing Unit (GPU) comprising a BVH unit that constitutes a lower layer of the BVH tree, based on availability of the identifier. 21. The method of claim 20,
The BVH unit includes:
Determining whether a bit vector indicating the availability of the parent node identifier is set,
Fetching information of a first child node corresponding to the parent node from the BVH cache when the bit vector is set,
Declaring the leaf node as a second child node corresponding to the parent node,
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 21. The method of claim 20,
The BVH unit includes:
It is determined whether or not a bit vector is set,
If the bit vector is not set, determining whether the parent node identifier is available in the BVH cache,
Fetching information of a first child node corresponding to the parent node from the BVH cache when the parent node identifier is available,
Declaring the leaf node as a second child node corresponding to the parent node,
Merging a bounding box corresponding to the first child node and a bounding box corresponding to the second child node. 21. The method of claim 20,
The BVH unit includes:
It is determined whether or not a bit vector is set,
If the bit vector is not set, determining whether the parent node identifier is available in the BVH cache,
If the parent node identifier is not available, declaring a first child node corresponding to the parent node as the leaf node,
And stores information of the first child node in the BVH cache. 21. The method of claim 20,
Wherein the 3D tiles are determined from a 2D tile by a binning unit, and wherein the 2D tile comprises a plurality of primitives. 21. The method of claim 20,
To construct the BVH tree, the leaf nodes are received sequentially. A computer-readable recording medium storing a program for executing the method according to any one of claims 1 to 12.

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