KR20170031311A

KR20170031311A - Data storage device and operating method thereof

Info

Publication number: KR20170031311A
Application number: KR1020150128549A
Authority: KR
Inventors: 김재우; 정재형; 김광현
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2015-09-10
Filing date: 2015-09-10
Publication date: 2017-03-21

Abstract

The present invention relates to a data storage device and an operation method thereof that can efficiently perform an ECC decoding operation. A data storage device according to an embodiment of the present invention includes a nonvolatile memory device; Volatile memory device to detect whether or not data bits of data read from the nonvolatile memory device are necessary to control error correction code (ECC) decoding on the read data, and to control the error correction code (ECC) decoding A data detection block for transmitting a detection result when judged; And an error correction code (ECC) decoding block for controlling an error correction code (ECC) decoding operation on the read data in response to the detection result.

Description

&Lt; Desc / Clms Page number 1 > DATA STORAGE DEVICE AND OPERATING METHOD THEREOF &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and more particularly, to a data storage device and an operation method thereof capable of efficiently performing an ECC decoding operation.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use a data storage device that utilizes a memory device. The data storage device is used as an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because it has no mechanical driving part, has very high access speed of information and low power consumption. A data storage device having such advantages includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, and a solid state drive (SSD).

BACKGROUND ART [0002] As portable electronic devices reproduce large-capacity files such as music, moving pictures, etc., data storage devices are required to have a large storage capacity. The data storage device uses a flash memory device, which is one of the non-volatile memory devices, as a storage medium, in order to secure a large storage capacity, for example, a memory device having a high degree of integration of memory cells.

An embodiment of the present invention is to provide a data storage device and an operation method thereof that can efficiently perform an ECC decoding operation.

A data storage device according to an embodiment of the present invention includes a nonvolatile memory device; Volatile memory device to detect whether or not data bits of data read from the nonvolatile memory device are necessary to control error correction code (ECC) decoding on the read data, and to control the error correction code (ECC) decoding A data detection block for transmitting a detection result when judged; And an error correction code (ECC) decoding block for controlling an error correction code (ECC) decoding operation on the read data in response to the detection result.

A method of operating a data storage device according to an embodiment of the present invention includes counting the number of erased data bits of data read from a non-volatile memory device, comparing the number of erased data bits with a reference value, And skipping error correction code (ECC) decoding operations on the read data if the number of erasure data bits is greater than or equal to the reference value.

According to embodiments of the present invention, the operation speed of the data storage device can be increased, and the power consumption of the data storage device can be reduced while the ECC decoding operation is performed.

1 is a block diagram illustrating an exemplary data storage device in accordance with an embodiment of the present invention.
2 is a view for explaining a decoding setting register according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a state where a sensing reference value used as a determination reference of the operation of the data sensing block shown in FIGS. 4 and 5 is stored in a sensing reference value register.
FIGS. 4 and 5 are diagrams for explaining the operation of the data sensing block for detecting deletion data.
FIGS. 6 and 7 are diagrams for explaining the operation of the data sensing block for sensing data that can not be ECC decoded.
8 is a flowchart for explaining the ECC decoding operation of the data storage device.
FIG. 9 is a flowchart showing the subdivision of step S100 of FIG.
FIG. 10 is another flowchart showing the subdivision of step S100 of FIG.
11 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention.
12 is a block diagram illustrating an exemplary data processing system including a solid state drive (SSD) in accordance with an embodiment of the present invention.
13 is a block diagram exemplarily showing the SSD controller shown in FIG.
14 is a block diagram illustrating an exemplary computer system in which a data storage device according to an embodiment of the present invention is mounted.
15 is a block diagram of a nonvolatile memory device included in a data storage device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating an exemplary data storage device in accordance with an embodiment of the present invention. The data storage device 100 may store data accessed by a host device (not shown) such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, an in- vehicle infotainment system, The data storage device 100 may also be referred to as a memory system.

The data storage device 100 may be manufactured in any one of various types of storage devices according to an interface protocol connected to the host device. For example, the data storage device 100 may be a solid state drive (SSD), an MMC, an eMMC, an RS-MMC, a multi-media card in the form of a micro- a secure digital card in the form of micro-SD, a universal storage bus (USB) storage device, a universal flash storage (UFS) device, a storage device in the form of a personal computer memory card international association (PCMCIA) ) Storage devices, PCI-E (PCI express) card-type storage devices, CF (compact flash) cards, smart media cards, memory sticks, It can be configured as any one.

The data storage device 100 may be manufactured in any one of various types of package types. For example, the data storage device 100 may be a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi chip package (MCP), a chip on board (COB) level fabricated package, a wafer-level stack package (WSP), and the like.

The data storage device 100 may include a non-volatile memory device 300. The non-volatile memory device 300 may operate as a storage medium of the data storage device 100. The nonvolatile memory device 300 may include a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a tunneling magneto (MRAM), a phase change random access memory (PRAM) using chalcogenide alloys, and a transition metal oxide (TMR) Volatile memory devices of various types such as resistive random access memory (RERAM) and the like.

The data storage device 100 may include a controller 200. The controller 200 may include a control unit 210, a random access memory 220, a data sense block 230, an error correction code (ECC) decoding block 240 and a report block 250.

The control unit 210 can control all operations of the controller 200. The control unit 210 can analyze and process signals, commands or requests input from the host device. To this end, the control unit 210 can decrypt and drive the firmware or software loaded into the random access memory 220. The control unit 210 may be implemented in hardware or a combination of hardware and software.

The random access memory 220 may store firmware or software driven by the control unit 210. In addition, the random access memory 220 may store management data such as data necessary for driving firmware or software, for example, address mapping information. That is, the random access memory 220 may operate as a working memory of the control unit 210.

The random access memory 220 may temporarily store data to be transferred from the host apparatus to the nonvolatile memory apparatus 300 or from the nonvolatile memory apparatus 300 to the host apparatus. That is, the random access memory 220 may operate as a data buffer memory or a data cache memory.

The data sensing block 230 may detect data bits of data (RDT) read from the non-volatile memory device 300. That is, the data sensing block 230 can detect which digital value ("1" or "0") is formed by each of the data bits of the read data RDT. The data sense block 230 may count the number of digital values constituting the data bits and compare the number of counted digital values with the sense reference value stored in the winding reference value register 231. [ The data sensing block 230 may transmit the detection result DTCT to the error correction code (ECC) decoding block 240 and the report block 250 based on the comparison result.

The data sensing block 230 may sense what digital value ("1" or "0") the particular bit of the read data RDT is made of. The data sensing block 230 may transmit the detection result DTCT to the error correction code (ECC) decoding block 240 and the report block 250 based on the value of the specific bit detected.

The data sensing block 230 may sense the data bits of the read data RDT and then transmit the read data RDT to the error correction code (ECC) decoding block 240. [

An error correction code (ECC) decoding block 240 (hereinafter referred to as an ECC decoding block 240) may perform an ECC decoding operation on the read data RDT. That is, the ECC decoding block 240 can perform an error checking operation for checking whether or not an error is included in the read data RDT, and an error correcting operation for correcting an error that can be corrected.

The ECC decoding block 240 may include a decoding setting register 214. As shown in FIG. 2, the decoding setting register 241 may be divided into an area where a first value and a second value are stored. The first value and the second value stored in the decoding setting register 241 are determined by the control unit 210 and may be set (or stored) in the respective areas under the control of the control unit 210. [

The first value is a value that determines whether to skip the ECC decoding operation. If the first value is set to data "1 ", it means that ECC decoding should be performed, and if it is set to data" 0 ", it means that ECC decoding should be skipped. If the first value is set to data "0 ", it means that ECC decoding should proceed, and if it is set to data" 1 ", it may mean that ECC decoding should be skipped. The second value means the number of repetitions of the ECC decoding operation.

The ECC decoding block 240 may control an ECC decoding operation on data (RDT) read out in response to the detection result (DTCT) transmitted from the data sensing block (230). For example, the ECC decoding block 240 skips the ECC decoding operation for the read data (RDT) based on the detection result (DTCT) and the first value set (or stored) in the decoding setting register 241 skip). As another example, the ECC decoding block 240 may perform ECC decoding on the read data (RDT) based on the detection result (DTCT) and the first and second values set (or stored) in the decoding setting register The operation can be repeatedly performed to the second value or less.

The ECC decoding block 240 may send the result (DRSLT) of the ECC decoding operation (hereinafter referred to as the ECC decoding result (DRSLT)) to the report block 250. The ECC decoding result DRSLT may include information on whether the ECC decoding operation has been successfully completed or failed. When the ECC decoding operation is successfully completed, the ECC decoding result may include the number of error bits included in the read data (RDT), the number of error corrected error bits, and the number of times the ECC decoding operation is repeated. If the ECC decoding operation fails, the ECC decoding result may include the number of error bits included in the read data (RDT).

The report block 250 generates an ECC for the read data RDT based on the detection result DTCT transmitted from the data sensing block 230 and the ECC decoding result DRSLT transmitted from the ECC decoding block 240. [ Information ECCINF of the decoding operation to the control unit 210. [ The information ECCINF of the ECC decoding operation includes information as to whether or not the ECC decoding operation for the read data RDT has been skipped or performed, information as to whether the ECC decoding operation performed has been successfully completed or failed, The number of error bits included in the RDT, the number of error corrected error bits, and the number of times the ECC decoding operation is repeated.

Although not shown, the controller 200 may include an error correction code (ECC) encoding block. An error correction code (ECC) encoding block may perform an ECC encoding operation on data to be stored in the non-volatile memory device 300. For example, an error correction code (ECC) encoding block generates an error correction code (e.g., parity data) for data to be stored in the nonvolatile memory device 110, To the data to be stored in the nonvolatile memory device 110.

As described above, the data sensing block 230 may sense the data bits of the read data RDT. By performing the data sensing operation, the data sensing block 230 can determine whether the read data (RDT) is data requiring ECC decoding control. The data sensing block 230 may transmit the read data (RDT) to the ECC decoding block 240 as a detection result (DTCT) that the ECC decoding control is necessary.

In order to determine whether the read data RDT is data requiring ECC decoding control, the data sensing block 230 may determine whether the read data RDT is deleted data. The operation of the data sensing block 230 for determining whether the read data RDT is erased data will be described in detail with reference to FIGS.

FIG. 3 is a diagram illustrating a state where a sensing reference value used as a determination reference of the operation of the data sensing block shown in FIGS. 4 and 5 is stored in a sensing reference value register. As described above, the sensing reference value can be determined by the control unit (210 in FIG. 1). The detection reference value may be changed according to the size of the read data (RDT) or according to the error occurrence rate. For convenience of explanation, the case where the detection reference value "8" is stored in the detection reference value register 231 is illustrated in FIG.

FIGS. 4 and 5 are diagrams for explaining the operation of the data sensing block for detecting deletion data. In the description of FIGS. 4 and 5, it is assumed that data "1" is erase data and data "0" is program data. In some cases, data "0" may be erased data and data "1" may be program data. For convenience of explanation, it will be assumed that the read data (RDT) consisting of (or processed) 13 bits of user data (UD), metadata (MD) and parity data (PD).

The data sensing block 230 may sense and count the value of each of the data bits of the read data RDT until the number of data "1 ", which is the erasure data bit, is equal to the sensing reference value. 4, when the number of data "1" satisfies the detection reference value "8", that is, when the number of data "1" becomes equal to the detection reference value "8", the data sensing block 230 counts And transmit the detection result (DTCT). The detection result DTCT in this case will mean that the read data RDT is erasure data.

The data sensing block 230 may sense and count the value of each of all the data bits of the read data RDT. The data sensing block 230 may determine whether the number of the erased data bits counted is greater than or equal to a reference value. Referring to FIG. 5, the data sensing block 230 may sense and count data bits constituting the read data RDT from the beginning to the end. The data sensing block 230 may transmit the detection result DTCT when the number of data "1 ", which is the erasure data bit, is greater than or equal to the sensing reference value" 8 ". The detection result DTCT in this case will mean that the read data RDT is erasure data.

4 and 5, the data sensing block 230 compares the number of erased data bits counted with the sensing reference value stored in the sensing reference value register 231, ) Is the deleted data. This means that, by adjusting the sensing reference value, the judgment margin of the data sensing block 230 can be secured even if the values of several bits constituting the read data RDT are changed.

In order to determine whether the read data RDT is data requiring ECC decoding control, the data sensing block 230 may determine whether the read data RDT is data that can not be error-corrected. The operation of the data sensing block 230 for determining whether the read data RDT is data that can not be error-corrected will be described in detail with reference to FIGS. 6 to 7. FIG.

FIGS. 6 and 7 are diagrams for explaining the operation of the data sensing block for sensing data that can not be ECC decoded. For convenience of explanation, it will be assumed that read data (RDT) consisting of (or processed) 13 bits.

The read data RDT may be composed of user data UD, metadata MD and parity data PD. The user data UD may be data requested to be written from the host device. The metadata MD may be data for managing the user data UD. The parity data PD may be data added in the ECC encoding operation for error correction of the user data UD.

The currently read data RDT has been previously read out from the nonvolatile memory device 300 in FIG. 1 for various reasons (for example, to update the data or to secure the reliability of the data) And may be stored data. The result of the ECC decoding operation performed in a previous read operation may be stored with the user data UD as metadata (MD) before the data is again stored. That is, the metadata MD may be added to the user data UD as information related to the previous ECC decoding result of the read data RDT. The metadata MD may be information indicating whether the previous ECC decoding operation of the read data RDT was successfully completed or failed.

The data sensing block 230 may detect the value of the bits of the metadata. Referring to FIG. 6, the data sensing block 230 may sense data "1 " indicating that the previous ECC decoding result was a success. Referring to FIG. 7, the data sensing block 230 may sense data "0" indicating that the previous ECC decoding result was a failure. In this case, the data sensing block 230 may transmit a detection result (DTCT) indicating that the read data (RDT) is data that can not be error-corrected.

8 is a flowchart for explaining the ECC decoding operation of the data storage device. Hereinafter, the ECC decoding operation for the read data will be described in detail with reference to FIGS. 1 and 8. FIG.

In step S100, the data sensing block 230 determines whether the read data is an ECC decoding control signal or not based on a result of detecting a value ("1" or "0") of each of the data bits of the read data It is possible to determine whether or not the data is necessary. Data requiring ECC decoding control may mean at least one of the erased data and the data in which the previous ECC decoding operation failed. The data sensing block 230 may transmit the detection result DTCT based on the determination result to the ECC decoding block 240 when it is determined that the read data is data requiring ECC decoding control.

The operation of determining whether the read data is the deleted data will be described with reference to the flowchart of FIG. And the operation of determining whether the read data is the data in which the previous ECC decoding operation is failed will be described with reference to the flowchart of FIG.

If it is determined that the read data is data that does not require ECC decoding control, the procedure will proceed to step S200. In step S200, the ECC decoding operation on the read data can be normally performed.

On the other hand, if it is determined that the read data is data requiring ECC decoding control, the ECC decoding operation on the read data can be skipped or simplified so that the resource of the data storage device is not consumed much in the ECC decoding operation .

In step S300, the ECC decoding block 240 determines whether the first value of the decoding setting register 241 is set to "ECC decoding skip" in response to the detection result DTCT sent from the data sensing block 230 It can be judged.

If a first value (data "0" in FIG. 2) indicating skipping of the ECC decoding operation is set in the decoding setting register 241, the procedure will proceed to step S410. In step S410, the ECC decoding block 240 may skip the ECC decoding operation on the read data. In step S420, the ECC decoding block 240 may transmit the read data to the random access memory 220 used as the data buffer memory.

When the first value (data "1" in FIG. 2) indicating the progress of the ECC decoding operation is set in the decoding setting register 241, the number of repetitions of the ECC decoding operation for the read data is adjusted, and the ECC decoding operation Can be performed briefly. In step S510, the ECC decoding block 240 may perform the ECC decoding operation on the read data repeatedly below the second value of the decoding setting register 241. [

The second value may be determined to be a value smaller than the number of repetitions of the normal ECC decoding operation performed in step S200. That is, in operation S510, that is, the ECC decoding block 240 may perform the ECC decoding operation on the read data with a smaller number of times than the normal number of iterations.

In step S520, the ECC decoding block 240 may transmit the decoded data or the read data to the random access memory 220 used as the data buffer memory. The ECC decoding block 240 may transmit the decoded data to the random access memory 220 used as the data buffer memory when the ECC decoding operation for the data read in step S510 is successful. When the ECC decoding operation for the data read in step S510 fails, the ECC decoding block 240 may transmit the read data as it is to the random access memory 220 used as the data buffer memory.

FIG. 9 is a flowchart showing the subdivision of step S100 of FIG. FIG. 9 is a flowchart illustrating an operation for determining whether the read data described with reference to FIGS. 3 to 5 is deleted data.

In step S111, the data sensing block 230 may count the number of erasure data bits of the read data. In step S113, the data sensing block 230 may determine whether the counted number of erasure data bits is greater than or equal to the stored reference value stored in the sensing reference value register 231. [

If the counted number of erased data bits is equal to or greater than the sensing reference value, the read data is determined to be erasure data, and the procedure may proceed to step S300. On the other hand, if the counted number of erased data bits is smaller than the detection reference value, it is determined that the read data is not deleted data, and the procedure may proceed to step S200.

FIG. 10 is another flowchart showing the subdivision of step S100 of FIG. FIG. 10 is a flowchart of an operation for determining whether the read data described with reference to FIGS. 6 and 7 is data in which a previous ECC decoding operation is failed.

In step S121, the data sensing block 230 may sense the previous ECC decoding result value (i.e., the bit value of the metadata) of the read data. In step S123, the data sensing block 230 may determine whether the previous ECC decoding result indicates an ECC decoding failure.

If the previous ECC decoding result indicates an ECC decoding failure, the procedure may proceed to step S300. On the other hand, if the previous ECC decoding result indicates successful ECC decoding, the procedure may proceed to step S200.

11 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 11, a data processing system 1000 may include a host device 1100 and a data storage device 1200.

The data storage device 1200 may include a controller 1210 and a non-volatile memory device 1220. The data storage device 1200 may be connected to and used by a host device 1100 such as a cellular phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, an in-vehicle infotainment system, Data storage device 1200 is also referred to as a memory system.

The controller 1210 may include a host interface unit 1211, a control unit 1212, a memory interface unit 1213, a random access memory 1214 and an error correction code (ECC) unit 1215.

The control unit 1212 can control all operations of the controller 1210 in response to a request from the host apparatus 1100. [ The control unit 1212 may drive firmware or software for controlling the non-volatile memory device 1220. [

The random access memory 1214 can be used as a working memory of the control unit 1212. The random access memory 1214 may be used as a buffer memory for temporarily storing data read from the nonvolatile memory device 1220 or data provided from the host device 1100. [

The host interface unit 1211 may interface the controller 1210 with the host apparatus 1100. [ For example, the host interface unit 1211 may be a universal serial bus (USB) protocol, a universal flash storage (UFS) protocol, a multi-media card (MMC) protocol, a peripheral component interconnection (PCI) Through one of a variety of interface protocols, such as a PCI Express protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface May communicate with the device 1100.

The memory interface unit 1213 may interface the controller 1210 and the non-volatile memory device 1220. The memory interface unit 1213 may provide commands and addresses to the non-volatile memory device 1220. The memory interface unit 1213 can exchange data with the nonvolatile memory device 1220.

The memory interface unit 1213 may include a data sensing block 1216. The data sense block 1216 may sense data bits of data read from the non-volatile memory device 1220 and may send the results of the detection to an error correction code (ECC) unit 1215.

An error correction code (ECC) unit 1215 may ECC encode data to be stored in the non-volatile memory device 1220. And an error correction code (ECC) unit 1215 can ECC decode the data read from the nonvolatile memory device 1220. [ An error correction code (ECC) unit 1215 may skip or briefly perform an ECC decoding operation based on the detection result sent from the data sensing block 1216. [ An error correction code (ECC) unit 1215 may be included in the memory interface unit 1213.

The non-volatile memory device 1220 may be used as a storage medium of the data storage device 1200. The non-volatile memory device 1220 may include a plurality of non-volatile memory chips (or dies) (NVM_1 to NVM_k).

The controller 1210 and the non-volatile memory device 1220 may be fabricated in any of a variety of data storage devices. For example, the controller 1210 and the nonvolatile memory device 1220 may be integrated into a single semiconductor device and may be implemented as a multi-media card in the form of MMC, eMMC, RS-MMC, micro-MMC, SD, a secure digital card in the form of micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a PCMCIA (personal computer memory card international association) A smart media card, a memory stick, or the like.

12 is a block diagram illustrating an exemplary data processing system including a solid state driver (SSD) in accordance with an embodiment of the present invention. Referring to FIG. 12, the data processing system 2000 may include a host device 2100 and a solid state drive (SSD) 2200.

The SSD 2200 may include an SSD controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 through 223n, a power supply 2240, a signal connector 2250, a power connector 2260 have.

The SSD controller 2210 may access the non-volatile memory devices 2231 to 223n in response to a request from the host device 2100. [

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223n. In addition, the buffer memory device 2220 can temporarily store data read from the nonvolatile memory devices 2231 to 223n. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the nonvolatile memory devices 2231 to 223n under the control of the SSD controller 2210. [

The nonvolatile memory devices 2231 to 223n may be used as a storage medium of the SSD 2200. [ Each of the nonvolatile memory devices 2231 to 223n may be connected to the SSD controller 2210 through a plurality of channels CH1 to CHn. One channel may be coupled to one or more non-volatile memory devices. Non-volatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 2240 can provide the power supply PWR input through the power supply connector 2260 into the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power supply 2241 may supply power to the SSD 2200 so that the SSD 2200 can be normally terminated when sudden power off occurs. The auxiliary power supply 2241 may include large capacitors capable of charging the power supply PWR.

The SSD controller 2210 can exchange the signal SGL with the host device 2100 through the signal connector 2250. [ Here, the signal SGL may include a command, an address, data, and the like. Signal connector 2250 may be a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), or the like, depending on the interface manner of the host device 2100 and the SSD 2200. [ ), A peripheral component interconnection (PCI), and a PCI-E (PCI Express) connector.

13 is a block diagram exemplarily showing the SSD controller shown in FIG. 13, the SSD controller 2210 includes a memory interface unit 2211, a host interface unit 2212, an error correction code (ECC) unit 2213, a control unit 2214, and a random access memory 2215 .

The memory interface unit 2211 may provide a control signal such as a command and an address to the nonvolatile memory devices 2231 to 223n. The memory interface unit 2211 can exchange data with the nonvolatile memory devices 2231 to 223n. The memory interface unit 2211 may scatter data transferred from the buffer memory device 2220 to the respective channels CH1 to CHn under the control of the control unit 2214. [ The memory interface unit 2211 can transfer the data read from the nonvolatile memory devices 2231 to 223n to the buffer memory device 2220 under the control of the control unit 2214. [

The memory interface unit 2211 may include a data sensing block 2216. The data sensing block 2216 may sense data bits of data read from the non-volatile memory devices 2231 to 223n and may transmit the detection result to an error correction code (ECC) unit 2213. [

The host interface unit 2212 may provide interfacing with the SSD 2200 in correspondence with the protocol of the host device 2100. For example, the host interface 2212 may be a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI) E (PCI Express) < / RTI > protocols. The host interface unit 2212 may perform a disk emulation function to allow the host apparatus 2100 to recognize the SSD 2200 as a hard disk drive (HDD).

The control unit 2214 can analyze and process the signal SGL input from the host apparatus 2100. [ The control unit 2214 can control the operation of the buffer memory device 2220 and the nonvolatile memory devices 2231 to 223n in accordance with firmware or software for driving the SSD 2200. [ Random access memory 2215 may be used as an operating memory for driving such firmware or software.

An error correction code (ECC) unit 2213 can generate parity data of data to be transmitted to the nonvolatile memory devices 2231 to 223n from data stored in the buffer memory device 2220. [ The generated parity data may be stored in the nonvolatile memory devices 2231 to 223n together with the data. An error correction code (ECC) unit 2213 can detect an error of data read out from the nonvolatile memory devices 2231 to 223n. If the detected error is within the correction range, the error correction code (ECC) unit 2213 can correct the detected error.

An error correction code (ECC) unit 2213 may skip or briefly perform an ECC decoding operation based on the detection result sent from the data sensing block 2216. [ An error correction code (ECC) unit 2213 may be included in the memory interface unit 2211. [

14 is a block diagram illustrating an exemplary computer system in which a data storage device according to an embodiment of the present invention is mounted. 14, a computer system 3000 includes a network adapter 3100, a central processing unit 3200, a data storage 3300, a RAM 3400, a ROM 3500, ) And a user interface 3600. [ Here, the data storage device 3300 may be composed of the data storage device 100 shown in FIG. 1, the data storage device 1200 shown in FIG. 11, or the SSD 2200 shown in FIG.

The network adapter 3100 may provide interfacing between the computer system 3000 and external networks. The central processing unit 3200 may perform various operations for driving an operating system or an application program residing in the RAM 3400. [

The data storage device 3300 can store necessary data in the computer system 3000. For example, an operating system, an application program, various program modules, program data, and user data for driving the computer system 3000 May be stored in the data storage device 3300.

The RAM 3400 may be used as an operating memory of the computer system 3000. An application program, various program modules read from the data storage device 3300 and program data required for driving the programs are stored in the RAM 3400 at the boot time, Can be loaded. The ROM 3500 may store a basic input / output system (BIOS), which is a basic input / output system activated before the operating system is activated. Information exchange between the computer system 3000 and the user can be made through the user interface 3600. [

15 is a block diagram of a nonvolatile memory device included in a data storage device according to an embodiment of the present invention. 15, a non-volatile memory device 300 includes a memory cell array 310, a row decoder 320, a column decoder 330, a data read / write block 340, a voltage generator 350, (360).

The memory cell array 310 may include memory cells arranged in regions where the word lines WL1 to WLm and the bit lines BL1 to BLn cross each other. Memory cells may be grouped into access blocks, such as memory blocks, erase units, pages that are program and read units.

The row decoder 320 may be coupled to the memory cell array 310 via word lines WL1 through WLm. The row decoder 320 may operate under the control of the control logic 360. The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 can select and drive the word lines WL1 to WLm based on the decoding result. Illustratively, row decoder 320 may provide the word line voltages provided from voltage generator 350 to word lines WLl through WLm.

The column decoder 330 may be connected to the memory cell array 310 through the bit lines BL1 to BLn. The column decoder 330 may operate under the control of the control logic 360. The column decoder 330 may decode the address provided from the external device. The column decoder 330 may connect the read / write circuits of the data read / write block 340 corresponding to the bit lines BL1 to BLn and the bit lines BL1 to BLn, respectively, based on the decoding result. In addition, the column decoder 330 can drive the bit lines BL1 to BLn based on the decoding result.

The data read / write block 340 may operate under the control of the control logic 360. The data read / write block 340 may operate as a write driver or as a sense amplifier, depending on the mode of operation. For example, the data read / write block 340 may operate as a write driver that stores data provided from an external device in the memory cell array 310 during a write operation. As another example, the data read / write block 340 may operate as a sense amplifier that reads data from the memory cell array 310 during a read operation.

Voltage generator 350 may generate a voltage used for internal operation of non-volatile memory device 300. [ Voltages generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. [ For example, a program voltage generated in a program operation may be applied to a word line of memory cells in which a program operation is to be performed. As another example, the erase voltage generated in the erase operation may be applied to the well-area of the memory cells where the erase operation is to be performed. As another example, the read voltage generated in the read operation may be applied to the word line of the memory cells in which the read operation is to be performed.

The control logic 360 can control all operations of the nonvolatile memory device 300 based on control signals provided from an external device. For example, the control logic 360 may control the operation of the non-volatile memory device 100, such as the read, write, and erase operations of the non-volatile memory device 300.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Data storage device
200: controller
210: Control unit
220: Random access memory
230: Data sensing block
231: Detection reference value register
240: ECC decoding block
241: Decoding setting register
250: Report Block
300: non-volatile memory device

Claims

A nonvolatile memory device;
Volatile memory device to detect whether or not data bits of data read from the nonvolatile memory device are necessary to control error correction code (ECC) decoding on the read data, and to control the error correction code (ECC) decoding A data detection block for transmitting a detection result when judged; And
And an error correction code (ECC) decoding block for controlling an error correction code (ECC) decoding operation on the read data in response to the detection result.

The method according to claim 1,
The error correction code (ECC) decoding block may skip the error correction code (ECC) decoding operation on the read data in response to the detection result, or perform the error correction code (ECC) And the number of repetitions of the data.

3. The method of claim 2,
The error correction code (ECC) decoding block includes a decoding setting register,
Wherein the error correction code (ECC) decoding block determines whether a first value, which means skipping the error correction code (ECC) decoding operation, is stored in the decoding setting register in response to the detection result.

The method of claim 3,
Wherein the error correction code (ECC) decoding block skips the error correction code (ECC) decoding operation if the first value is stored in the decoding configuration register.

The method of claim 3,
The error correction code (ECC) decoding block repeatedly performs the error correction code (ECC) decoding operation to a second value or less stored in the decoding setting register when the first value is not stored in the decoding setting register Data storage device.

The method according to claim 1,
Wherein the data sensing block counts the number of erasure data bits of the read data and transmits the detection result when the counted number of erasure data bits is greater than or equal to a sensing reference value.

The method according to claim 6,
Wherein the data sensing block terminates the count if the number of the erased data bits counted equals the sensing reference value.

The method according to claim 6,
Wherein the data sensing block includes a sensing reference value register in which the sensing reference value is stored.

The method according to claim 1,
Wherein the read data includes a result of an error correction code (ECC) decoding operation performed in a previous read operation,
Wherein the data sensing block senses the resultant value and transmits the detection result when the resultant value indicates a failure of a previous error correction decoding (ECC) operation.

A method of operating a data storage device comprising:
The number of erasure data bits of data read from the nonvolatile memory device is counted,
Compares the counted number of erased data bits with a reference value, and
And skipping an error correction code (ECC) decoding operation on the read data if the counted number of erased data bits is greater than or equal to the reference value.

11. The method of claim 10,
Further comprising performing the error correction code (ECC) decoding operation normally when the counted number of erased data bits is less than the reference value.

11. The method of claim 10,
Further comprising decreasing the number of iterations of the error correction code (ECC) decoding operation when the counted number of erased data bits is greater than or equal to the reference value.

A method of operating a data storage device comprising:
Detecting the result of a previous error correction code (ECC) decoding operation of data currently read from the non-volatile memory device, and
And skipping current error correction code (ECC) decoding operations on the read data if the result indicates failure of the previous error correcting code (ECC) decoding operation.

14. The method of claim 13,
And performing a current error correction code (ECC) decoding operation on the read data if the resultant value indicates success of the previous error correction code (ECC) decoding operation.

14. The method of claim 13,
Further comprising decrementing the number of iterations of the error correction code (ECC) decoding operation if the result value indicates failure of the previous error correction code (ECC) decoding operation.