KR20160130026A - Liquid Crystal Display Device and Driving Method thereof - Google Patents

Abstract

The present invention relates to a display panel; a gate driver, a data driver, and a timing controller. The display panel display images. The gate driver supplies gate pulses to a display panel. The data driver supplies data voltage to a display panel. The timing controller controls the gate driver and the data driver to selectively change the driving frequency of the display panel between a low-speed driving mode and a high-speed driving mode. The timing controller divides a single frame into odd and even frames in a time-division scheme and outputs the divided frames. The timing controller also controls the gate driver to only drive the (N+1)-th and (N+2)-th gate lines and the gate lines in corresponding pairs during an odd frame and to only drive the (N+3)-th and (N+4)-th gate lines and the gate lines in corresponding pairs during an even frame.

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

The present invention relates to a liquid crystal display device and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display and a plasma liquid crystal display (PDP) ) Have been increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

A liquid crystal display device includes a liquid crystal panel and a backlight unit. The liquid crystal panel includes a transistor substrate formed with a thin film transistor, a storage capacitor, and the like, and a liquid crystal layer disposed between the color filter substrate and the color filter substrate on which the color filter and the black matrix are formed.

Conventionally, one frame is divided in order to reduce the power consumption of the liquid crystal display device and to reduce the heat generation of the data driver (Source D-IC), only the odd gate lines are driven in the odd frame, A low-speed driving method in which only the gate line is driven has been proposed. In addition, this method has been implemented in a 4-dot version (Dot Inversion) method in order to solve the problem of image quality such as vertical crosstalk as well as reduction of power consumption of a liquid crystal display device having a full high definition (FHD) resolution.

However, when the above-described conventional method is directly applied to a liquid crystal display device having a UHD (Ultra High Definition) resolution, there is a problem that a gate line in which charge is charged and a gate line in which a strong charge occurs occur in two lines A fine horizontal line appears on the liquid crystal panel). When the conventional method described above is directly applied to a liquid crystal display device having a UHD resolution, deterioration of image quality occurs at a variable driving frequency (low speed <-> high speed). Therefore, a liquid crystal display device having a UHD resolution is required to reduce power consumption, reduce the heat generation of the data driver, and improve the display quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the related art, and it is an object of the present invention to provide a liquid crystal display device having a UHD resolution capable of reducing power consumption, reducing heat generation of a data driver, preventing and improving glitch- Thereby improving display quality.

The present invention provides a liquid crystal display device including a display panel, a gate driver, a data driver, and a timing controller. The display panel displays the image. The gate driver supplies gate pulses to the display panel. The data driver supplies the data voltage to the display panel. The timing controller controls the gate driver and the data driver such that the driving frequency of the display panel is selectively variable between the low-speed driving mode and the high-speed driving mode. The timing controller outputs one frame in an odd-numbered frame and an even-numbered frame in a time division manner, and drives only the (N + 1) th and (N + 2) -th gate lines and the corresponding pair of gate lines during the first frame of the odd and even frames And controls the gate driver to drive only the (N + 3) th and (N + 4) th gate lines and the corresponding pair of gate lines during the selected second frame of the odd and even frames.

When the display panel is operated in the low-speed driving mode, about charge is generated in the (N-1) th gate line during the first frame, strong charging occurs in the Nth gate line, A strong charge is generated in the (N + 2) -th gate line, and a gate line in which approximately charging occurs during one frame including the first and second frames and a gate line in which strong charging occurs occur alternately .

The timing controller can output N compensation sub-frames (N is an integer equal to or greater than 1) during a transition period in which the driving frequency of the display panel is variable.

The timing controller may vary the gate output enable signal so that polarity overlap between subframes on the display panel is minimized when N compensated subframe outputs.

The timing controller controls the polarity conversion rule between the first and second compensation subframes provided when the mode is changed from the low-speed drive mode to the high-speed drive mode and the first and second compensation subframes provided when the high- The polarity conversion rule may be different.

In the low speed driving mode, only the (N + 1) th and (N + 2) th gate lines and the corresponding pair of gate lines are driven during the first frame in order to omit the output of the gate pulse with respect to 1/2 of the gate lines of the display panel Skip driving for driving only the (N + 3) th and (N + 4) th gate lines and the corresponding pair of gate lines during the second frame, and for all the gate lines of the display panel in the high- And a 1/4 skip drive for skipping the output of the gate pulse for 1/4 of the gate lines of the display panel can be performed in the transient period between the low-speed driving mode and the high-speed driving mode.

The timing controller can change the gate output enable signal once to the opposite polarity so that the polarity of the corresponding line is reversed during the first and second compensating subframe periods when the last polarity of the low speed driving mode and the first operating polarity of the high speed driving mode are the same can do.

The timing controller changes the gate output enable signal to the opposite polarity so that the polarity of the line is reversed during the first compensation subframe period when the last polarity of the low speed drive mode is different from the first operation polarity of the high speed drive mode, The gate output enable signal may be changed to the opposite polarity so that the polarity of the corresponding line during the compensating sub-frame period is opposite to that of the first compensating sub-frame period.

In another aspect, the present invention provides a method of driving a liquid crystal display. A method of driving a liquid crystal display, comprising: detecting whether a driving frequency of a display panel is variable; providing N compensating subframes in a first mode when the driving frequency is switched from a low driving mode to a high driving mode; Frame is switched from the high-speed driving mode to the low-speed driving mode, the N compensation sub-frames are provided in a second scheme different from the first scheme.

In the low-speed driving mode, one frame is divided into an odd-numbered frame and an even-numbered frame in order to omit the output of the gate pulse for 1/2 of the gate lines of the display panel, N + 1 and N + 2 gate lines and corresponding pairs of gate lines, and for the second selected one of the odd and even frames, the (N + 3) th and (N + 4) In the high-speed driving mode, gate pulses are output to all the gate lines of the display panel. In the transition period between the low-speed driving mode and the high-speed driving mode, gate lines It is possible to perform the 1/4 skip drive for omitting the output of the gate pulse with respect to 1/4 of the drive pulses.

The present invention has the effect of reducing the power consumption when implementing a liquid crystal display device having a UHD resolution and reducing the heat of the data driver (Source D-IC). In addition, the present invention has the effect of preventing and improving the noise of the glitch type on the display panel when the frequency is changed for changing the drive mode, thereby improving the display quality. In addition, the present invention has an effect that a line memory can be used or can be used in an unused state.

1 is a schematic block diagram of a liquid crystal display according to an embodiment of the present invention;
2 is an exemplary layout of a pixel array;
3 is a view showing output characteristics of a gate pulse according to a conventional driving method.
4 is a view showing a charging characteristic of a data voltage according to a conventional driving method;
5 is a view for explaining a problem that occurs when a liquid crystal display device having a UHD resolution is driven by a conventional driving method.
FIG. 6 illustrates output characteristics of a gate pulse according to an embodiment of the present invention; FIG.
FIG. 7 illustrates charging characteristics of a data voltage according to an embodiment of the present invention. FIG.
8 is a diagram showing a configuration of a logic circuit for varying an output characteristic of a gate pulse.
9 is a waveform diagram of odd-numbered frames to compare a conventional driving method when the line memory is not used and a driving method according to the first embodiment of the present invention.
10 illustrates waveforms of odd and even frames to show a driving method according to the first embodiment of the present invention when the line memory is not used.
11 is a waveform diagram of an odd-numbered frame to compare a conventional driving method when using a line memory and a driving method according to a second embodiment of the present invention.
12 illustrates waveforms of odd and even frames to show a driving method according to a second embodiment of the present invention when using a line memory.
13 is an exemplary view showing a driving method according to an experimental example;
14 is a view showing a problem of a driving method according to an experimental example;
15 is an exemplary view schematically showing a driving method according to an embodiment of the present invention;
16 is a view showing an improvement of a driving method according to an embodiment of the present invention;
17 is a flowchart illustrating a driving method according to an embodiment of the present invention.
FIGS. 18 and 19 are exemplary diagrams for explaining a driving method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating an arrangement of a pixel array.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, a host system 14, .

The timing controller 11 receives the digital video data DATA of the input image from the host system 14 through a Low Voltage Differential Signaling (LVDS) interface method and outputs the digital video data DATA of the input video to the mini-LVDS And supplies it to the data driver 12 through the interface method.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14 Control signals for controlling the operation timings of the data driver 12 and the gate driver 13 are generated. The control signals include a gate timing control signal for controlling the operation timing of the gate driver 13 and a source timing control signal for controlling the operation timing of the data driver 12. [ The timing controller 11 time-divides one frame into a first sub-frame and a second sub-frame and variably outputs the gate timing control signal in consideration of the timing at which the data voltage is charged in the data lines DL.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is a signal for controlling the timing at which the first gate pulse (or scan pulse) is generated. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE is a signal for controlling the output of the gate driver 13.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE) And a sharing control signal (CSC). The source start pulse SSP is a signal for controlling the data sampling start timing of the data driver 12. [ The source sampling clock SSC is a clock signal for controlling sampling timing of data in the data driver 12 on the basis of the rising or falling edge. The polarity control signal POL is a signal for controlling the polarity of the data voltages sequentially output in each output channel of the data driver 12. [ The polarity control signal POL may be inverted in units of one frame period corresponding to the version in which the column is a version in which the column is a column, or may be inverted in N horizontal periods in response to a version method with a vertical N dot. The charge sharing control signal CSC is a signal used to short-circuit all of the output channels of the data driver 12 for a predetermined period.

The data driver 12 includes a shift register, a latch array, a digital-to-analog converter, an output circuit, and the like. The data driver 12 latches the digital video data DATA in accordance with the source timing control signal and then converts the latched data into analog positive / negative gamma compensation voltages, To data lines DL through a plurality of output channels. The data driver 12 inverts the polarities of the data voltages output from the respective output channels according to the column inversion method or the N dot inversion method according to the polarity control signal POL supplied from the timing controller 11. [

The gate driver 13 sequentially generates gate pulses according to the gate timing control signals set based on the charging timing of the data voltage, and then divides (or separates) the gate pulses according to a predetermined rule, and supplies the gate pulses to the gate lines. The shift register of the gate driver 13 may be formed directly on the lower substrate according to a gate-driver In Panel (GIP) scheme.

The display panel 10 includes a liquid crystal layer formed between two substrates. On the lower substrate of the display panel 10, a pixel array is formed. In the pixel array, a liquid crystal cell Clc (pixel) formed at the intersection of the data lines DL and the gate lines GL, TFTs connected to the pixel electrode 1 of the pixels, A common electrode 2 and a storage capacitor Cst. Each of the liquid crystal cells Clc is connected to a TFT (Thin Film Transistor) and driven by an electric field between the pixel electrode 1 and the common electrode 2.

On the upper substrate of the display panel 10, a black matrix, red, green, and blue color filters are formed. On the upper substrate and the lower substrate of the display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The common electrode 2 is formed on the upper substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. And is formed on the lower substrate together with the pixel electrode 1 in the horizontal electric field driving system. The display panel 10 may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode.

The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

As shown in FIG. 2, a liquid crystal display device according to an embodiment of the present invention is a method for reducing power consumption, and a connection structure of pixels can be designed by a Z-inversion method. In FIG. 2, D1 to D8 are a part of data lines to which a data voltage is supplied, and G1 to G4 are a part of gate lines to which a gate pulse is supplied. In the case of the Z inversion method, the pixels PIX of an odd line are connected to TFTs (Thin Film Transistors) so as to be adjacent to either the right side or the left side of the data line, and the pixels of even lines are connected to TFTs And adjacent to the other of the right and left sides of the data line.

Conventionally, in order to reduce the power consumption of the liquid crystal display device and to reduce the heat generation of the data driver (Source D-IC), only the odd gate lines are driven in the odd frame and only the even gate lines are driven in the even frame. A low-speed driving method has been proposed. The low-speed driving method lowers the driving frequency so that power consumption can be reduced while still images are displayed on the display panel. (In the present invention, the normal drive corresponding to the normal drive is expressed as high-speed drive in order to facilitate understanding since the drive frequency is faster than the low-speed drive.)

In addition, this method has been implemented in a 4-dot version (Dot Inversion) method in order to solve the problem of image quality such as vertical crosstalk as well as reduction of power consumption of a liquid crystal display device having a full high definition (FHD) resolution. However, when the above-described conventional method is directly applied to a liquid crystal display device having a UHD (Ultra High Definition) resolution, the following problems have arisen.

FIG. 3 is a view showing an output characteristic of a gate pulse according to a conventional driving method, FIG. 4 is a view showing a charging characteristic of a data voltage according to a conventional driving method, FIG. 5 is a graph illustrating a charging characteristic of a liquid crystal display Fig. 8 is a view for explaining a problem that occurs when the optical disc drive is driven.

As shown in FIGS. 3 and 4, in the conventional driving method, one frame is divided into odd-numbered frames and even-numbered frames, and only odd-numbered gate lines are driven during odd-numbered frames and only even-numbered gate lines are driven during even-numbered frames. That is, in the conventional driving method, a gate pulse is divided into one line by one line between subframes and outputted.

Specifically, gate pulses corresponding to the scan high are transmitted to the first, third, fifth and seventh gate lines G1, G3, G5 and G7 during odd-numbered frames (left side in FIG. 4) The gate pulse is skipped (skipped; skipped or skipped). On the contrary, gate pulses corresponding to the scan high are transmitted to the second, fourth, sixth and eighth gate lines G2, G4, G6 and G8 during the even-numbered frame (right side of FIG. 4) The pulse is skipped (skipped; skipped or skipped).

According to the above driving method, the first sub-frame divided by 1/2 and the second sub-frame are gathered to form one frame in the display panel. At this time, characteristics such as charging the data voltages by the dot inversion method of 4 dots for one frame are displayed on the display panel by the above driving method.

However, when the resolution of the display panel of the liquid crystal display device is increased to UHD, 1H (horizontal time) is decreased compared with FHD, and the charging time is reduced. Therefore, when a liquid crystal display device having UHD resolution is driven by the conventional driving method, ripple of common voltage (ripple due to increase of Vcom capacitance) becomes large as shown in FIG. As a result, not only the time for returning the common voltage to the normal level is delayed but also the charging characteristic is lowered.

In particular, when the conventional driving method is directly applied to a liquid crystal display device having a UHD resolution, a problem that a gate line in which a weak charge occurs and a gate line in which a strong charge occurs occur in two lines as shown in FIG. 4C A fine horizontal line appears on the liquid crystal panel due to the luminance deviation).

As a result of research to solve such a problem, it is considered that the following driving method is required for reducing the power consumption of the liquid crystal display device having UHD resolution and reducing the heat generation of the data driving unit.

FIG. 6 illustrates output characteristics of a gate pulse according to an exemplary embodiment of the present invention. FIG. 7 illustrates charging characteristics of a data voltage according to an exemplary embodiment of the present invention. Referring to FIG.

As shown in FIGS. 6 and 7, an embodiment of the present invention drives one frame by dividing it into an odd frame and an even frame. Further, an embodiment of the present invention may be applied to (N + 1) th and (N + 2) th gate lines and corresponding thereto during a selected first frame among odd and even frames (hereinafter, it is defined as an odd frame but may be an even frame) (N + 3) th and (N + 4) -th gate lines during a second frame (hereinafter, it may be an odd frame) of a selected one of odd and even frames Driving only the corresponding pair of gate lines. That is, one embodiment of the present invention outputs gate pulses in two lines by two lines between subframes.

Specifically, the N + 1 and N + 2 gate lines G1 and G2 and the N + 5 and N + 6 gate lines G5 and G6 (hereinafter referred to as gate lines Gate lines G3 and G4 and the (N + 7) th and (N + 8) th gate lines G7 and G8 (hereinafter referred to as &quot; Gate lines are omitted), the gate pulse is not transferred (skipped) (skipped or skipped). On the other hand, the N + 3 and N + 4 gate lines G3 and G4, the N + 7 and N + 8 gate lines G7 and G8 The gate pulses corresponding to the scan high are transferred to the (N + 1) th and (N + 2) th gate lines G1 and G2, Line omitted), the gate pulse is not transferred (skipped) (skipped or skipped).

According to the above driving method, the first sub-frame divided by 1/2 and the second sub-frame are gathered to form one frame in the display panel. At this time, the data driver outputs the data voltages in a 4-dot version (Dot Inversion) method, but the same characteristics as those in which the data voltages are charged in the vertical 2 dot inversion .

As a result, when a liquid crystal display device having a UHD resolution is driven by a driving method according to an embodiment of the present invention, a gate line in which approximately charging is performed and a gate line in which strong charging occurs are arranged in a line It is possible to improve (alleviate) the problem of luminance deviation compared to the conventional driving method. That is, the embodiment of the present invention can maintain the image quality of the same level as the vertical 2-dot version by distributing the charged regions at intervals of two lines.

On the other hand, as shown in FIG. 7A, approximately charge is generated in the (N-1) th gate line (the uppermost gate line in the drawing) during the first frame corresponding to the odd numbered frame, Lt; / RTI &gt; In this manner, the weak charge during the first frame (first field) also occurs in the N + 3 gate line located under the fourth line from the (N-1) th gate line. Also, strong charging during the first field (1st field) occurs also in the N + 4 gate line located four lines from the Nth gate line.

As shown in FIG. 7 (b), during the second frame corresponding to the even-numbered frame, about charge is generated in the (N + 1) -th gate line and strong charge is generated in the (N + 2) -th gate line. In this manner, the weak charge during the second frame (2nd Field) also occurs on the (N + 5) th gate line located below the fourth line from the (N + 1) th gate line. Also, strong charging during the second frame (2nd field) occurs in the N + 6 gate lines located under the fourth line from the (N + 2) th gate line.

As a result, as shown in (c) of FIG. 7, the gate line in which the charge is about to occur during one frame (1 frame) including the first and second frames (1st field and 2nd field) It occurs alternately for each line.

In addition, in the conventional driving method, since the gate lines in which the charge and the strong charge occur are alternately generated in every two lines during one frame, the fine horizontal lines appear in the form of a thick line. On the other hand, in the driving method according to an embodiment of the present invention, since the gate lines in which the filling and the strong charging occur are alternately generated for one line during one frame, the fine horizontal lines appear in a weak line form. Therefore, by driving a liquid crystal display device having a UHD resolution by a driving method according to an embodiment of the present invention, it is possible to improve (mitigate) a problem that a fine horizontal line appears compared with a conventional driving method.

In order to implement the driving method of the embodiment of the present invention, the polarity of the data voltage for changing the frequency of the variable signal can be changed by changing the timing of the driving signal depending on whether the line memory is used or not.

FIG. 8 is a diagram showing the configuration of a logic circuit for varying the output characteristics of gate pulses. FIG. 9 is a diagram showing the structure of a logic circuit for varying the output characteristics of an odd-numbered frame in order to compare the driving method according to the first embodiment of the present invention, FIG. 10 is a diagram illustrating waveforms of odd and even frames to show a driving method according to the first embodiment of the present invention when the line memory is not used. FIG. 12 shows waveforms of odd and even frames in order to show the driving method according to the second embodiment of the present invention when the line memory is used. Fig. 12 shows waveforms of odd and even frames in order to compare the driving method according to the second embodiment of the present invention. Fig.

8, the first stage of the gate driver includes a flip-flop circuit FF and a flip-flop circuit FF which operate according to the gate start pulse GSP and the gate shift clock GSC to generate an output signal, (AND) for masking the output signal of the gate driver G1 with the gate output enable signal GOE and outputting the gate pulse GK.

The liquid crystal display according to an embodiment of the present invention uses a logic circuit shown in FIG. 8 so as to separately output gate pulses in two lines by two lines between subframes, The stage may be constructed, but is not limited thereto.

On the other hand, in the case of the gate driver shown in FIG. 8, the output of the gate pulse is varied in accordance with the logic state (configuration of the pulse) of the gate output enable signal GOE. Therefore, the gate output enable signal GOE and the gate start pulse GSP can use one signal or two signals depending on whether the line memory is used or not. Hereinafter, an embodiment for understanding the above description will be described.

[Line memory unused reference timing]

9A and 9B, the driving method according to the first embodiment of the present invention (FIG. 9B) differs from the conventional driving method (FIG. 9A) (GSP). The manner of using the line memory unused must change the gate output enable signal GOE to enable interlace operation.

10, the driving method according to the first exemplary embodiment of the present invention transfers gate pulses to the first and second gate lines G1 and G2 during odd frame timing, (Or variable) the gate output enable signal GOE to transfer gate pulses to the third and fourth gate lines G3 and G4 during even frame timing.

For example, during odd frame timing, the gate output enable signal GOE changes from a logic high to a logic low corresponding to gate pulse output times of the first and second gate lines G1 and G2. During the Even Frame Timing, the gate output enable signal GOE is changed from a logic high to a logic low corresponding to gate pulse output times of the third and fourth gate lines G3 and G4. This method enables interlace operation in the form of a two line by two line between subframes by varying the gate output enable signal GOE.

[Line Memory Usage Timing]

As shown in FIG. 11, the driving method according to the second embodiment of the present invention (FIG. 11B) needs to vary the gate shift clock GSC with respect to the conventional driving method (FIG. The method using the line memory may improve the luminance by increasing the gate on timing during interlace driving.

12, the driving method according to the second exemplary embodiment of the present invention transfers gate pulses to the first and second gate lines G1 and G2 during odd frame timing, (Or variable) the gate output enable signal GOE to transfer gate pulses to the third and fourth gate lines G3 and G4 during even frame timing.

For example, during odd frame timing, the gate output enable signal GOE changes from a logic high to a logic low corresponding to gate pulse output times of the first and second gate lines G1 and G2. During the Even Frame Timing, the gate output enable signal GOE is changed from a logic high to a logic low corresponding to gate pulse output times of the third and fourth gate lines G3 and G4.

This method enables interlace operation in the form of a two line by two line between subframes by varying the gate output enable signal GOE. This method outputs the data signal input during the odd frame timing and fetches the data signal stored in the line memory during the even frame timing and outputs the data signal.

[Comparison of First and Second Embodiments]

When the line memory is not used as in the first embodiment, since charging is performed immediately after the gate shift clock GSC and the gate start pulse GSP are varied, the voltage charging characteristic may be somewhat lowered. On the other hand, in the case of using the line memory as in the second embodiment, since the gate shift clock GSC is varied and the charge is generated when the 1 H (horizontal time) delay occurs, the voltage charging characteristic can be improved have.

Therefore, the present invention can be implemented in one of a mode using a line memory or a mode using no line memory according to the configuration, response characteristic, charging characteristic, etc. of the liquid crystal display device.

Meanwhile, if the driving frequency is variable (low speed < - > high speed) while driving the liquid crystal display device in the same manner as the embodiment of the present invention, a glitch (Display quality deterioration) may occur. An embodiment of the present invention prevents and improves the problem of generating a glitch-like noise on a display panel when a liquid crystal display having a UHD resolution is implemented.

FIG. 13 is a view illustrating an example of a driving method according to an experimental example, FIG. 14 is a view showing a problem of a driving method according to an experimental example, FIG. 15 is a drawing schematically illustrating a driving method according to an embodiment of the present invention And FIG. 16 is a view showing an improvement of a driving method according to an embodiment of the present invention.

As shown in FIGS. 13 and 14, when the driving frequency is changed to a low speed (for example, 30 Hz) and a high speed (for example, 60 Hz) by using the driving method according to the experimental example, the number of gate skip lines changes instantaneously do.

For example, when the driving frequency is changed from the low-speed driving mode to the high-speed driving mode, all the gate lines are driven while half skipping driving is performed on the gate line side. On the other hand, if the driving frequency is changed in the high-speed driving mode to the low-speed driving mode, all the gate lines are driven on the gate line side, and then half skip driving is performed.

As described above, in the low-speed driving mode, in order to omit the output of the gate pulse with respect to 1/2 of the gate lines of the display panel, the (N + 1) th and (N + Gate driving only for the (N + 3) th and (N + 4) th gate lines and the corresponding pair of gate lines during the even-numbered frame. In the high-speed driving mode, gate pulses are output to all the gate lines of the display panel. In the transition period between the low-speed driving mode and the high-speed driving mode, 1/4 skip driving is performed to omit the gate pulse output for 1/4 of the gate lines of the display panel.

In the case of the 1/4 skip driving, only the gate lines of the (N + 1) th to N + J (J is an integer of 8 or more) gate lines and the corresponding pairs of gate lines are driven similarly to the 1/2 skip driving, N + K (K is a number equal to or greater than J) and N + R (R is a number equal to or greater than K + 8) and a corresponding pair of gate lines. In the case of 1/2 skip drive and 1/4 skip drive, the position where the gate pulse is outputted differs from the position where the gate pulse is not outputted and the skip position is changed according to the number of gate lines, that is, the resolution.

It has been found that the sustain period (polarity overlap) of the same polarity is repeated in 3 to 4 sub-frames in some gate lines by such a driving method. In the driving method according to the experimental example, a glitch-type noise instantly occurs on the display panel when the frequency is varied for changing the driving mode. As a result of repeating the experiment to solve this problem, the following embodiment can prevent and improve this problem.

As shown in FIGS. 15 and 16, in the driving method according to the embodiment of the present invention, when the driving frequency is varied to a low speed (for example, 30 Hz) and a high speed (for example, 60 Hz) N (where N is an integer equal to or greater than one) compensating sub-frames.

The inserting of the compensating sub-frame is performed by the timing controller, and the timing of the operation of the timing signal (for example, the gate output enable signal or the like) for controlling the gate driver is varied depending on whether or not the line memory is interlocked with the timing controller.

On the other hand, the N compensating subframes inserted during the transitional period may be composed of two compensating subframes. And the polarity conversion rule between two compensation subframes provided when the low speed drive mode is converted to the high speed drive mode and the polarity change rules between the two compensation subframes provided when the high speed drive mode is converted to the low speed drive mode are different.

If the driving frequency is changed from the low-speed driving mode to the high-speed driving mode, the half-skipping driving is performed, and the 1/4 skip driving is performed during the first and second compensation sub-frames. . If the driving frequency is changed from the high-speed driving mode to the low-speed driving mode, all the gate lines are driven, then the 1/4 skip driving is performed during the first and second compensation sub-frames, .

According to such a driving method, it has been found that even when a sustain time (polarity overlap) of the same polarity appears in some gate lines, only a maximum of two sub-frames are repeated. That is, since the glitch-type noise hardly occurs on the display panel when the frequency is changed for the driving mode change, the driving method according to the embodiment of the present invention can prevent and improve the problems in the experimental example. As a result of inserting the compensating subframe during the variable interval of the frequency, the polarity repetition is minimized and the number of gate skip lines is sequentially changed to smooth the screen switching.

FIG. 17 is a flow chart for explaining a driving method according to an embodiment of the present invention, and FIGS. 18 and 19 are illustrations for specifically explaining a driving method according to an embodiment of the present invention.

As shown in FIG. 17, the driving method according to an embodiment of the present invention is different from the compensation method when switching from the low-speed driving mode to the high-speed driving mode and the compensation method when switching from the high- Do.

First, whether or not the driving frequency is variable is detected (S110). If there is no variable of the driving frequency (N), the device continuously detects whether the driving frequency is variable or not.

Alternatively, if the drive frequency is variable (Y), the device determines whether the variable drive frequency is switched from a low speed (AHz; example 30 Hz) drive mode to a high speed (AHz; If it is not switched from the low-speed drive mode to the high-speed drive mode (N), the device re-determines whether the high-speed drive mode is the low-speed drive mode (S150).

Alternatively, when the variable of the driving frequency is switched from the low-speed driving mode to the high-speed driving mode (Y), the device provides N compensation subframes in the first manner. In addition, after performing the ½ skip drive corresponding to the low speed drive mode, the 1/4 skip drive is performed during the compensation sub-frame, and then all the gate lines are driven while the high speed drive mode is performed (S130).

Thereafter, it is detected whether the driving frequency is variable (S140). If there is no variable of the driving frequency (N), the device continuously detects whether the driving frequency is variable or not.

Alternatively, if the drive frequency is variable (Y), the apparatus determines whether the variable of the drive frequency is switched from the high-speed drive mode to the low-speed drive mode (S150). If the high-speed drive mode is not switched to the low-speed drive mode (N), the device re-determines whether the low-speed drive mode is the high-speed drive mode (S120).

Alternatively, when the variable of the drive frequency is switched from the high-speed drive mode to the low-speed drive mode (Y), the device provides N compensation subframes in a second manner. Then, all the gate lines corresponding to the high-speed driving mode are driven, and then the 1/4 skip driving is performed during the compensation sub-frame, and then the low-speed driving mode is performed while the 1/2 skip driving is performed (S160).

As shown in FIG. 18, when the driving frequency is changed from the low-speed driving mode to the high-speed driving mode, the operation of inserting the compensating sub-frame according to the following rule is performed. According to this rule, even when the subframe in which the last operation is determined is in the front of 2 subframes (1F), the time during which the same polarity is maintained becomes the two subframes 1F and 2F.

In the case of the line having the same polarity as the last polarity of the low-speed drive mode and the first operation polarity of the high-speed drive mode, the gate output enable signal GOE is once changed to the opposite polarity during the inserted compensating subframe period. At this time, the first compensating sub-frame 3F is provided in a polarity opposite to that of the pre-charging sub-frame 1F, and the second compensating sub-frame 4F is provided in a polarity opposite to that of the first compensating sub- do.

a) When operating in the low speed drive mode before the polarity conversion 2 subframe (at 1F): The gate output enable signal GOE in the first inserted first compensation subframe 3F is set so that the polarity of the corresponding line is reversed Lt; / RTI &gt; Thus, when a polarity transition appears before two subframes with respect to the compensation subframe, a gate pulse is applied to the corresponding gate line of the first compensation subframe 3F, while a gate pulse is applied to the second compensation subframe 4F The gate pulse is skipped.

b) When operating in the low speed drive mode in front of the polarity conversion 1 subframe (at 2F): The gate output enable signal GOE in the second compensating subframe 4F to be inserted so that the polarity of the corresponding line is reversed Lt; / RTI &gt; Thus, when a polarity transition appears before one sub-frame with respect to the compensating sub-frame, a gate pulse is applied to the corresponding gate line of the second compensating sub-frame 4F, while a gate pulse is applied to the first compensating sub- The gate pulse is skipped.

(B) In the case of the line having the last polarity of the low-speed drive mode and the first operation polarity of the high-speed drive mode being different, the gate output enable signal GOE changes to the opposite polarity during the first compensation subframe (3F). Then, during the second compensation sub-frame 4F, the gate output enable signal GOE again changes to the opposite polarity. At this time, the first compensation sub-frame 3F is provided in the polarity opposite to the previous last sub-frame 2F, and the second compensation sub-frame 4F is provided in the polarity opposite to the first compensation sub-frame 3F do.

As shown in FIG. 19, when the driving frequency is changed from the high-speed driving mode to the low-speed driving mode, the operation of inserting the compensating sub-frame according to the following rule is performed. According to this rule, even if the subframe that controls the start operation is after two subframes (6F), the time during which the same polarity is maintained becomes two subframes (4F, 5F).

In the case of a line having the same polarity as the last polarity of the high-speed driving mode and the first operating polarity of the low-speed driving mode, the gate output enable signal GOE is once changed to the opposite polarity during the inserted compensating subframe period. At this time, the first and second compensating sub-frames 3F and 4F are provided in the opposite polarity to the previous sub-frame 2F.

(5F) in the first subframe after polarity conversion: the gate output enable signal (GOE) in the first inserted first compensation subframe (3F) is set such that the polarity of the corresponding line is reversed Lt; / RTI &gt;

(6F) in the second subframe after polarity conversion: In the second compensating subframe (4F) inserted in the second time, the gate output enable signal GOE has the polarity of the corresponding line reversely charged Respectively.

(B) In the case where the last polarity of the high-speed driving mode is different from the first operating polarity of the low-speed driving mode, the gate output enable signal GOE changes to the opposite polarity during the first compensating sub-frame 3F. Then, during the second compensation sub-frame 4F, the gate output enable signal GOE again changes to the opposite polarity. At this time, the first compensation sub-frame 3F is provided in the polarity opposite to the previous sub-frame 2F, and the second compensation sub-frame 4F is provided in the polarity opposite to the first compensation sub-frame 3F.

According to an embodiment of the present invention, a liquid crystal display device is implemented so as to perform vertical 4 dot inversion driving in a low speed driving mode and vertical 2 dot inversion in a high speed driving mode do.

By operating in accordance with the above rules, even if the polarity start position changes during frequency conversion, 1/4 skip drive (3/4 line operation) enables operation for solving the previously found problem. If the polarities of the compensating sub-frames are different, the compensating sub-frames are operated twice (1/2 line operation). If the polarities are the same, only one compensating sub-frame is operated 1/4 &lt; / RTI &gt; line operation).

As described above, the present invention has the effect of reducing the power consumption of the liquid crystal display device having a UHD resolution and reducing the heat of the data driver (Source D-IC). In addition, the present invention has the effect of preventing and improving the noise of the glitch type on the display panel when the frequency is changed for changing the drive mode, thereby improving the display quality. In addition, the present invention has an effect that a line memory can be used or can be used in an unused state.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

10: Display panel 11: Timing controller
12: Data driver 13: Gate driver
14: Host system

Claims (10)

A display panel for displaying an image;
A gate driver for supplying a gate pulse to the display panel;
A data driver for supplying a data voltage to the display panel; And
And a timing controller for controlling the gate driver and the data driver such that a driving frequency of the display panel is selectively variable between a low-speed drive mode and a high-
The timing controller outputs one frame in an odd-numbered frame and an even-numbered frame in a time-division manner, outputs N + 1 and N + 2 gate lines during a first frame of the odd and even frames, And controls only the gate driver to drive only the (N + 3) th and (N + 4) th gate lines and the corresponding pair of gate lines during the second selected one of the odd and even frames. The method according to claim 1,
The display panel
When operating in the low-speed drive mode,
During the first frame, about charge is generated in the (N-1) th gate line and a strong charge occurs in the (N) th gate line,
Charge is generated in the (N + 1) -th gate line during the second frame and strong charging occurs in the (N + 2) -th gate line,
Wherein a gate line in which a charge is performed and a gate line in which a strong charge is generated are generated alternately for every one line during the one frame including the first and second frames. The method according to claim 1,
The timing controller
And outputs N compensating sub-frames (N is an integer equal to or greater than 1) during a transition period in which the driving frequency of the display panel is variable. The method of claim 3,
The timing controller
Wherein the gate output enable signal is varied so that polarity overlap between subframes on the display panel is minimized when the N compensating subframes are outputted. The method of claim 3,
The timing controller
A polarity conversion rule between first and second compensation subframes provided when the mode is changed from the low-speed drive mode to the high-speed drive mode and first and second compensation sub-frames provided when the high- Wherein the polarity conversion rule between frames is different. The method according to claim 1,
In the low-speed driving mode, the (N + 1) th and (N + 2) th gate lines during the first frame and the corresponding pairs of gate lines during the first frame are omitted in order to omit the output of gate pulses for 1/2 of the gate lines of the display panel. Line drive for driving only the (N + 3) th and (N + 4) th gate lines and the corresponding pair of gate lines during the second frame,
A gate pulse is output to all the gate lines of the display panel in the high-speed driving mode,
And a 1/4 skip drive for skipping the output of gate pulses for 1/4 of the gate lines of the display panel during a transitional period between the low-speed driving mode and the high-speed driving mode. 6. The method of claim 5,
The timing controller
When the last polarity of the low-speed driving mode is equal to the first operating polarity of the high-speed driving mode, the gate output enable signal is changed once in the opposite polarity so that the polarity of the corresponding line is reversed during the first and second compensating sub- . 6. The method of claim 5,
The timing controller
When the last polarity of the low-speed drive mode is different from the first operation polarity of the high-speed drive mode, the gate output enable signal is changed to the opposite polarity so that the polarity of the corresponding line is reversed during the first compensation sub- And the gate output enable signal is changed to the opposite polarity so that the polarity of the corresponding line is opposite to the first compensating sub-frame period during the second compensating sub-frame period. Detecting whether the driving frequency of the display panel is variable or not;
Providing N compensating subframes in a first manner when the driving frequency is switched from a low speed driving mode to a high speed driving mode; And
And providing N compensation subframes in a second mode different from the first mode when the driving frequency is switched from the high-speed driving mode to the low-speed driving mode. 10. The method of claim 9,
In the low-speed driving mode, one frame is divided into odd-numbered frames and even-numbered frames in order to omit the output of gate pulses for 1/2 of the gate lines of the display panel, And driving only the (N + 1) th and (N + 2) th gate lines and the corresponding pair of gate lines during the frame, and driving the N + 3 and N + 4 gate lines during the selected second frame of the odd and even frames, Skip driving is performed to drive only the corresponding gate line,
A gate pulse is output to all the gate lines of the display panel in the high-speed driving mode,
And skipping the output of gate pulses for 1/4 of the gate lines of the display panel in a transitional period between the low-speed drive mode and the high-speed drive mode.

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