KR20160098757A - Embedded System and error recovery method thereof - Google Patents

Abstract

The present invention relates to an embedded system and a method for repairing error therein, which employ error correction and synchronization restoration methods based on triple modular redundancy and partial reconfiguration, thereby enabling high reliability of a sequential circuit. The embedded system comprises: memory; a processor which includes a plurality of cores individually processing assigned tasks; a memory controller which is disposed between the memory and the processor, and is responsible for data transmission between the memory and the processor; a peripheral device which is connected to the processor via an on-chip peripheral bus (OPB), and supports task processing operation of the processor; an input/output port which is connected to the processor via the on-chip peripheral bus, and is responsible for communication with an external device; and a first error processing unit which is disposed between the memory controller and the processor, detects error in the processor, and stores register information about the cores in the memory.

Description

[0001] Embedded system and error recovery method [

The present invention relates to an embedded system and an error recovery method thereof, and more particularly, to an embedded system capable of achieving high reliability in an order circuit by using error correction and synchronous recovery by triple redundancy and partial reconfiguration, ≪ / RTI >

With the miniaturization of CMOS processes, high integration and high performance of system-on-chip (SoC) have been achieved. As a result, reconfigurable SRAM type FPGAs are attracting attention as new mass-production devices. In addition, by implementing an embedded processor core in the FPGA, system management can be performed, thereby reducing the cost of system construction.

However, SRAM type FPGAs may cause circuit malfunction by SEU (Single Event Upset). SEU is a soft error in which the value of memory or Flip-Flop is reversed due to the effects of radiation or neutrons.

In FPGA, circuit configuration information is stored in configuration memory. Therefore, when an SEU occurs in the FPGA, there is a possibility that the circuit information mounted in the configuration memory is inadvertently changed.

Until recently, the frequency of occurrence of SEU was low at the ground level, and SEU was considered only in the automotive and space application fields where the error is serious. However, as the miniaturization of the LSI progresses and the threshold voltage of the transistor is lowered, it can be considered that the influence of the SEU is surfaced at the ground level.

Moreover, SEU is an area where reliability is an important issue, such as automotive electronics systems and social infrastructure systems, which is why FPGAs are not deployed. Because of this, the importance of high reliability of FPGA is increasing.

A typical high reliability method of an FPGA is the Triple Modular Redundancy (TMR). TMR is a method of triple redundant circuitry to take the majority of outputs, which can hide errors in one circuit.

In combinational circuits, high reliability can be achieved by air correction using air concealment and reconfiguration by TMR. In particular, by using partial reconfiguration, errors can be corrected without stopping the operation of the system.

However, currently available error correction methods initialize circuit information at the time of reconfiguration, so even Flip-Flops and register information are initialized. Therefore, it is difficult to achieve high reliability for a sequential circuit including a processor. It is impossible to recover the operation because the internal state does not coincide with the TMR and partial reconfiguration of the order circuit.

When the entire circuit is reconfigured, in addition to the reconfiguration processing, it is necessary to store the register information in the external FPGA, and to restore the reconfiguration.

Errors affecting FPGA devices include soft errors and hard errors. Hard errors are physical breaks such as wire breaks, while soft errors are SEUs that cause a 1-bit inversion in memory or Flip-Flop.

Radiation or neutrons collide with the silicon causing charge drift that disturbs the transistor's current. This noise causes the SEU to exceed the threshold voltage of the transistor. For this reason, as the threshold voltage of the transistor is lowered due to miniaturization of the integrated circuit line width, SEU generation is expected to increase.

For ASICs, the influence of SEU is temporary because the circuit configuration is fixed. Storage memory will be permanently affected, but it can be handled by ECC (Error Correcting Code). However, since the FPGA stores the circuit configuration information in the SRAM, it can be seriously affected by the SEU.

Errors occurring in the FPGA by the SEU can be classified into transient error and permanent error depending on the location where they occur. Transient errors are errors that occur in flip-flops or latches and affect the output. The effect is temporary unless feedback of the output is performed. However, Permanent error causes malfunction by changing circuit configuration or executable program, and the effect is permanent.

For this reason, it is necessary to cope with the internal memory of FPGA by ECC like ASIC, and error correction by reconfiguration is necessary for configuration memory.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a method and apparatus for high reliability in an order circuit by using an error correction method and a synchronous recovery method by triple redundancy and partial reconfiguration And an error recovery method for the embedded system.

According to an aspect of the present invention, there is provided an embedded system including: a memory; A processor unit including a plurality of cores for individually processing tasks to be allocated; A memory controller located between the memory and the processor and responsible for data transfer between the memory and the processor; A peripheral unit connected to the processor unit via an on-chip peripheral bus (OPB) for assisting a task processing operation of the processor unit; An input / output port connected to the processor unit via the on-chip peripheral bus and configured to communicate with an external device; And a first error processing unit located between the memory controller and the processor unit, for detecting errors generated in the processor unit and storing register information for the plurality of cores in the memory.

Wherein the first error processing unit comprises: a first detection circuit for detecting an error generated in the processor unit; And a first majority circuit for storing an error detected in the first detection circuit and storing the register information transmitted from the plurality of cores in the memory.

The embedded system further includes a second error processing unit connected to the processor unit and the peripheral unit, and configured to detect and process an error generated in the processor unit.

Wherein the second error processing unit comprises: a second detection circuit for detecting an error generated in the processor unit; And a second majority circuit for hiding errors detected in the second detection circuit.

The embedded system further includes a third error processing unit connected between the input / output port and the peripheral device and detecting and processing an error generated in the processor unit.

Wherein the third error processing unit comprises: a third detecting circuit for detecting an error generated in the processor unit; And a third majority circuit that hides errors detected by the third detection circuit.

An error recovery method of an embedded system according to an embodiment of the present invention includes: processing a task to which a plurality of cores of a processor unit are allocated; Detecting whether an error occurs in processing the task by the plurality of cores; A step of partially reconstructing a core in which an error has occurred if it is determined that an error has occurred as a result of the determination in the step of detecting occurrence of the error; And generating an interrupt for all of the cores, and performing synchronization by sharing register information of a core that is operating normally.

At this time, the step of synchronizing includes: generating an interrupt to the plurality of cores; Storing register information of the plurality of cores in a memory; And registering information of a core that is normally operating among a plurality of register information stored in the memory, to be restored to all the cores, thereby synchronizing the cores.

According to the present invention, there is provided an embedded system and an error recovery method thereof that can achieve high reliability in an order circuit by using an error correction and synchronization recovery method based on triple redundancy and partial reconfiguration.

Therefore, it is possible to realize the low cost of the system by applying the FPGA which is one of the automotive electronic system and the social infrastructure system, which is regarded as reliable.

1 is a block diagram showing the configuration of an embedded system according to an embodiment of the present invention.
2 is a flowchart illustrating an error recovery operation of the embedded system according to an embodiment of the present invention.
3 is a state diagram illustrating an error recovery operation of the embedded system according to the embodiment of the present invention
4 is a flowchart illustrating a synchronization process of an embedded system according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like numbers refer to like elements throughout.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

There are two ways to make FPGA highly reliable: error mitigation and error correction. Error mitigation is a method that does not output an error to the outside by a redundancy circuit such as TMR or Duplication with Comparison (DWC). As a result, it is possible to take measures against transient errors.

Error correction is a method of correcting permanent error using reconstruction. Error correction by scrubbing or partial reconstruction using total reconstruction is used. Combination circuit (Combinational Circuit) can combine error mitigation and error correction to achieve high reliability. In particular, when the TMR and partial reconstruction are combined, the error can be corrected without stopping the operation of the system.

However, with respect to a sequential circuit, research on error mitigation is progressing, but error correction is not sufficient. In the case of the currently used reconfiguration method, reconfiguration is performed by initializing the circuit information. At this time, since the internal information of the sequential circuit is also initialized, a process of restoring to the state immediately before the occurrence of the error is also required. Even when using TMR and partial reconfiguration, the internal state of the reconfigured circuit is changed, so it is necessary to synchronize with the redundancy circuit.

The present invention focuses on the re-configurability feature of the FPGA, and performs error correction and synchronization recovery by TMR and partial reconfiguration. At this time, the synchronous recovery is realized by taking the majority of each register information using the FPGA internal memory, storing it in the memory, and returning it to the entire processor.

Hereinafter, an embedded system and an error recovery method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an embedded system according to an embodiment of the present invention. In this case, the configuration shown in FIG. 1 is an example in which the core is set as a partial reconfiguration area for error correction in the embedded processor core, and the SEU is generated.

1, an embedded system 100 according to an embodiment of the present invention includes a memory 110, a memory controller 120, a processor unit 130, a peripheral unit 140, an input / output port 150, 1 to the third error processing units 160, 170, and 180, respectively.

At this time, the embedded system 100 according to the present embodiment includes one memory controller, but may be configured to include a plurality of memory controllers. Accordingly, a plurality of the first error processing units may be configured.

The memory 110 stores data transmitted from the memory controller 120 and transmits data requested by the memory controller 120.

The memory controller 120 is located in the memory 110 and the processor unit 130 and stores data or requests data to the memory 110 under the control of the processor unit 130.

In this case, the memory controller 120 and the processor unit 130 are connected to each other through a local memory bus (LMB) to transmit and receive signals. In particular, the memory controller 120 and the processor unit 130 communicate data through a data local memory bus (DLMB) And sends and receives commands via an instruction local memory bus (ILMB).

The processor unit 130 includes a plurality of cores that individually process tasks to be allocated. According to the present embodiment, the processor unit 130 includes first to third cores 131, 132 and 133, The number of cores included in the unit 130 may vary depending on the system. Here, the first to third cores 131, 132 and 133 may be RISC types of the Harvard architecture.

The processor unit 130 stores data generated while processing a task in the memory 110 or reads data necessary for task processing from the memory 110. [

The processor unit 130 is connected to the memory controller 120 through a local memory bus (LMB) to transmit and receive signals, and transmits and receives signals to and from the peripheral device (OS) through an on-chip peripheral bus (OPB) And transmits and receives a signal.

The peripheral device unit 140 assists the task processing operation of the processor unit 130 or provides time information. The peripheral device unit 140 may be composed of various types of modules according to system specifications, In the example, it is assumed that the peripheral unit 140 includes a timer 141 and an on-chip peripheral bus (OPB) interrupt controller 142.

The processor unit 130 may include three cores 131, 132, and 133. The processor unit 130 may be configured to correspond to the number of cores included in the processor unit 130. In this embodiment, Therefore, the embedded system 100 according to the embodiment of the present invention is provided with three peripheral units 141, 142, and 143.

At this time, the peripheral device unit 140 is connected to the processor unit 130 via an on-chip peripheral bus (OPB) to transmit and receive signals.

The input / output port 150 is responsible for communication with devices outside the embedded system 100.

Each of the first to third error processing units 160, 170, and 180 includes a majority circuit and a detection circuit.

That is, the first error processing unit 160 includes a first majority circuit 161 and a first detection circuit 162. The second error processing unit 170 includes a second majority circuit 171 and a second detection circuit 162. [ Circuit 172 and the third error processing unit 180 includes a third majority circuit 181 and a third detection circuit 182. [

The first error processing unit 160 is connected between the memory controller 120 and the processor unit 130 and is connected to the processor unit 130 through a local memory bus (LMB).

The first majority circuit 161 of the first error processing unit 160 serves to hide the error and to reduce the memory consumption by sharing the memory 110.

Also, the first majority circuit 161 makes it possible to store the correct register information in the memory 110.

The second error processing unit 170 is connected between the processor unit 130 and the peripheral device unit 140 and is connected to the peripheral device unit 140 through an on-chip peripheral bus (OPB) Lt; / RTI >

The second majority circuit 171 of the second error processing unit 170 prevents the peripheral device unit 140 from being affected by an error even if an error occurs in the processor unit 130.

The third error processing unit 180 is connected between the input / output port 150 and an on-chip peripheral bus (OPB).

The third majority circuit 181 of the third error processing unit 180 is arranged to hide an error relating to the input / output port 150.

The first to third majority circuits 161, 171 and 181 function differently depending on the positions of the first to third majority circuits 161 to 171. The first to third detection circuits 162, And is configured to detect errors occurring in the cores 131, 132,

Here, the first to third majority circuits 161, 171 and 181 detect a place where an error has occurred and output a signal to perform a partial reconfiguration.

The logical expressions of the first to third detection circuits 162, 172, and 182 are as follows.

Here, R0, R1, and R2 are outputs from the triple redundancy module, and E0, E1, and E2 are signals indicating which module is in error.

In the foregoing, an embedded system according to an embodiment of the present invention has been described. Hereinafter, an error recovery operation of the embedded system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a flowchart illustrating an error recovery operation of an embedded system according to an embodiment of the present invention. FIG. 3 is a state diagram illustrating an error recovery operation of the embedded system according to an embodiment of the present invention.

Hereinafter, an error recovery operation of the embedded system according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3. It is assumed that an error has occurred in the third core 133. FIG.

First, as the embedded system operates, the multiple cores 131, 132, and 133 operate to process an allocated task (S210). At this time, it is assumed that the multiple cores (131, 132, 133) initially operate normally.

The detection circuits 162, 172, and 182 detect whether an error occurs in any core while the multiple cores 131, 132, and 133 are operating (S220).

If it is determined in step S220 that an error is not detected (S220-No), an error occurrence is continuously detected. If an error is detected in the third core 133 (S220-Yes) The detection circuit which has detected the error outputs the control signal for partial reconfiguration to the third core 133 in which the error has occurred to partially reconfigure (S230) (t2 in Fig. 3).

On the other hand, in step S230, partial reconfiguration is performed on the cores where an error has occurred, but the internal states among the cores are not synchronized.

After the partial reconfiguration is performed according to step S230, interrupts are generated in all the cores (t3 in FIG. 3), and the register information of the cores in normal operation is shared to perform synchronization (S240) (t4 in FIG. 3).

When all the cores are synchronized in accordance with step S240, all the cores perform normal operation.

Hereinafter, the synchronization process of the core according to step S240 will be described in more detail with reference to FIG.

4 is a flowchart illustrating a synchronization process of an embedded system according to an embodiment of the present invention.

Referring to FIG. 4, an interrupt is generated in each core (S241). At this time, the register information of the normally operating core receiving the interrupt is stored in the memory, but as the error occurs, the partially reconfigured core does not accept the interrupt and outputs a command for executing the start process. However, the startup process execution command output from the core is hidden by the majority circuit, and the register information storage instruction request is adopted from the cores where no error has occurred.

As a result, all the cores transmit the register information storage command to the memory (S242), and the synchronization on a command-by-command basis is completed at this point.

Then, the register information is read from all the cores and stored in the memory via the majority circuit (S243). At this time, the register information of the core that is operating normally is stored in the memory.

In step S243, the stored register information is restored to all cores (S244). Accordingly, the internal states between the cores are synchronized with each other, and the recovery processing and the synchronization processing for the cores where the errors occurred are ended.

According to the present invention, there is provided an embedded system and an error recovery method thereof that can achieve high reliability in an order circuit by using an error correction and synchronization recovery method based on triple redundancy and partial reconfiguration.

Therefore, it is possible to realize the low cost of the system by applying the FPGA which is one of the automotive electronic system and the social infrastructure system, which is regarded as reliable.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the scope of the invention is not limited to the disclosed embodiments, but, on the contrary, Various modifications, alterations, and alterations can be made within the scope of the present invention.

Therefore, the embodiments described in the present invention and the accompanying drawings are intended to illustrate rather than limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and accompanying drawings . The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

100: embedded system 110: memory
120: memory controller 130:
131, 132, 133: core 140:
141: Timer 142: OPB controller
150: input / output ports 160, 170, 180:
161, 171, 181: majority circuit 162, 172, 182: detection circuit

Claims (8)

Memory;
A processor unit including a plurality of cores for individually processing tasks to be allocated;
A memory controller located between the memory and the processor and responsible for data transfer between the memory and the processor;
A peripheral unit connected to the processor unit via an on-chip peripheral bus (OPB) for assisting a task processing operation of the processor unit;
An input / output port connected to the processor unit via the on-chip peripheral bus and configured to communicate with an external device; And
And a first error processing unit located between the memory controller and the processor unit, for detecting an error occurring in the processor unit and storing register information for the plurality of cores in the memory.
The method according to claim 1,
Wherein the first error processing unit comprises:
A first detection circuit for detecting an error generated in the processor unit; And
And a first majority circuit serving to hide an error detected by the first detection circuit and storing register information transmitted from the plurality of cores in the memory.
The method according to claim 1,
And a second error processing unit connected to the processor unit and the peripheral unit, for detecting and processing an error generated in the processor unit.
The method of claim 3,
And the second error processing unit,
A second detection circuit for detecting an error generated in the processor unit; And
And a second majority circuit for hiding errors detected in said second detection circuit.
The method according to claim 1,
And a third error processing unit connected between the input / output port and the peripheral device and detecting and processing an error generated in the processor unit.
6. The method of claim 5,
The third error processing unit,
A third detection circuit for detecting an error generated in the processor unit; And
And a third majority circuit that hides errors detected by the third detection circuit.
Processing a task to which a plurality of cores of a processor unit are assigned;
Detecting whether an error occurs in processing the task by the plurality of cores;
A step of partially reconstructing a core in which an error has occurred if it is determined that an error has occurred as a result of the determination in the step of detecting occurrence of the error; And
Generating an interrupt in all of the cores and performing synchronization by sharing register information of a core operating normally;
And an error recovery method for an embedded system.
8. The method of claim 7,
Wherein the step of synchronizing comprises:
Generating an interrupt in the plurality of cores;
Storing register information of the plurality of cores in a memory; And
Wherein the register information of a core that is normally operating among a plurality of register information stored in the memory is restored to all cores so that synchronization between the cores is performed.

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