KR20160083170A - Low voltage differential signaling system - Google Patents

Abstract

The present invention relates to a low voltage differential signaling system, and suggests an alignment method having compatibility which saves time by transmitting a data packet for alignment for correcting bit slip from one side of a receiver and a transmitter to the other side, by automatically calculating a bit slip value using the data packet for alignment, and by allowing the process of alignment to be automatically performed.

Description

{Low Voltage Differential Signaling System}

The present invention relates to low voltage differential signaling systems.

As the demand for high speed data generation and processing has increased recently, the ability to transmit data from one point to another has become a measure of overall system performance. As a solution for this high speed data transmission, a low voltage differential signal Voltage Differential Signal) method is used.

Generally, a low-voltage differential signaling system is an electrical signaling system that transmits two different voltages to a transmitter (LVDS) and a receiver to compare two voltage signals to recover data. That is, a low-voltage differential signaling system uses the voltage difference between two wires for information encoding.

Low-voltage differential signal transmitters transmit low-voltage differential signal (LVDS) data through a low-voltage differential signal cable (LVDS cable), so the amplitude of the signal (LVDS) is small and the two lines are well- , Electromagnetic noise and power consumption are small, and high-speed data transmission is possible.

Due to these advantages, the low voltage differential signaling method is applied to various fields such as data transmission between chips, as well as data transmission between boards.

When transferring data between boards using a low-voltage differential signaling method, the phase between the clock signals and the data between the boards is not constant for each board. Therefore, before the first board is set and data is transmitted for the first time, The data bit slip must be identified and corrected.

Conventionally, a separate equipment (JTAG: Joint Test Action Group) is connected to the board to detect the bit slip in the low voltage differential signaling system. The transmitter then transmits a specific pattern of data to identify the bit slip, and the experimenter directly verifies the waveform of the data received at the receiver through the instrument. Then, the bit slip value is grasped by repeatedly performing the correction process until the same pattern as the specific pattern transmitted from the transmitter is outputted. The bit slip value thus obtained is used to correct the data transmitted from the transmitter.

However, since the alignment process for correcting the bit slip using the apparatus is not only a correction process but also a pattern correction is performed until a bit slip value is found, a long time is required. Also, when the characteristics of the system change, the bit slip value is changed, for example, when the transmitter and the receiver are first connected, when the transmitter or receiver is changed in setting, or when the transmitter or receiver is replaced or repaired. That is, since the bit slip value between the hardware is incompatible, the experimenter must perform the bit slip correction process manually by connecting the equipment again, which is time consuming and troublesome.

It is an object of the present embodiments to provide a low-voltage differential signaling system capable of shortening the time required for the alignment process by automatically performing an alignment process for correcting bit slip.

It is an object of the present embodiments to provide a low-voltage differential signaling system capable of quickly and easily performing alignment by designing the bit slip alignment process to be compatible between hardware.

One embodiment includes a transmitter for transmitting an alignment data packet for correcting a bit slip to request alignment when a predetermined alignment condition is satisfied; And a receiver for receiving the alignment data packet and comparing the alignment data packet with information of an alignment data packet which is held in advance to calculate a bit slip value for alignment and recovering a data packet received from the transmitter according to the bit slip value Voltage differential signal system according to the present invention.

According to one embodiment of the present invention, in the present low-voltage differential signaling system, by automatically calculating the bit slip value, the time for calculating the bit slip value can be drastically reduced have.

According to an embodiment of the present invention, the bit slip value can be automatically calculated regardless of the hardware, so that the design method for alignment is compatible and the alignment can be performed quickly and easily.

1 is a block diagram of a low-voltage differential signaling system according to an embodiment of the present invention.
FIG. 2A is a graph sequentially showing signals of a lock packet, a key packet, and a blank packet, FIG. 2B is a graph showing a signal in which a lock packet, a key packet, and a blank packet are sequentially repeated two times FIG. 2 (c) is a graph showing a signal in which a lock packet, a key packet, and a blank packet are repeated twice, and FIG. 2 (d) Fig. 2 (e) is a graph illustrating an alignment data packet received at the receiver. Fig.
FIG. 3 is a diagram of a data packet showing a process of performing alignment in the alignment unit of FIG. 1. FIG.
Fig. 4 (a) is a graph of data packets before alignment performed on the receiver, and Fig. 4 (b) is a graph of data packets after alignment on the receiver.
5 is a block diagram of a low-voltage differential signaling system according to another embodiment of the present invention.
6 is a diagram illustrating a process of performing alignment in a low-voltage differential signaling system according to the present invention.
FIG. 7 (a) is a graph of data packets transmitted and received by the first transceiver of FIG. 6, and FIG. 7 (b) is a graph of data packets transmitted and received by the second transceiver of FIG.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."

1 is a block diagram of a low-voltage differential signaling system according to an embodiment of the present invention.

In the low voltage differential signal according to the present embodiment, the transmitter 10 and the receiver 30 share information about a specific data packet for correcting the bit slip of data, and the transmitter 10 When a specific data packet is transmitted, the receiver 30 restores a specific data packet and compares the specific data packet with previously stored information, thereby automatically generating a bit slip value for alignment of a data packet provided from the transmitter 10. [

The transmitter 10 according to the present embodiment can transmit the alignment data packet to the receiver 30 so as to automatically perform the alignment for correcting the bit slip of the data when the predetermined alignment condition is satisfied.

The transmitter 10 may include a serial converter 11, a clock generator 13, a data processor 15, and an alignment request unit 17. The predetermined alignment condition is a condition in which the transmitter 10 and the receiver 30 are connected to each other for the first time to transmit and receive data and when the settings of the transmitter 10 or the receiver 30 are changed, Such as a case in which the alignment member 30 is replaced or repaired. It goes without saying that addition and deletion of alignment conditions can be performed in addition to the above-described conditions.

The serializer 11 can generate serial data by serializing parallel data inputted from a plurality of channels by using a high-speed signal. That is, the serializer 11 converts the parallel data formed by 16 bits, 32 bits, etc. into serial data of 1 bit string. The serial converter 11 may be implemented as an FPGA (Field Programmable Gate Array).

When the serial data of one bit string is transmitted and the clock rates of the transmitter 10 and the receiver 30 are different from each other, overflow occurs in the buffer of the receiver 30 and data of several bits may be lost from one bit . This is referred to as a bit slip, and loss of data can be prevented by performing correction for shifting data by a bit at which the bit slip occurs in the receiver 30. [

The clock generating unit 13 can generate a reference clock signal which is transmitted together when the serial data is transmitted and used for synchronizing the serial data.

The data processing unit 15 transmits the serial data converted by the serial converting unit 11 and the reference clock signal from the clock generating unit 13 to the receiver 30. At this time, The serial data and the reference clock signal may be separately transmitted to the receiver 30 in accordance with the type of the clock recovery unit 33 on the side of the receiver 30 and the reference clock signal may be inserted into the serial data, (30).

One of a PLL (Phase Locked Loop) circuit and a CDR (Clock Data Recovery) circuit may be used as the clock recovery unit 33 on the receiver 30 side. When the PLL circuit is used, the data line for transmitting the serial data and the clock line for transmitting the reference clock signal are separately provided, so that the data processor 15 transmits the serial data through the data line, The clock signal can be transmitted. If the CDR circuit is used, an embedded clock line for transmitting the serial data and the reference clock signal at a time is provided, and the data processor 15 inserts the reference clock signal into the serial data to transmit the serial data and the reference clock signal to the receiver 30 through the embedded clock line. .

The alignment request unit 17 can transmit the alignment data packet to the receiver 30 so as to automatically calculate the number of bits to which the data should be shifted in order to prevent data loss due to bit slip.

The alignment data packet is formed of first to third alignment packets, wherein the first alignment packet is a Lock Packet, the second alignment packet is a Key Packet, and the third alignment packet is a Blank Packet ). In the following embodiments, the length of each packet is 8 bits, but the length of each packet is freely adjustable by a designer. In addition, the length of each packet may be the same length or may be formed to be different from each other.

FIG. 2A is a graph sequentially showing signals of a lock packet, a key packet, and a blank packet, FIG. 2B is a graph showing a signal in which a lock packet, a key packet, and a blank packet are sequentially repeated twice FIG. 2 (c) is a graph showing a signal in which a lock packet, a key packet, and a blank packet are repeated twice, and FIG. 2 (d) Fig. 2 (e) is a graph illustrating an alignment data packet received at the receiver. Fig.

The lock packet can be used for the purpose of enabling the receiver 30 to detect that the data packet for alignment has started to be transmitted. Accordingly, the lock packet can be formed such that all bits are 1, which is a high value, so as to be easily detected by the receiver 30, as shown in Fig. 2 (a). If the lock packet is formed with 8 bits, the lock packet has a value of 11111111. If the lock packet is formed of 16 bits, the lock packet has a value of 11111111 11111111.

The key packet may provide a key value for calculating the bit slip value to the receiver 30 that recognizes that the alignment process has been started by the lock packet. The receiver 30 may calculate the bit slip value using the number of bits shifted in the key packet by receiving the key packet.

2 (a), only one bit of all the bits is set to have a high value, so that the number of bits having a value of 1 in the receiver 30 is set to be a bit slip Value can be calculated.

If the key packet is formed of 8 bits, the key packet may have a value of 00000001, 00000010, 00000100, 00001000, or the like. However, values such as 10000000 and 01000000 are not suitable as key packets. Because all bits of the lock packet are 1, if the key packet is set to 10000000, it is difficult to distinguish between the lock packet and the key packet. Likewise, when the key packet is set to 01000000, if the value of 0 located at the head of the key packet can not be restored properly due to distortion in transmission of the data packet or the like, it becomes difficult to distinguish between the lock packet and the key packet.

On the other hand, one or more bits of the key packet may be set to a high value. For example, the key packet can be formed by 00010001 or 00000101 or the like. Also, even when the length of the key packet is formed to be 16 bits or so, several high values can be included in the key packet. For example, 16-bit key packets can be set to 00000001 00000001, 00010001 00010001, 00000101 00000101, and so on.

The blank packet is a packet for notifying the receiver 30 that the transmission of the key packet is completed and the process for alignment is completed. While the blank packet is being transmitted, the receiver 30 is able to calculate the bit slip value and prepare to receive the data packet from the transmitter 10.

The blank packet has a value of 00000000 as shown in FIG. 2 (a), in which all the bits are formed with a Low value of 0. The formation of all the bits of the blank packet in this manner is intended to make the distinction from the key packet clear.

On the other hand, the lock packet, the key packet, and the blank packet can be transmitted a plurality of times, respectively. At this time, the lock packet, the key packet, and the blank packet may be cyclically transmitted a plurality of times, or one packet may be transmitted a plurality of times, and then the next packet may be transmitted a plurality of times. Also, only a specific packet may be transmitted a plurality of times.

For example, it is possible to sequentially transmit a lock packet, a key packet, and a blank packet, and sequentially transmit a lock packet, a key packet, and a blank packet again. Then, as shown in FIG. 2 (b), packets can be transmitted in the order of lock packet → key packet → blank packet → lock packet → key packet → blank packet.

When a lock packet, a key packet, and a blank packet are transmitted a plurality of times each, as shown in Fig. 2 (c), packets are transmitted in the order of lock packet, lock packet, key packet, key packet, blank packet, Can be transmitted.

On the other hand, when a specific packet is transmitted a plurality of times, only a key packet serving as a key value for alignment can be continuously transmitted a plurality of times. That is, as shown in FIG. 2 (d), packets can be transmitted in the order of lock packet → key packet → key packet → blank packet.

When the alignment request unit 17 completes the generation of the alignment data packets, the data processor 15 inserts the reference clock signal into the alignment data packet and transmits it to the receiver 30. Then, when the bit slip value is calculated in the receiver 30, the data processor 15 inserts the reference clock signal into the serial data to be transmitted to the receiver 30 to form a data packet and transmit it to the receiver 30 have.

The receiver 30 according to the present embodiment can calculate the bit slip value using the data packets for alignment provided in the transmitter 10. [ To this end, the receiver 30 may include a parallel conversion unit 31, a clock recovery unit 33, an alignment calculation unit 35, and an alignment execution unit 37.

The parallel conversion unit 31 can convert the serial data converted by the serial conversion unit 11 of the transmitter 10 into parallel data using the reference clock signal. That is, the parallel conversion unit 31 restores 1-bit serial data into 16-bit or 32-bit parallel data.

The clock recovery unit 33 may recover the reference clock signal transmitted from the transmitter 10 and generate a recovery clock signal using the reference clock signal.

The clock recovery unit 33 may be a PLL circuit or a CDR circuit. When the clock recovery unit 33 is configured as a PLL circuit, the serial data and the reference clock signal are received through separate data lines and clock lines, so that the clock recovery unit 33 restores only the reference clock signal.

Generally, the PLL circuit may be composed of a phase detector, a voltage controlled oscillator (VCO), and a loop filter.

The phase detector can use an analog multiplier, an exclusive-OR gate, a flip-flop, etc., and can generate a voltage proportional to the phase difference between the input signal and the output signal. The VCO outputs a signal voltage having a frequency proportional to a voltage value input from the loop filter to the VCO, and the loop filter uses a low-pass filter or an integrator.

The clock recovery unit 33 receives the reference clock signal transmitted through the clock line as an input signal, and restores the reference clock signal to output a recovery clock signal.

When the clock recovery unit 33 is constituted by a CDR circuit, the serial data in which the reference clock signal is inserted is received from the transmitter 10. The clock recovery unit 33 separates the data and the reference clock signal, . Then, the clock recovery unit 33 correctly reconstructs the data by sampling the received data using the extracted reference clock signal as a recovery clock signal.

When the alignment data packet transmitted from the transmitter 10 is sampled in accordance with the recovery clock signal, the alignment calculation unit 35 can calculate the bit slip value using the lock packet, the key packet, and the blank packet. The alignment calculation unit 35 previously stores the values for the lock packet, the key packet, and the blank packet in a separate memory (not shown). Accordingly, when the lock packet, the key packet, and the blank packet are received, the alignment calculation unit 35 can judge how many bits are shifted compared with the lock packet, the key packet, and the blank packet which are held in advance .

For example, although a lock packet, a key packet, and a blank packet are sequentially transmitted from the transmitter 10 as shown in FIG. 2A, as shown in FIG. 2 (e), 111 00000001 00000000 11111 , The alignment calculation unit 35 can confirm that 00000001 is a key packet and determine 111, which is arranged in front of the key packet, as a lock packet. Accordingly, since the alignment calculation section 35 shifts 5 bits, it can be determined that bit slip is required five times. Thus, the alignment calculating section 35 calculates the bit slip value to be 5.

The alignment performing unit 37 aligns the data packet transmitted from the transmitter 10 using the bit slip value calculated by the alignment calculating unit 35 to thereby accurately restore the data packet from the transmitter 10 .

The alignment performing unit 37 may first receive a plurality of preset data packets and perform alignment by shifting a plurality of data packets according to the bit slip value. The number of data packets to be aligned at one time by the alignment performing unit 37 can be freely set by the designer in consideration of the length of the data packet, the communication speed, and the like.

For example, as shown in FIG. 3, when three data packet units are aligned, the alignment unit 37 receives three data packets and transmits the three data packets to the storage unit (not shown) ), And align three data packets. If the length of the data packet is 8 bits and the bit slip value is 5, the first data packet and the second data packet are delayed, and the third data is the current data. If the length of the data packet is 8 bits, the data window becomes 8 bits. Therefore, in order to align the data window with the delayed data, the alignment unit 37 shifts each data packet to the right by 5 bits.

A process of performing alignment in the low-voltage differential signaling system according to the present embodiment will now be described.

The alignment request section 17 of the transmitter 10 provides the lock packet to the data processing section 15 and the clock generation section 13 generates the reference clock signal and supplies the lock packet to the data processing section 15, . The data processor 15 inserts the reference clock signal into the lock packet and transmits it to the receiver 30.

The clock recovery unit 33 of the receiver 30 separates and restores the reference clock signal from the lock packet provided from the transmitter 10 to generate a recovery clock signal. The data of the lock packet is provided to the alignment calculating section 35. When the lock packet is received by the alignment calculating section 35, the alignment calculating section 35 counts the number of bits of the received lock packet.

The alignment request unit 17 of the transmitter 10 provides the key packet to the data processing unit 15 following the lock packet and the data processing unit 15 inserts the reference clock signal into the key packet and transmits it to the receiver 30 .

The clock recovery unit 33 of the receiver 30 generates a recovery clock signal from the key packet, and the alignment calculation unit 35 determines how many bits the High signal is located in the key packet.

The alignment request unit 17 of the transmitter 10 finally supplies the blank packet to the data processor 15 and the data processor 15 inserts the reference clock signal into the blank packet and transmits it to the receiver 30.

The clock recovery unit 33 of the receiver 30 generates a recovery clock signal from the blank packet. The alignment calculation unit 35 can recognize that the Low signal constituting the blank packet is the last packet of the alignment data packet and calculate the bit slip value in which the alignment data packet is shifted.

The alignment calculating section 35 transmits the calculated bit slip value to the alignment performing section 37. The alignment performing section 37 stores a plurality of data packets transmitted from the transmitter 10 and then transmits a plurality of data packets Shifted by the bit slip value.

4 (a), when the data packet received by the receiver 30 is subjected to the alignment process, the data packet can be corrected and output as shown in FIG. 4 (b).

5 is a block diagram of a low-voltage differential signaling system according to another embodiment of the present invention.

The low voltage differential signaling system according to the present embodiment may include a transmitter and a receiver capable of transmitting and receiving data packets. Here, since the transmitter and the receiver can transmit and receive data packets, they are referred to as a first transceiver 110 and a second transceiver 130, respectively.

When transmitting and receiving data packets between the first transceiver 110 and the second transceiver 130, each of the first transceiver 110 and the second transceiver 130 must be able to perform bit slip alignment. To this end, both the first transceiver 110 and the second transceiver 130 are required to have a configuration for transmitting an alignment data packet and a configuration for receiving an alignment data packet to calculate a bit slip value and performing alignment do.

Accordingly, the first transceiver 110 of the present embodiment includes a first serial-parallel conversion unit 113, a first clock generation unit 111, a first clock recovery unit 115, a first data processing unit 123, And may further include a first alignment request unit 117, a first alignment calculation unit 119, and a first alignment unit 121.

The first serial-to-parallel converter 113 can generate serial data by serializing parallel data input from a plurality of channels using a high-speed signal. In addition, the first serial-to-parallel converter 113 may convert the serial data received from the second transceiver 130 into parallel data.

The first clock recovery unit 115 restores the recovery clock signal received together with the alignment data packet or the general data packet from the second transceiver 130. Then, the first clock recovery unit 115 reconstructs the data by sampling the received data using the recovery clock signal.

The first data processor 123 may insert the reference clock signal generated by the first clock generator 111 into the serial data from the first serial-to-parallel converter 113 and transmit it to the second transceiver 130, The reference clock signal and the serial data can be synchronized and transmitted to the second transceiver 130, respectively. The first data processor 123 separates the clock signal from the alignment data packet or the general data packet received from the second transceiver 130 and transfers the clock signal to the first clock recovery unit 115.

The first alignment request unit 117, like the alignment request unit in the above-described embodiment, is configured to automatically calculate the number of bits to shift data in order to prevent data loss due to bit slip, A key packet, and a blank packet to the second transceiver 130, as shown in FIG.

The first alignment calculation unit 119 measures the number of bits of the alignment data packet shifted by bit slip using the lock packet, the key packet, and the blank packet transmitted from the second transceiver 130, The number can be calculated as a bit slip value.

The first alignment performing unit 121 shifts the data packet received from the second transceiver 130 by using the bit slip value calculated by the first alignment calculating unit 119 so as to prevent the loss of the data packet have.

The second transceiver 130 of the present embodiment includes a second serial-parallel conversion unit 133, a second clock recovery unit 135, a second clock generation unit 131, a second data processing unit 143, A calculation unit 139, a second alignment unit 141, and a second alignment request unit 137.

The second serial-to-parallel converter 133 converts the serial data received from the first transceiver 110 into parallel data or converts parallel data inputted from a plurality of channels into serial data using a high-speed signal, To the transceiver (110).

The second clock recovery unit 135 restores the reference clock signal received together with the alignment data packet or the general data packet from the first transceiver 110. Then, the first clock recovery unit 115 samples the received data using the reference clock signal.

The second clock generating unit 131 generates a reference clock signal for use in synchronizing serial data in the first transceiver 110 when the serial data transmitted from the second transceiver 130 to the first transceiver 110 is transmitted, Signal can be generated.

The second data processing unit 143 separates the reference clock signal from the alignment data packet or the general data packet received from the first transceiver 110 and outputs the reference clock signal to the second clock recovery unit 135 . In addition, the second data processor 143 may insert the data into the reference clock signal generated by the second clock generator 131 and transmit the data to the first transceiver 110, or may synchronize the reference clock signal and the serial data, 1 < / RTI >

Similarly to the alignment calculation unit of the above-described embodiment, the second alignment calculation unit 139 receives a lock packet, a key packet, and a blank packet, which are alignment data packets, from the first transceiver 110, It is possible to judge how many bits are shifted compared with the key packet and the blank packet, and to calculate the bit slip value.

The second alignment performing unit 141 shifts the data packet received from the first transceiver 110 according to the bit slip value when the bit slip value is calculated by the second alignment calculating unit 139, .

The second alignment request unit 137 may be configured to request the first transceiver 110 to prevent data packets transmitted from the second transceiver 130 to the first transceiver 110 from being lost in the first transceiver 110 Lock packet, key packet, and blank packet, so that the first transceiver 110 performs alignment of the data packet.

A process of performing alignment in a low-voltage differential signaling system according to this configuration will now be described with reference to FIG.

The first alignment request unit 117 of the first transceiver 110 transfers the lock packet to the first data processor 123 and the first clock generator 111 generates a reference clock signal And transmits it to the first data processor 123. The first data processor 123 inserts the reference clock signal into the lock packet and transmits it to the second transceiver 130 (S600).

The second data processor 143 and the second clock recovery unit 135 of the second transceiver 130 separate the reference clock signal from the lock packet, sample the lock packet, and generate a recovery clock signal. Then, the second alignment calculator 139 of the second transceiver 130 counts how many bits of the High signal are input, thereby starting the alignment process (S605).

Meanwhile, the second alignment request unit 137 of the second transceiver 130 transfers the lock packet to the second data processor 143, the second clock generator 131 generates the reference clock signal, And transfers it to the processing unit 143. The second data processor 143 inserts the reference clock signal into the lock packet and transmits it to the first transceiver 110 (S610).

Upon receiving the lock packet from the second transceiver 130, the first data processor 123 and the first clock recovery unit 115 of the first transceiver 110 separate the reference clock signal from the lock packet and sample the lock packet And generates a recovery clock signal. Then, the first alignment calculation unit 119 of the first transceiver 110 counts how many bits of the High signal have been input, thereby starting the alignment process (S615).

At the same time, the first alignment request unit 117 of the first transceiver 110 transmits the key packet to the first data processor 123. The first data processor 123 inserts the key packet into the reference clock signal and transmits it to the second transceiver 130 (S620).

The second data processor 143 and the second clock recovery unit 135 of the second transceiver 130 separate the reference clock signal from the key packet and the second alignment calculator 139 separates the high clock signal And the bit slip value is calculated (S625). At the same time, the second alignment request unit 137 generates and transmits a key packet to the second data processing unit 143, and the second data processing unit 143 inserts the reference clock signal into the key packet to transmit the key packet to the first transceiver 110, (S630).

The first transceiver 110 separates the reference clock signal from the key packet, and the first alignment calculation unit 119 calculates a bit slip value according to the position of the High signal included in the key packet (S635). The first alignment request unit 117 provides the blank packet to the first data processing unit 123 and the first data processing unit 123 inserts the reference clock signal into the blank packet, (S640).

The second data processor 143 and the second clock recovery unit 135 of the second transceiver 130 separate the reference clock signal from the blank packet and in the second alignment calculator 139, Upon receiving the blank packet, the alignment process is completed (S645), and the bit slip value is transmitted to the second alignment performing unit 141. [ The second alignment request unit 137 forms a blank packet and provides it to the second data processing unit 143. The second data processing unit 143 inserts the reference clock signal into the blank packet and transmits the blank packet to the first transceiver 110 (S650).

The first data processor 123 and the first clock recovery unit 115 of the first transceiver 110 separate the reference clock signal from the blank packet. When the first alignment calculation unit 119 receives the blank packet, (S655), and transmits the bit slip value to the first alignment performing unit 121. [

Through this alignment process, the first transceiver 110 and the second transceiver 130 alternately transmit and receive the mutual lock packet, the key packet, and the blank packet to automatically calculate the bit slip value for alignment, The first and second alignment units 141 shift the data packet using the bit slip value to align the packet.

Accordingly, as shown in the upper part of FIG. 7A, the data packet Rx received by the first transceiver 110 is aligned and output, and in the graph shown in the lower part of FIG. 7 (b) The data packet Rx received by the second transceiver 130 is aligned and output. 7A is a graph of data packets transmitted by the first transceiver 110 and the graph shown at the top of FIG. 7B is a graph of the data packets transmitted by the second transceiver 130 It is a graph of a data packet to be transmitted. That is, the data packets at the upper part of Fig. 7 (a) and the upper part of Fig. 7 (b) become the same by the alignment and the data packets at the lower part of Fig. It becomes.

As described above, in the low voltage differential signaling system according to the embodiment of the present invention, when the alignment condition is satisfied, the transmitter 30 transmits the alignment data packet to the receiver 30, and the receiver 30 transmits the lock packet, , The bit slip value can be calculated using the alignment data packet made up of blank packets. When the bit slip value is calculated, the data packet transmitted from the transmitter 10 to the receiver 30 is shifted and aligned by the bit slip value, thereby preventing loss of data.

Accordingly, in the present low-voltage differential signaling system, since the bit slip value is automatically calculated, the time for calculating the bit slip value can be drastically reduced as compared with the case where the test person manually determines the bit slip, thereby shortening the development period . In addition, since the bit slip value can be automatically calculated regardless of the hardware, the design method for the alignment becomes compatible, and the alignment can be performed quickly and easily.

The standard content or standard documents referred to in the above-mentioned embodiments constitute a part of this specification, for the sake of simplicity of description of the specification. Therefore, it is to be understood that the content of the above standard content and portions of the standard documents are added to or contained in the scope of the present invention.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as falling within the scope of the present invention.

10: Transmitter 11: Serial conversion section
13: clock generator 15: data processor
17: alignment request unit 30: receiver
31: parallel conversion unit 33: clock recovery unit
35: alignment calculating section 37: alignment performing section
110: first transceiver 111: first clock generating unit
113: first serial-parallel conversion unit 115: first clock recovery unit
117: first alignment request unit 119: first alignment calculation unit
121: first alignment performing unit 123: first data processing unit
130: second transceiver 131: second clock generating unit
133: second serial-parallel conversion unit 135: second clock-
137: second alignment request unit 139: second alignment calculation unit
141: second alignment performing unit 143: second data processing unit

Claims (9)

A transmitter for transmitting an alignment data packet for correcting a bit slip to request alignment when a predetermined alignment condition is satisfied; And
And a receiver for receiving the alignment data packet and comparing the information with the information of the alignment data packet which is held in advance to calculate a bit slip value for alignment and recovering a data packet received from the transmitter according to the bit slip value Voltage differential signal system. The method according to claim 1,
Wherein the alignment data packet includes:
A lock packet informing the start of the alignment;
A key packet transmitted to calculate the bit slip value, wherein at least one bit has a High value;
And a blank packet indicating the end of the alignment. 3. The method of claim 2,
Wherein the lock packet has all bits of a high value. 3. The method of claim 2,
Wherein the blank packet has all bits of a Low value. 3. The method of claim 2,
Wherein at least one of the lock packet, the key packet, and the blank packet is transmitted a plurality of times. The method according to claim 1,
The receiver comprising:
An alignment calculation section for calculating the bit slip value, which is the number of bits shifted by the alignment data packet according to a position of a bit having a High value in the key packet among the alignment packets;
And an alignment unit performing an alignment of a data packet transmitted from the transmitter using the bit slip value. The method according to claim 6,
Wherein the alignment performing unit stores a plurality of data packets transmitted from the transmitter and shifts the plurality of data packets according to the bit slip value to recover the data. The method according to claim 1,
The receiver further comprises an alignment request unit for transmitting the alignment data packet to the transmitter to request alignment;
Wherein the transmitter comprises: an alignment calculating section for calculating a bit slip value, which is a number of shifted bits of the alignment data packet received from the receiver; and an alignment calculating section for performing alignment of data packets transmitted from the receiver using the bit slip value Further comprising an execution unit operable to generate the low voltage differential signal. 9. The method of claim 8,
Wherein the transmitter and the receiver alternately transmit a lock packet, a key packet, and a blank packet included in the alignment data packet to the other party.

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