KR20160013399A - Organic light emitting diode display device and fabricating method of the same - Google Patents

Abstract

The present invention discloses an organic light emitting display device and a manufacturing method thereof. According to the present invention, the organic light emitting display device includes: a substrate having a display region and a non-display region; a gate wire formed in one direction on the substrate and a data line intersecting with the gate wire; a thin film transistor disposed on the display region and formed in an intersecting region of the gate wire and the data wire; an organic light emitting diode disposed on the thin film transistor and including a first electrode, an organic light emitting layer, and a second electrode; and a pad unit disposed on the non-display region. The pad unit includes a pad electrode connected to the gate wire or the data wire, and an encapsulation pattern is disposed on a connection part of the pad electrode and the gate wire or the data wire.

Description

[0001] The present invention relates to an organic electroluminescent display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to an organic light emitting display and a method of manufacturing the same, and more particularly, to an organic light emitting display having improved reliability and a manufacturing method thereof.

In recent years, as the information age has come to a full-fledged information age, a display field for visually representing electrical information signals has been rapidly developed. In response to this, various flat panel display devices having excellent performance of thinning, lightweighting, Flat Display Device) has been developed to replace CRT (Cathode Ray Tube).

Specific examples of such flat panel display devices include a liquid crystal display device (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD) A plasma display panel (PDP), a field emission display (FED), an electroluminescence display (ELD), and an electro-wetting display (EWD) And the like. In general, a flat panel display panel, which realizes images, is an essential component. The flat panel display panel includes a pair of substrates bonded together with an intrinsic light emitting material or a polarizing material layer therebetween.

Since an organic light emitting diode (OLED) display device, which is one of such flat panel display devices, includes an organic light emitting element that is a self light emitting element, a separate light source used in a liquid crystal display It is lightweight and thin. In addition, it has superior viewing angle and contrast ratio compared with liquid crystal display devices, is advantageous in terms of power consumption, can be driven by DC low voltage, has a quick response speed, is resistant to external impacts due to its solid internal components, It has advantages.

Such an organic light emitting display device is divided into a display area and a non-display area outside the display area. A thin film transistor and an organic electroluminescent device are formed in the display region. The non-display region is provided with a pad portion including a thin film transistor from an external power source and a pad electrode for applying a signal voltage to the organic electroluminescent element. Here, the thin film transistor and the organic electroluminescent device are electrically connected to each other through a pad portion and a plurality of wirings.

The pad electrode of the pad portion formed in the non-display region may be exposed to the outside in order to be connected to the driving portion. At this time, corrosion of the pad electrode may occur due to external moisture and oxygen. When the pad electrode is corroded, signal transmission is not smooth and reliability may be a problem.

The present invention relates to an organic light emitting display device capable of preventing corrosion of a pad electrode and preventing signal transmission failure by forming a pad electrode which is exposed to the outside by a material which is not corroded by oxygen and moisture due to external exposure, And a manufacturing method thereof.

Further, the present invention provides an organic light emitting display device and a method of manufacturing the same, which can prevent a wiring from being exposed by forming a sealing pattern at a connection portion between a wiring and the pad electrode, prevent corrosion of wiring, and prevent signal transmission failure It has its purpose.

In addition, the present invention includes a wiring formed of a first wiring layer including the same material as the pad electrode and a second wiring layer including a material having a low resistance, and the first wiring layer and the pad electrode are integrally formed, An organic electroluminescent display device, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided an organic light emitting display including: a substrate divided into a display region and a non-display region; A gate wiring formed on the substrate in one direction and a data wiring crossing the gate wiring; A thin film transistor disposed on the display region and formed in an intersection region of the gate wiring and the data wiring; An organic light emitting element disposed on the thin film transistor, the organic light emitting element including a first electrode, an organic light emitting layer, and a second electrode; And a pad portion disposed on the non-display region, wherein the pad portion includes a pad electrode connected to the gate wiring or the data wiring, and a sealing pattern is formed at a connection portion between the pad electrode and the gate wiring or the data wiring. .

A method of manufacturing an organic light emitting display device according to the present invention is characterized in that a thin film transistor is formed in the display region on a substrate divided into a display region and a non-display region, Forming a dummy layer disposed on the substrate; Forming a protective film on the thin film transistor to expose the dummy layer; Forming a planarization film on the protective film in the display region; Forming an electrode material layer on the entire surface of the substrate on which the planarization layer is formed; Forming a photoresist pattern on the electrode material layer in the display area; Etching the electrode material layer and the dummy layer using the photoresist pattern and the protective film as masks to form a first electrode in the display region and exposing the pad electrode in the non-display region; And forming an encapsulation pattern on the exposed pad electrode.

The organic electroluminescent display device and the method of manufacturing the same according to the present invention can prevent corrosion of the pad electrode and prevent signal transmission failure by forming the pad electrode exposed to the outside as a material which is not corroded by oxygen and moisture due to external exposure, There is an effect that can be prevented.

In addition, the organic light emitting display device and the method of manufacturing the same according to the present invention can prevent the wiring from being exposed by forming a sealing pattern at the connection between the wiring and the pad electrode, preventing corrosion of the wiring, It is effective.

Further, the organic light emitting display device and the method of manufacturing the same according to the present invention include a wiring formed of a first wiring layer including the same material as the pad electrode and a second wiring layer including a material having a small resistance, And the pad electrode are integrally formed, thereby simplifying the process and reducing the manufacturing cost.

1 is a plan view of an organic light emitting display according to a first embodiment of the present invention.
2 is a cross-sectional view of an organic light emitting display according to a first embodiment of the present invention.
3 is a cross-sectional view of an organic light emitting display according to a second embodiment of the present invention.
4A to 4C are views illustrating a method of manufacturing an organic light emitting display according to a second embodiment of the present invention.
5 is a plan view of an organic light emitting display according to a third embodiment of the present invention.
6 is a cross-sectional view of an organic light emitting display according to a third embodiment of the present invention.
7A and 7B are views illustrating a method of manufacturing an organic light emitting display according to a third embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

For a description of a time relationship, for example, 'after', 'after', and 'after'. If the temporal posterior relation is explained by 'before' or the like, it may include cases where 'right' or 'direct' is not used and is not continuous.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

First, an organic light emitting display according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of an organic light emitting display according to a first embodiment of the present invention. 2 is a cross-sectional view of an organic light emitting display according to a first embodiment of the present invention.

Referring to FIGS. 1 and 2, the organic light emitting display according to the first embodiment of the present invention includes a substrate 100 divided into a display region and a non-display region. The substrate 100 may be an insulating substrate. At this time, the substrate 100 may include silicon (Si), glass, plastic, or polyimide (PI). However, the present invention is not limited thereto, and a plurality of layers formed on the substrate 100 and a material capable of supporting the elements are sufficient.

A thin film transistor Tr and an organic light emitting diode OL electrically connected to the thin film transistor Tr may be disposed in a display region of the substrate 100. [ In addition, a pad portion may be disposed in the non-display region of the substrate 100. The pad portion may include a first pad portion and a second pad portion. The thin film transistor Tr, the organic light emitting diode OL, the first pad portion and the second pad portion will be described in detail as follows.

A gate line 118 is formed on the substrate 100 in one direction, and a data line 119 is formed in a direction different from the one direction. The gate line 118 and the data line 119 intersect with each other to define a pixel region in the display region. A thin film transistor Tr is formed in an intersection region of the gate wiring 118 and the data wiring 119. Also, an organic light emitting diode (OL) electrically connected to the thin film transistor (Tr) is formed in the pixel region.

The thin film transistor Tr includes a semiconductor layer 111 formed on the substrate 100, a gate electrode 113 branched from the gate wiring 118, a source electrode 115 branched from the data wiring 119, And a drain electrode 116 spaced apart from the source electrode 115 in the same layer. The organic light emitting diode OL may include a first electrode 130, an organic emission layer 135, and a second electrode 136.

The first pad unit may include a first pad electrode 140, and the second pad unit may include a second pad electrode 150. The first pad electrode 140 may be connected to the gate line 118. The second pad electrode 150 may be connected to the data line 119.

A semiconductor layer 111 is formed on the substrate 100 in the display region. The semiconductor layer 111 may include a source region, a channel region, and a drain region. A gate insulating layer 120 is formed on the semiconductor layer 111. The gate insulating layer 120 may be formed in the display region and the non-display region. That is, the gate insulating layer 120 may be formed on the entire surface of the substrate 100 on which the semiconductor layer 111 is formed.

The gate line 118, the gate electrode 113, and the first pad electrode 140 may be formed on the gate insulating layer 120. The gate electrode 113 may be formed to overlap the semiconductor layer 111 in the display region. Also, the first pad electrode 140 may be formed in a non-display region.

The gate wiring 118 and the gate electrode 113 may be formed as a double layer. In detail, the gate wiring 118 may be formed by stacking a first gate wiring layer 118a and a second gate wiring layer 118b. The gate electrode 113 may be formed by stacking a first gate electrode layer 113a and a second gate electrode layer 113b.

The first gate wiring layer 118a and the first gate electrode layer 113a may be formed of the same material. At this time, the first gate wiring layer 118a and the first gate electrode layer 113a may be integrally formed.

The first gate wiring layer 118a and the first gate electrode layer 113a can improve adhesion between the second gate wiring layer 118b and the second gate electrode layer 113b. For example, the first gate wiring layer 118a and the first gate electrode layer 113a may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof.

The second gate wiring layer 118b and the second gate electrode layer 113b may be formed of the same material. The second gate wiring layer 118b and the second gate electrode layer 113b may be integrally formed.

The second gate wiring layer 118b and the second gate electrode layer 113b may be formed of a metal having a low resistance. For example, the second gate wiring layer 118b and the second gate electrode layer 113b may be formed of copper (Cu).

The first pad electrode 140 may be formed of a material that is not corroded by oxygen and moisture due to external exposure. The first pad electrode 140 may be formed of a material that is not etched by the etchant of the first electrode 130 of the OLED OL. In addition, the first pad electrode 140 may be formed of the same material as the first gate wiring layer 118a of the gate wiring 118. For example, the first pad electrode 140 may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof. Therefore, corrosion of the first pad electrode 140 can be prevented and signal transmission failure can be prevented.

The first pad electrode 140 may be connected to the gate line 118. The first pad electrode 140 may be formed integrally with the gate line 118. In detail, the first pad electrode 140 may be formed integrally with the first gate wiring layer 118a of the gate wiring 118. Therefore, the first pad electrode 140, the gate wiring 118, and the gate electrode 113 can be formed by the same process, thereby simplifying the process and reducing manufacturing cost.

An interlayer insulating film 121 is formed on the gate wiring 118 and the gate electrode 113. In the display region, the interlayer insulating layer 121 and the gate insulating layer 120 may include a contact hole exposing the semiconductor layer 111. The contact hole may expose a source region and a drain region of the semiconductor layer 111.

The data line 119, the source electrode 115, the drain electrode 116 and the second pad electrode 150 may be formed on the interlayer insulating film 121 including the contact hole. The data line 119, the source electrode 115 and the drain electrode 116 may be formed in the display region and the second pad electrode 150 may be formed in the non-display region.

The data line 119 may be arranged to extend in a direction different from the gate line 118. The source electrode 115 and the drain electrode 116 may be spaced apart from each other and may be in contact with the semiconductor layer 111 exposed through the contact hole. The source electrode 115 may be in contact with a source region of the semiconductor layer 111 and the drain electrode 116 may be in contact with a drain region of the semiconductor layer 111.

The data line 119, the source electrode 115, and the drain electrode 116 may be formed as a double layer. In detail, the data line 119 may be formed by stacking a first data wiring layer 119a and a second data wiring layer 119b. The source electrode 115 may be formed by stacking a first source electrode layer 115a and a second source electrode layer 115b. In addition, the drain electrode 116 may be formed by stacking a first drain electrode layer 116a and a second drain electrode layer 116b.

The first data line layer 119a, the first source electrode layer 115a, and the first drain electrode layer 116a may be formed of the same material. The first data wiring layer 119a and the first source electrode layer 115a may be integrally formed.

The first data wiring layer 119a, the first source electrode layer 115a and the first drain electrode layer 116a are formed on the second data wiring layer 119b, the second source electrode layer 115b, The adhesive strength of the electrode layer 116b can be improved. For example, the first data line layer 119a, the first source electrode layer 115a, and the first drain electrode layer 116a may be selected from the group consisting of moly titanium (MoTi), titanium (Ti) As shown in FIG.

The second data wiring layer 119b, the second source electrode layer 115b, and the second drain electrode layer 116b may be formed of the same material. The second data wiring layer 119b and the second source electrode layer 115b may be integrally formed.

The second data wiring layer 119a, the second source electrode layer 115b, and the second drain electrode layer 116b may be formed of a metal having a low resistance. For example, the second data wiring layer 119b, the second source electrode layer 115b, and the second drain electrode layer 116b may be formed of copper (Cu).

The second pad electrode 150 may be formed of a material that is not corroded by oxygen and moisture due to external exposure. The second pad electrode 150 may be formed of a material that is not etched by the etchant of the first electrode 130 of the OLED OL. The second pad electrode 150 may be formed of the same material as the first data line layer 119a of the data line 118. For example, the second pad electrode 150 may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof. Therefore, corrosion of the second pad electrode 150 can be prevented, and signal transmission failure can be prevented.

The second pad electrode 150 may be connected to the data line 119. The second pad electrode 150 may be formed integrally with the data line 119. In detail, the second pad electrode 150 may be formed integrally with the first data wiring layer 119a of the data line 119. Thus, the second pad electrode 150, the data line 119, the source electrode 115, and the drain electrode 116 can be formed in the same process, thereby simplifying the process and reducing the manufacturing cost.

The first pad electrode 140 of the first pad portion and the second pad electrode 150 of the second pad portion may be exposed to the outside in order to be connected to the driving unit. When the pad electrodes 140 and 150 are formed of copper or the like, when the pad electrodes 140 and 150 are exposed to the outside, corrosion may occur due to contact with oxygen and moisture. Such corrosion causes defective signal transmission, and reliability of the organic light emitting display is reduced.

Accordingly, the pad electrodes 140 and 150 may be formed of a material that is not corroded by oxygen and moisture even when exposed to the outside. In addition, the first electrode 130 may be formed of a material which is not etched by the etchant of the first electrode 130 of the OLED. Therefore, damage of the pad electrodes 140 and 150 in the process of forming the first electrode 130 of the OLED OL can be prevented. For example, the pad electrodes 140 and 150 may be formed of one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof. As a result, corrosion can be prevented, reliability can be improved, and signal transmission failure can be improved.

The gate line 118 and the data line 119 connected to the first pad electrode 140 and the second pad electrode 150 may include a material having a low resistance. For example, the gate wiring 118 and the data wiring 119 may include copper (Cu). As a result, the resistance of the wirings 118 and 119 is small, which is advantageous for signal transmission.

A thin film transistor Tr including the semiconductor layer 111, the gate electrode 113, the source electrode 115 and the drain electrode 116 and the first pad including the first pad electrode 140, And a second pad portion including the second pad electrode 150 may be formed. The first pad electrode 140 may be formed in the same process as the gate line 118 and the gate electrode 113. The second pad electrode 150 may be formed in the same process as the data line 119, the source electrode 115, and the drain electrode 116.

A protective film 122 may be formed on the thin film transistor Tr. The passivation layer 122 and the interlayer dielectric layer 121 may be formed to expose the first pad electrode 140 and the second pad electrode 150.

In detail, the interlayer insulating film 121 and the protective film 122 may be formed on the gate wiring 118. The interlayer insulating layer 121 and the passivation layer 122 are formed to expose the first pad electrode 140 and may not overlap the first pad electrode 140.

In addition, the protective layer 122 may be formed on the data line 119. At this time, the protective layer 122 is formed to expose the second pad electrode 150 and not overlap the second pad electrode 150.

That is, the first pad electrode 140 and the second pad electrode 150 may be exposed on the upper surface and the side surface. The first pad electrode 140 and the second pad electrode 150 are not corroded even when exposed to the outside and are not affected by the etchant of the first electrode 130 of the OLED OL, .

A data line 119 or a gate line 118 formed of a double layer is disposed under the protective layer 122. The data line 119 or the gate line 118 may be connected to the pad electrodes 140 and 150. At this time, a sealing pattern 170 may be formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150.

That is, the sealing pattern 170 may be in contact with the pad electrodes 140 and 150. In detail, the sealing pattern 170 may be in contact with the upper surface of the pad electrodes 140 and 150. The sealing pattern 170 may be in contact with the gate wiring 118 or the data wiring 119. In detail, the encapsulation pattern 170 may be in contact with the side surfaces of the gate wiring 118 or the data wiring 119. In addition, the sealing pattern 170 may be in contact with the upper surface and the side surface of the protective film 122.

The side surfaces of the second data wiring layer 119b of the data wiring 119 or the second gate wiring layer 118b of the gate wiring 118 disposed under the protective film 122 are exposed. The second data interconnection layer 119b and the second gate interconnection layer 118b are formed of a material having a low resistance but can be corroded by oxygen or moisture. The second data wiring layer 119b and the second gate wiring layer 118b are formed of a material that can be etched by the etching solution of the first electrode 130 of the organic light emitting diode OL. That is, when the second data wiring layer 119b or the second gate wiring layer 118b is formed to be exposed to the outside, the data wiring 119 or the gate wiring 118 is corroded, .

Accordingly, a sealing pattern 170 is formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150. That is, a sealing pattern 170 is formed so as to be in contact with the side surfaces of the second data wiring layer 119b and the second gate wiring layer 118b, and the second data wiring layer 119b and the second gate wiring layer 118b, May not be exposed. As a result, corrosion of the data line 119 and the gate line 118 can be prevented.

The encapsulation pattern 170 may be disposed at a connection portion between the data line 119 and the second pad electrode 150. The encapsulation pattern 170 may be disposed at a connection portion between the gate line 118 and the first pad electrode 140.

At this time, the sealing pattern 170 may be disposed to surround the side surfaces of the second gate wiring layer 118b and the side surfaces of the second data wiring layer 119b. However, the present invention is not limited thereto, and it is sufficient that the second data wiring layer 119b and the second gate wiring layer 118b are not exposed to the outside.

The encapsulation pattern 170 disposed at the connection between the data line 119 and the second pad electrode 150 may be arranged to extend in a direction perpendicular to the data line 119. The sealing pattern 170 disposed at the connection between the gate wiring 118 and the first pad electrode 140 may be disposed to extend in a direction perpendicular to the gate wiring 118.

The sealing patterns 170 arranged to extend in the direction perpendicular to the wirings 118 and 119 may be formed of an insulating material. For example, the sealing pattern 170 may be formed as a sealant. At this time, the sealing pattern 170 may be formed by coating the connection portions of the wirings 118 and 119 and the pad electrodes 140 and 150 without a separate patterning process. Therefore, the process can be simple and the productivity can be improved.

The planarization layer 123 may be formed on the protective layer 122. The planarization layer 123 may not be disposed on the first pad electrode 140 and the second pad electrode 150. That is, the planarization layer 123 may be formed only in the display region where the thin film transistor Tr is formed. The passivation layer 122 and the planarization layer 123 may include a contact hole exposing the drain electrode 116 of the thin film transistor Tr.

The drain electrode 116 may be electrically connected to the first electrode 130 of the organic light emitting diode OL through the passivation layer 122 and the contact hole passing through the planarization layer 123.

The organic light emitting diode OL is formed on the planarization layer 123. The organic light emitting diode OL includes a first electrode 130, a second electrode 136 formed to face the first electrode 130, and a second electrode 136 formed between the first electrode 130 and the second electrode 136 And an organic emission layer 135 formed on the organic emission layer 135.

In addition, a bank pattern 139 is formed on the planarization film 123. The bank pattern 139 is formed to expose the first electrode 130 of the organic light emitting diode OL. An organic light emitting layer 135 and a second electrode 136 are formed on the exposed first electrode 130. That is, the bank pattern 139 may define a light emitting region and a non-light emitting region. In addition, the bank pattern 139 is formed to surround the side surface of the first electrode 130, thereby preventing corrosion of the side surface of the first electrode 130.

The first electrode 130 may be an anode electrode. The first electrode 130 may be formed of a plurality of electrode layers. For example, the first electrode 130 may have a triple-layer structure in which a first electrode layer 130a, a second electrode layer 130b, and a third electrode layer 130c are sequentially stacked.

The first electrode layer 130a can increase the adhesion of the second electrode layer 130b. In addition, the first electrode layer 130a may be formed of a transparent conductive material. For example, the first electrode layer 130a may be formed of ITO.

The second electrode layer 130b may be a reflective layer. The second electrode layer 130b may be formed of a metal or a metal alloy. For example, the second electrode layer 130b may be formed of a silver (Ag) alloy. Accordingly, the organic light emitting diode OL may emit light at an upper portion of the organic light emitting diode OL.

The third electrode layer 130c has a large work function, so that the first electrode 130 can function as an anode electrode. The third electrode layer 130c may be formed of a transparent conductive material. For example, the third electrode layer 130c may be formed of ITO.

An organic light emitting layer 135 is formed on the first electrode 130. Although the organic light emitting layer 135 is shown as a single layer in the drawing, the present invention is not limited thereto. The organic light emitting layer 135 may include a hole injection layer, a hole transporting layer, an emitting material layer, and an electron transporting layer an electron transporting layer, and an electron injection layer. Although the organic light emitting layer 135 is formed only on the first electrode 130 exposed by the bank pattern 139 in the drawing, the organic light emitting layer 135 may be formed on the bank pattern 139 .

A second electrode 136 may be formed on the organic light emitting layer 135 so as to face the first electrode 130. In this case, the second electrode 136 may be a cathode electrode. The second electrode 136 may be formed of a metal or a metal alloy having a low work function. However, it is not limited thereto and may include a material which can be generally used as a cathode electrode. Further, although not shown in the figure, auxiliary electrodes may be further formed in the display region to lower the voltage drop of the second electrode 136. [

Next, an organic light emitting display device according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is a cross-sectional view of an organic light emitting display according to a second embodiment of the present invention. 4A to 4C are views illustrating a method of manufacturing an organic light emitting display according to a second embodiment of the present invention.

The organic light emitting display device according to the second embodiment of the present invention may have the same structure as the organic light emitting display device according to the first embodiment described above. The description overlapping with the embodiment described above may be omitted. The same reference numerals are assigned to the same components.

3, the organic light emitting display according to the second exemplary embodiment of the present invention includes an encapsulation pattern 170 and a second gate interconnection layer 118b between the encapsulation pattern 170 and the second data interconnection layer 119b. A filler 180 may be included. The filler 180 may include a getter.

That is, the filler 180 may block the oxygen and moisture that flow into the gate wiring 118 and the data wiring 119, together with the sealing pattern 170. As a result, moisture and oxygen can be blocked, and corrosion of the gate wiring 118 and the data wiring 119 can be prevented.

The filler 180 may be formed to contact the back surface of the protective film 122. In addition, the filler 180 may be formed to contact the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b.

The second gate wiring layer 118b or the second data wiring layer 119b may be etched using the protective film 122 as a mask. At this time, due to an under-cut phenomenon, the ends of the second gate wiring layer 118b or the second data wiring layer 119b may be formed further inward than the end of the protective film 122. [ That is, a space may be formed under the end of the protective film 122.

At this time, the filler 180 may be disposed in a space formed at the lower end of the protective film 122. This can prevent a space from being formed between the sealing pattern 170 and the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b. The filler 180 may be formed at any position between the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b and the sealing pattern 170. [

Next, a second embodiment of the present invention will be described in more detail with reference to a manufacturing method.

4A, a thin film transistor Tr is formed in the display region on a substrate 100 divided into a display region and a non-display region, and the first pad electrode 140 and the second pad 140 are formed in the non- Electrode 150 is formed. A first dummy layer 45 and a second dummy layer 55 are formed on the first pad electrode 140 and the second pad electrode 150, respectively.

A method of forming the thin film transistor Tr, the first pad electrode 140, the second pad electrode 150, the first dummy layer 45, and the second dummy layer 55 will be described in more detail as follows .

A semiconductor layer (111) is formed on the substrate (100). The semiconductor layer 111 may be formed by forming a semiconductor material layer, forming a photoresist pattern on the semiconductor material layer, etching the semiconductor material layer using the photoresist pattern as a mask, stripping the photoresist layer. The semiconductor layer 111 may be formed in the display region. A gate insulating layer 120 is formed on the semiconductor layer 111. The gate insulating layer 120 may be formed on the entire surface of the substrate 100 on which the semiconductor layer 111 is formed.

A gate wiring 118, a gate electrode 113 branched from the gate wiring 118, a first pad electrode 140, and a first dummy layer 45 are formed on the gate insulating layer 120. More specifically, a first gate wiring material layer and a second gate wiring material layer are formed on the gate insulating film 120, and a photoresist pattern is formed on the second gate wiring material layer. The second gate wiring material layer is etched using the photoresist pattern as a mask to expose the first gate wiring material layer. Thereafter, the exposed first gate wiring material layer is etched, and the photoresist pattern is removed.

The first gate wiring material layer and the second gate wiring material layer are formed of a material which is not etched with the same etching liquid. Thus, the first gate wiring material layer disposed on the first gate wiring material layer may be etched first, and then the first gate wiring material layer may be etched.

Thus, the gate wiring 118 and the gate electrode 113 formed by stacking the first gate wiring material layer and the second gate wiring material layer can be formed. Also, a first pad electrode 140 formed of the first gate wiring material layer and a first dummy layer 45 formed of the second gate wiring material layer may be formed.

That is, the gate wiring 118 and the gate electrode 113 may be formed as a double layer. In detail, the gate wiring 118 may be formed by stacking a first gate wiring layer 118a and a second gate wiring layer 118b. The gate electrode 113 may be formed by stacking a first gate electrode layer 113a and a second gate electrode layer 113b.

The first gate wiring layer 118a and the first gate electrode layer 113a may be formed of the same material as the first pad electrode 140. [ That is, the first gate wiring layer 118a, the first gate electrode layer 113a, and the first pad electrode 140 may be formed of a first gate wiring material layer. In addition, the first gate wiring layer 118a, the first gate electrode layer 113a, and the first pad electrode 140 may be integrally formed.

In addition, the second gate wiring layer 118b and the second gate electrode layer 113b may be formed of the same material as the first dummy layer 45. That is, the second gate wiring layer 118b, the second gate electrode layer 113b, and the first dummy layer 45 may be formed of a second gate wiring material layer. In addition, the second gate wiring layer 118b, the second gate electrode layer 113b, and the first dummy layer 45 may be integrally formed.

The first gate wiring material layer may improve adhesion of the second gate wiring material layer. In addition, the first gate wiring layer may be formed of a material which is not corroded by oxygen and moisture due to external exposure. In addition, the first gate wiring material layer may be formed of a material which is not etched by the etchant of the first electrode of the organic light emitting element. For example, the first gate wiring material layer may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof.

Further, the second gate wiring material layer may be formed of a metal having a low resistance. For example, the second gate wiring material layer may be formed of copper (Cu). At this time, the second gate wiring material layer may be formed of a material which is later etched by the etching solution of the first electrode of the organic light emitting device.

The gate wiring 118 is arranged to extend in one direction. The gate electrode 113 may be formed in a region overlapping the semiconductor layer 111. The first pad electrode 140 and the first dummy layer 45 may be disposed at the ends of the gate line 118.

An interlayer insulating film 121 is formed on the gate wiring 118, the gate electrode 113, the first pad electrode 140, and the first dummy layer 45. The interlayer insulating layer 121 may be formed on the entire surface of the substrate 100.

A plurality of contact holes are formed on the interlayer insulating film 121. In detail, a contact hole is formed through the interlayer insulating layer 121 and the gate insulating layer 120 to expose the semiconductor layer 111.

A data line 119, a source electrode 115, a drain electrode 116, a second pad electrode 150 and a second dummy layer 55 branched from the data line 119 are formed on the interlayer insulating film 121, . In detail, a first data wiring material layer and a second data wiring material layer are formed on the interlayer insulating film 121, and a photoresist pattern is formed on the second data wiring material layer. The second data wiring material layer is etched using the photoresist pattern as a mask to expose the first data wiring material layer. Thereafter, the exposed first data wiring material layer is etched, and the photoresist pattern is removed.

The first data wiring material layer and the second data wiring material layer are formed of a material that is not etched with the same etchant. Therefore, the first data wiring material layer disposed on the first data wiring material layer may be etched first, and then the first data wiring material layer may be etched.

Thus, the data line 119, the source electrode 115, and the drain electrode 116 formed by stacking the first data wiring material layer and the second data wiring material layer can be formed. In addition, a second pad electrode 150 formed of the first data wiring material layer and a second dummy layer 55 formed of the second data wiring material layer may be formed.

That is, the data line 119, the source electrode 115, and the drain electrode 116 may be formed as a double layer. In detail, the data line 119 may be formed by stacking a first data wiring layer 119a and a second data wiring layer 119b. The source electrode 115 may be formed by stacking a first source electrode layer 115a and a second source electrode layer 115b. In addition, the drain electrode 116 may be formed by stacking a first drain electrode layer 116a and a second drain electrode layer 116b.

The first data line layer 119a, the first source electrode layer 115a and the first drain electrode layer 116a may be formed of the same material as the second pad electrode 150. [ That is, the first data wiring layer 119a, the first source electrode layer 115a, the first drain electrode layer 116a, and the second pad electrode 150 may be formed of a first data wiring material layer. The first data wiring layer 119a, the first source electrode layer 115a, and the second pad electrode 150 may be integrally formed.

The second data line layer 119b, the second source electrode layer 115b and the second drain electrode layer 116b may be formed of the same material as the second dummy layer 55. [ That is, the second data wiring layer 119b, the second source electrode layer 115b, the second drain electrode layer 116b, and the second dummy layer 55 may be formed of a second data wiring material layer. In addition, the second data wiring layer 119b, the second source electrode layer 115b, and the second dummy layer 55 may be integrally formed.

The first data wiring material layer may improve the adhesion of the second data wiring material layer. In addition, the first data wiring material layer may be formed of a material which is not corroded by oxygen and moisture due to external exposure. In addition, the first data wiring material layer may be formed of a material which is not etched by the etching solution of the first electrode of the organic light emitting element. For example, the first data wiring material layer may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof.

Further, the second data wiring material layer may be formed of a metal having a low resistance. For example, the second data wiring material layer may be formed of copper (Cu). At this time, the second data wiring material layer may be formed of a material which is later etched by the etching solution of the first electrode of the organic light emitting element.

The data line 119 is arranged to extend in a different direction from the gate line 118. The source electrode 115 and the drain electrode 116 may be spaced apart from each other and may be disposed in contact with the semiconductor layer 111 through a contact hole. The second pad electrode 150 and the second dummy layer 55 may be disposed at the ends of the data line 119.

The thin film transistor Tr including the semiconductor layer 111, the gate electrode 113, the source electrode 115 and the drain electrode 116, the first pad electrode 140, the first pad electrode The first dummy layer 45, the second pad electrode 150 and the second dummy layer 55 disposed on the second pad electrode 150 may be formed on the first and second pad electrodes 140 and 140. The thin film transistor Tr is formed in a display region and the first dummy layer 45, the second dummy layer 55 and the first dummy layer 55 are formed in a non-display region .

The first pad electrode 140 and the first dummy layer 45 are formed integrally with the gate wiring 118 and the second pad electrode 150 and the second dummy layer 55 are formed on the data wiring But it is not limited thereto. That is, the first pad electrode 140 and the first dummy layer 45 are formed integrally with the gate line 118, and the second pad electrode 150 and the second dummy layer 55 are formed in the data line 119 may not be integrally formed. The second pad electrode 150 and the second dummy layer 55 are formed integrally with the data line 119. The first pad electrode 140 and the first dummy layer 45 are formed in the same pattern as the gate lines 118 may not be integrally formed. That is, it suffices that at least one pad electrode and at least one dummy layer are integrally formed with at least one wiring.

A protective layer 122 is formed on the entire surface of the substrate 100 including the data line 119, the source electrode 115, the drain electrode 116, the second pad electrode 150 and the second dummy layer 55 . The protective layer 122 and the interlayer insulating layer 121 are then etched to expose the first dummy layer 45 and the second dummy layer 55. In detail, the protective layer 122 and the interlayer insulating layer 121 formed on the first dummy layer 45 are etched to expose the first dummy layer 45. Also, the protective layer 122 formed on the second dummy layer 55 is etched to expose the second dummy layer 55.

In addition, a contact hole may be formed in the protective film 122 to expose the drain electrode 116 of the thin film transistor Tr. Accordingly, the protective film 122 is disposed on the thin film transistor Tr and is arranged to expose the dummy layers 45 and 55.

A planarization layer 123 is formed on the protective layer 122 in the display region. The planarization layer 123 may be formed on the display region and may not be formed on the first pad electrode 140 and the second pad electrode 150. In addition, the planarization layer 123 may include a contact hole formed in a region corresponding to the drain electrode 116 of the thin film transistor Tr.

However, the method of forming the passivation layer 122 and the planarization layer 123 including the contact hole exposing the drain electrode 116 is not limited thereto. For example, the protective layer 122 may be formed on the entire surface of the substrate 100, and a planarization pattern having a high level difference in the display region and a low level difference in the non-display region may be formed on the protective layer 122. At this time, the planarization pattern may expose the protective layer 122 in a region corresponding to the first dummy layer 45, the second dummy layer 55, and the drain electrode 116. The first dummy layer 45, the second dummy layer 55 and the drain electrode 116 are exposed by etching the protective film 122 and the interlayer insulating film 121 using the planarization pattern including the holes as a mask . Thereafter, when the planarization pattern is ashing to remove only the low-level planarization pattern disposed in the non-display area, the planarization layer 123 having a high level difference disposed in the display area may remain as the planarization layer 123.

That is, the protective layer 122 and the interlayer dielectric layer 121 expose the first dummy layer 45 and the second dummy layer 55 in the non-display region, and the planarization layer 123 and the protective layer 122 May be formed in such a manner as to expose the drain electrode 116 in the display region.

An electrode material layer is formed on the entire surface of the substrate 100 on which the planarization layer 123 is formed. The electrode material layer may include a first electrode material layer 30a, a second electrode material layer 30b, and a third electrode material layer 30c. The first electrode material layer 30a and the second electrode material layer 30b are sequentially formed on the planarization layer 123, the protective layer 122, the first dummy layer 45 and the second dummy layer 55, And a third electrode material layer 30c are laminated.

A photoresist pattern 40 is formed on the third electrode material layer 30c. The photoresist pattern 40 may be disposed in the first electrode formation region of the organic light emitting device. That is, the photoresist pattern 40 may be formed in a region where the contact hole exposing the drain electrode 116 is formed.

Referring to FIG. 4B, the electrode material layer and the dummy layers 45 and 55 are etched using the photoresist pattern 40 and the protective layer 122 as masks. That is, the first electrode material layer 30a, the second electrode material layer 30b, the third electrode material layer 30c, the first dummy layer 45, and the second dummy layer 55 are etched. The first electrode material layer 30a, the second electrode material layer 30b, the third electrode material layer 30c, the first dummy layer 45 and the second dummy layer 55 may be etched with the same etchant have. The first pad electrode 140 and the second pad electrode 150 may include a first electrode material layer 30a, a second electrode material layer 30b, a third electrode material layer 30c, (45) and the second dummy layer (55). Thereafter, the photoresist pattern 40 is removed.

Accordingly, the first electrode 130 formed of the first electrode layer 130a, the second electrode layer 130b, and the third electrode layer 130c can be formed. The first dummy layer 45 and the second dummy layer 55 may be removed so that the first pad electrode 140 and the second pad electrode 150 are exposed.

The first electrode layer 130a may be formed of the first electrode material layer. The first electrode material layer may increase the adhesion of the second electrode material layer. The first electrode layer 130a may be formed of a transparent conductive material. For example, the first electrode layer 130a may be formed of ITO.

The second electrode layer 130b may be formed of the second electrode material layer. The second electrode layer 130b may be a reflective layer. The second electrode layer 130b may be formed of a metal or a metal alloy. For example, the second electrode layer 130b may be formed of a silver (Ag) alloy. Accordingly, the organic light emitting diode OL may emit light at an upper portion of the organic light emitting diode OL.

The third electrode layer 130c may be formed of the third electrode material layer. The third electrode layer 130c has a large work function, so that the first electrode 130 can function as an anode electrode. The third electrode layer 130c may be formed of a transparent conductive material. For example, the third electrode layer 130c may be formed of ITO.

An under-cut phenomenon may occur during the process of etching the first dummy layer 45 and the second dummy layer 55 using the protective layer 122 as a mask. That is, the side surfaces of the second gate wiring layer 118b and the second data wiring layer 119b are partly etched due to the penetration of the etchant, so that the second gate wiring layer 118b and the The end of the second data wiring layer 119b may be formed further inward. That is, a space may be formed under the end of the protective film 122.

Referring to FIG. 4C, a filler 180 may be formed in a space formed at the lower end of the protective film 122. The filler 180 may include a getter. Therefore, it is possible to prevent a space from being formed under the end of the protective film 122. However, the position of the filler 180 is not limited thereto and may be formed on the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b.

An encapsulation pattern 170 is formed on the pad electrodes 140 and 150. The encapsulation pattern 170 may be formed at a connection portion between the pad electrode 140 and the gate line 118 or the data line 119. The filler 180 may be omitted and a sealing pattern 170 may be formed as shown in FIG.

The sealing pattern 170 may be formed to extend in the direction perpendicular to the gate wiring 118 or the data wiring 119, respectively. At this time, the sealing pattern 170 may be formed of an insulating material. For example, the sealing pattern 170 may be formed as a sealant.

At this time, the sealing pattern 170 may be formed by coating the connection portions of the wirings 118 and 119 and the pad electrodes 140 and 150 without a separate patterning process. Therefore, the process can be simple and the productivity can be improved.

That is, the sealing pattern 170 may be in contact with the pad electrodes 140 and 150. In detail, the sealing pattern 170 may be in contact with the upper surface of the pad electrodes 140 and 150. The sealing pattern 170 may be in contact with the gate wiring 118 or the data wiring 119. In detail, the encapsulation pattern 170 can be in contact with the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b. In addition, the sealing pattern 170 may be in contact with the upper surface and the side surface of the protective film 122.

The dummy layers 45 and 55 are etched using the protective film 122 as a mask so that the side surfaces of the second gate wiring layer 118b and the second data wiring layer 119b disposed under the protective film 122 are exposed . The second gate wiring layer 118b and the second data wiring layer 119b are formed of a material having a low resistance but can be corroded by oxygen or moisture. Therefore, when the gate insulating layer is formed to be exposed to the outside, the data line 119 or the gate line 118 may be corroded, resulting in a bad signal transmission.

A sealing pattern 170 is formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150 so that the second gate wiring layer 118b and the second data wiring layer 119b It can be formed not to be exposed. As a result, corrosion of the data line 119 and the gate line 118 can be prevented.

Thereafter, a bank pattern is formed on the substrate 100 on which the first electrode 130 is formed. The bank patterns 139 may be formed in the display region and not in the non-display region. In addition, the first electrode 130 may be exposed in the display region.

An organic light emitting layer 135 is formed on the exposed first electrode 130. Although the organic light emitting layer 135 is shown as a single layer in the drawing, the present invention is not limited thereto. The organic light emitting layer 135 may include a hole injection layer, a hole transporting layer, an emitting material layer, and an electron transporting layer an electron transporting layer, and an electron injection layer. Although the organic light emitting layer 135 is formed only on the first electrode 130 exposed by the bank pattern 139 in the drawing, the organic light emitting layer 135 may be formed on the bank pattern 139 .

A second electrode 136 of the organic light emitting device is formed on the organic light emitting layer 135. Here, the first electrode 130 may be an anode electrode, and the second electrode 136 may be a cathode electrode. The second electrode 136 may be formed of a metal or a metal alloy having a low work function. However, it is not limited thereto and may include a material which can be generally used as a cathode electrode. Although not shown in the drawing, an auxiliary electrode may be formed on the display region together with the first electrode 130 to lower the voltage drop of the second electrode 136.

However, the formation order of the organic light emitting diode OL is not limited thereto. That is, after forming the bank pattern 139, the organic light emitting layer 135, and the second electrode 136 for exposing the first electrode 130 in the display region, the filler 180 and the sealing pattern 170 are formed You may. When the filler 180 and the sealing pattern 170 are formed first, the gate wiring 118 or the organic light emitting layer 135 may be formed in the process of forming the bank pattern 139, the organic light emitting layer 135, It is possible to prevent the data line 119 from being damaged.

Accordingly, the organic electroluminescent display device and the method of manufacturing the same according to the present invention are configured such that the pad electrodes 140 and 150 exposed to the outside are formed of a material which is not corroded by oxygen and moisture due to external exposure, Corrosion can be prevented and signal transmission failure can be prevented. The sealing patterns 170 are formed at the connection portions of the wirings 118 and 119 and the pad electrodes 140 and 150 to prevent the wirings 118 and 119 from being exposed and to prevent corrosion of the wirings 118 and 119, can do. The semiconductor device further includes wirings 118 and 119 formed of first wiring layers 118a and 119a including the same material as the pad electrodes 140 and 150 and second wiring layers 118b and 119b including a material having a low resistance, 1 wiring layers 118a and 119a and the pad electrodes 140 and 150 are integrally formed, the process can be simplified and the manufacturing cost can be reduced.

Next, an organic light emitting display device according to a third embodiment of the present invention will be described with reference to FIGS. 5 to 7. FIG. 5 is a plan view of an organic light emitting display according to a third embodiment of the present invention. 6 is a cross-sectional view of an organic light emitting display according to a third embodiment of the present invention. 7A and 7B are views illustrating a method of manufacturing an organic light emitting display according to a third embodiment of the present invention.

The organic light emitting display device according to the third embodiment of the present invention may have the same structure as the organic light emitting display device according to the previous embodiments. The description overlapping with the embodiment described above may be omitted. The same reference numerals are assigned to the same components.

5 and 6, an organic light emitting display according to a third exemplary embodiment of the present invention includes a substrate 100 divided into a display region and a non-display region. A thin film transistor Tr and an organic light emitting diode OL electrically connected to the thin film transistor Tr may be disposed in a display region of the substrate 100. [ In addition, a pad portion may be disposed in the non-display region of the substrate 100.

A gate line 118 is formed on the substrate 100 in one direction, and a data line 119 is formed in a direction different from the one direction. A thin film transistor Tr is formed in an intersection region of the gate wiring 118 and the data wiring 119. The thin film transistor Tr includes a semiconductor layer 111 formed on the substrate 100, a gate electrode 113 branched from the gate wiring 118, a source electrode 115 branched from the data wiring 119, And a drain electrode 116 spaced apart from the source electrode 115 in the same layer.

The organic light emitting diode OL may include a first electrode 230, an organic emission layer 135, and a second electrode 136. The first electrode 230 of the organic light emitting diode OL may include a plurality of electrode layers. The first electrode 230 of the organic light emitting diode OL may include a first electrode layer 230a, a second electrode layer 230b, a third electrode layer 230c, and a fourth electrode layer 230d.

The pad portion may include a first pad portion and a second pad portion. The first pad unit may include a first pad electrode 140. The second pad portion may include a second pad electrode 150.

A semiconductor layer 111 is formed on the substrate 100 in the display region and a gate insulating layer 120 is formed on the semiconductor layer 111. The gate insulating layer 120 may be formed in the display region and the non-display region.

The gate line 118, the gate electrode 113, and the first pad electrode 140 may be formed on the gate insulating layer 120. The gate electrode 113 may be formed to overlap the semiconductor layer 111 in the display region. Also, the first pad electrode 140 may be formed in a non-display region.

The gate wiring 118 and the gate electrode 113 may be formed as a double layer. In detail, the gate wiring 118 may be formed by stacking a first gate wiring layer 118a and a second gate wiring layer 118b. The gate electrode 113 may be formed by stacking a first gate electrode layer 113a and a second gate electrode layer 113b.

The first gate wiring layer 118a, the first gate electrode layer 113a, and the first pad electrode 140 may be formed of the same material. At this time, the first gate wiring layer 118a, the first gate electrode layer 113a, and the first pad electrode 140 may be integrally formed. For example, the first gate wiring layer 118a, the first gate electrode layer 113a, and the first pad electrode 140 may be formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti) Can be formed.

The second gate wiring layer 118b and the second gate electrode layer 113b may be formed of the same material. The second gate wiring layer 118b and the second gate electrode layer 113b may be integrally formed. For example, the second gate wiring layer 118b and the second gate electrode layer 113b may be formed of copper (Cu).

An interlayer insulating film 121 may be formed on the gate wiring 118 and the gate electrode 113. In the display region, the interlayer insulating layer 121 and the gate insulating layer 120 may include a contact hole exposing the semiconductor layer 111.

A data line 119, a source electrode 115, a drain electrode 116 and a second pad electrode 150 may be formed on the interlayer insulating layer 121. [ The data line 119, the source electrode 115 and the drain electrode 116 may be formed in the display region and the second pad electrode 150 may be formed in the non-display region.

The data lines 119 may extend in different directions from the gate lines 118 and may intersect with each other. The source electrode 115 and the drain electrode 116 may be spaced apart from each other and may be in contact with the semiconductor layer 111 exposed through the contact hole.

The data line 119, the source electrode 115, and the drain electrode 116 may be formed as a double layer. In detail, the data line 119 may be formed by stacking a first data wiring layer 119a and a second data wiring layer 119b. The source electrode 115 may be formed by stacking a first source electrode layer 115a and a second source electrode layer 115b. In addition, the drain electrode 116 may be formed by stacking a first drain electrode layer 116a and a second drain electrode layer 116b.

The first data line layer 119a, the first source electrode layer 115a, the first drain electrode layer 116a, and the second pad electrode 150 may be formed of the same material. The first data wiring layer 119a, the first source electrode layer 115a, and the second pad electrode 150 may be integrally formed. For example, the first data line layer 119a, the first source electrode layer 115a, the first drain electrode layer 116a, and the second pad electrode 150 may be formed of molybdenum (MoTi), titanium (Ti), and / And a combination thereof.

The second data wiring layer 119b, the second source electrode layer 115b, and the second drain electrode layer 116b may be formed of the same material. The second data wiring layer 119b and the second source electrode layer 115b may be integrally formed. For example, the second data wiring layer 119b, the second source electrode layer 115b, and the second drain electrode layer 116b may be formed of copper (Cu).

A thin film transistor Tr including the semiconductor layer 111, the gate electrode 113, the source electrode 115 and the drain electrode 116 and the first pad including the first pad electrode 140, And a second pad portion including the second pad electrode 150 may be formed. The first pad electrode 140 may be formed in the same process as the gate line 118 and the gate electrode 113. The second pad electrode 150 may be formed in the same process as the data line 119, the source electrode 115, and the drain electrode 116.

A protective film 122 may be formed on the thin film transistor Tr. The planarization layer 123 may be formed on the protective layer 122. The planarization layer 123 may not be disposed on the first pad electrode 140 and the second pad electrode 150.

The planarization layer 123 may be formed only in a display region where the thin film transistor Tr is formed. The passivation layer 122 and the planarization layer 123 may include a contact hole exposing the drain electrode 116 of the thin film transistor Tr. The passivation layer 122 and the interlayer dielectric layer 121 may be formed to expose the first pad electrode 140 and the second pad electrode 150.

The top and side surfaces of the first pad electrode 140 and the second pad electrode 150 may be exposed. The first pad electrode 140 and the second pad electrode 150 are not corroded even when exposed to the outside and are not affected by the etchant of the first electrode 130 of the OLED OL, .

A data line 119 or a gate line 118 formed of a double layer is disposed under the protective layer 122. The data line 119 or the gate line 118 may be connected to the pad electrodes 140 and 150. At this time, a sealing pattern 270 may be formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150.

The encapsulation pattern 270 may be in contact with the pad electrodes 140 and 150. In detail, the sealing pattern 270 may be in contact with the upper surface of the pad electrodes 140 and 150. The encapsulation pattern 270 may be in contact with the gate line 118 or the data line 119. In detail, the encapsulation pattern 270 may be in contact with the side surfaces of the second gate wiring layer 118b or the second data wiring layer 119b. In addition, the sealing pattern 270 may be in contact with the upper surface and the side surface of the protective film 122.

The side surfaces of the second data wiring layer 119b of the data wiring 119 or the second gate wiring layer 118b of the gate wiring 118 disposed under the protective film 122 are exposed. The second data interconnection layer 119b and the second gate interconnection layer 118b are formed of a material having a low resistance but can be corroded by oxygen or moisture. That is, when the second data wiring layer 119b or the second gate wiring layer 118b is formed to be exposed to the outside, the data wiring 119 or the gate wiring 118 is corroded, .

Therefore, a sealing pattern 270 is formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150. Accordingly, the second data wiring layer 119b and the second gate wiring layer 118b may be formed not to be exposed. In addition, corrosion of the data line 119 and the gate line 118 can be prevented.

The encapsulation pattern 270 may be disposed only at a connection portion between the data line 119 and the second pad electrode 150. In addition, the sealing pattern 270 may be disposed only at a connection portion between the gate wiring 118 and the first pad electrode 140. The encapsulation pattern 270 may be arranged in a plurality of island patterns.

At this time, the sealing pattern 270 may be formed of a transparent conductive material. For example, the encapsulation pattern 270 may comprise ITO. At this time, the sealing pattern 270 is formed more stably, and moisture permeation can be prevented. However, when the sealing patterns 270 are formed of a conductive material, they may be electrically connected to other pad electrodes 140 and 150 disposed adjacent to each other. That is, the encapsulation pattern 270 may be arranged in a plurality of island patterns.

The encapsulation pattern 270 may be disposed to surround the side surfaces of the second gate wiring layer 118b and the side surfaces of the second data wiring layer 119b. However, the present invention is not limited thereto, and it is sufficient that the second data wiring layer 119b and the second gate wiring layer 118b are not exposed to the outside.

The organic light emitting diode OL is formed on the planarization layer 123. The organic light emitting diode OL includes a first electrode 230, a second electrode 136 formed to face the first electrode 230, and a second electrode 136 formed between the first electrode 230 and the second electrode 136 And an organic emission layer 135 formed on the organic emission layer 135.

In addition, a bank pattern 139 is formed on the planarization film 123. The bank pattern 139 is formed to expose the first electrode 230 of the organic light emitting diode OL. An organic light emitting layer 135 and a second electrode 136 are formed on the exposed first electrode 130.

The first electrode 230 may be an anode electrode. The first electrode 230 may be formed of a plurality of electrode layers. For example, the first electrode 230 may have a four-layer structure in which a first electrode layer 230a, a second electrode layer 230b, a third electrode layer 230c, and a fourth electrode layer 230d are sequentially stacked .

The first electrode layer 230a, the third electrode layer 230c, and the fourth electrode layer 230d may be formed of a transparent conductive material. For example, the first electrode layer 230a, the third electrode layer 230c, and the fourth electrode layer 230d may be formed of ITO. The first electrode layer 230a may improve adhesion of the second electrode layer 230b. The third electrode layer 230c has a large work function so that the first electrode 230 can function as an anode electrode. The fourth electrode layer 230d is formed to surround the side surfaces of the first electrode layer 230a to the third electrode layer 230c to prevent corrosion of the second electrode layer 230b.

The second electrode layer 230b may be a reflective layer. The second electrode layer 230b may be formed of a metal or a metal alloy. For example, the second electrode layer 230b may be formed of a silver (Ag) alloy. Accordingly, the organic light emitting diode OL may emit light at an upper portion of the organic light emitting diode OL.

That is, the first electrode 230 of the organic light emitting diode OL includes a plurality of electrode layers. At this time, the sealing pattern 270 may be formed of the same material as the electrode layer disposed on the uppermost side of the first electrode 230. That is, the sealing pattern 270 may be formed of the same material as that of the fourth electrode layer 230d of the first electrode 230. In addition, the sealing pattern 270 may be formed in the same process as the fourth electrode layer 230d of the first electrode 230.

Next, a second embodiment of the present invention will be described in more detail with reference to a manufacturing method.

7A, a thin film transistor Tr is formed in the display region on a substrate 100 divided into a display region and a non-display region, and the first pad electrode 140 and the second pad 140 are formed in the non- Electrode 150 is formed. The first pad electrode 140 may be formed in the same process as the gate line 118 and the gate electrode 113. The second pad electrode 150 may be formed by a process using the data line 119, Drain electrode 116 in the same process.

A first dummy layer formed integrally with the second gate wiring layer 118b of the gate wiring 118 may be formed on the first pad electrode 140. [ An interlayer insulating layer 121 and a passivation layer 122 are disposed on the gate line 118. The interlayer insulating layer 121 and the passivation layer 122 are disposed to expose the first dummy layer.

A second dummy layer formed integrally with the second data wiring layer 119b of the data line 119 may be formed on the second pad electrode 150. [ A protective layer 122 is disposed on the data line 119 and the protective layer 122 is disposed to expose the second dummy layer.

A planarization layer 123 is formed on the protective layer 122 in the display region and an electrode material layer is formed on the entire surface of the substrate 100 on which the planarization layer 123 is formed. The electrode material layer may include a first electrode material layer, a second electrode material layer and a third electrode material layer which are sequentially stacked.

A photoresist pattern is formed on the third electrode material layer. The photoresist pattern may be disposed in the first electrode formation region of the organic light emitting device. The electrode material layer and the dummy layer are etched using the photoresist pattern and the protective layer 122 as a mask. That is, the first electrode material layer, the second electrode material layer, the third electrode material layer, the first dummy layer, and the second dummy layer are etched. The first electrode material layer, the second electrode material layer, the third electrode material layer, the first dummy layer, and the second dummy layer may be etched with the same etchant.

At this time, the first pad electrode 140 and the second pad electrode 150 are formed by etching the first electrode material layer, the second electrode material layer, the third electrode material layer, the first dummy layer and the second dummy layer It is not etched. Thereafter, when the photoresist pattern is removed, the first electrode layer 230a, the second electrode layer 230b, and the third electrode layer 230c may be formed. In addition, the first dummy layer and the second dummy layer may be removed, and the first pad electrode 140 and the second pad electrode 150 may be exposed.

A transparent conductive layer (not shown) is formed on the entire surface of the substrate 100 including the first electrode layer 230a, the second electrode layer 230b, the third electrode layer 230c, the exposed first pad electrode 140 and the second pad electrode 150. [ A material layer 31 is formed.

A first photoresist pattern 41 is formed on a region where the first electrode layer 230a to the third electrode layer 230c are formed and the first photoresist pattern 41 is formed on the connection portion between the first pad electrode 140 and the gate wiring 118 A second photoresist pattern 42 is formed and a third photoresist pattern 43 is formed at a connection portion between the second pad electrode 150 and the data line 119.

Referring to FIG. 7B, the transparent conductive material layer 31 is etched using the first photoresist pattern 41, the second photoresist pattern 42, and the third photoresist pattern 43 as a mask. A fourth electrode layer 230d is formed under the first photoresist pattern 41. [ Accordingly, the first electrode 230 including the first electrode layer 230a to the fourth electrode layer 230d may be formed. The first electrode layer 230a to the third electrode layer 230c may form the first electrode 230 and the fourth electrode layer 230d may be formed of the first electrode 230, As shown in FIG.

An encapsulation pattern 270 is formed under the second photoresist pattern 42 and the third photoresist pattern 43. The encapsulation pattern 270 is formed on the pad electrodes 140 and 150. That is, the sealing pattern 270 is formed at the connection portion between the pad electrodes 140 and 150 and the gate wiring 118 or the data wiring 119.

The encapsulation pattern 270 may be disposed only at a connection portion between the pad electrodes 140 and 150 and the gate lines 118 or the data lines 119 and may be arranged in a plurality of island patterns. Since the encapsulation pattern 270 is formed of a transparent conductive material, the encapsulation pattern 270 may be electrically connected to other pad electrodes 140 and 150 disposed adjacent to each other.

The dummy layer is etched using the protective layer 122 as a mask so that the side surfaces of the second gate wiring layer 118b and the second data wiring layer 119b disposed under the protective layer 122 are exposed. The second gate wiring layer 118b and the second data wiring layer 119b are formed of a material having a low resistance but can be corroded by oxygen or moisture. Therefore, when the gate insulating layer is formed to be exposed to the outside, the data line 119 or the gate line 118 may be corroded, resulting in a bad signal transmission.

A sealing pattern 270 is formed at a connection portion between the data line 119 or the gate line 118 and the pad electrodes 140 and 150 so that the second gate wiring layer 118b and the second data wiring layer 119b It can be formed not to be exposed. As a result, corrosion of the data line 119 and the gate line 118 can be prevented.

Thereafter, a bank pattern is formed on the substrate 100 on which the first electrode 230 is formed. The bank patterns 139 may be formed in the display region and not in the non-display region. In addition, the first electrode 230 may be exposed in the display area.

An organic light emitting layer 135 is formed on the exposed first electrode 230. Further, a second electrode 136 of the organic light emitting device is formed on the organic light emitting layer 135. Here, the first electrode 230 may be an anode electrode, and the second electrode 136 may be a cathode electrode. Although not shown in the drawings, an auxiliary electrode may be formed on the display region together with the first electrode 230 to lower the voltage drop of the second electrode 136.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

100: substrate
140: first pad electrode
150: second pad electrode
170, 270: encapsulation pattern
Tr: thin film transistor
OL: Organic light emitting device

Claims (21)

A substrate divided into a display area and a non-display area;
A gate wiring formed on the substrate in one direction and a data wiring crossing the gate wiring;
A thin film transistor disposed on the display region and formed in an intersection region of the gate wiring and the data wiring;
An organic light emitting element disposed on the thin film transistor, the organic light emitting element including a first electrode, an organic light emitting layer, and a second electrode; And
And a pad portion disposed on the non-display region,
Wherein the pad portion includes a pad electrode connected to the gate wiring or the data wiring, and a sealing pattern is disposed at a connection portion between the pad electrode and the gate wiring or the data wiring.
The method according to claim 1,
Wherein the sealing pattern disposed at a connection portion between the pad electrode and the gate wiring or the data wiring is arranged to extend in a direction perpendicular to the gate wiring or the data wiring.
The method according to claim 1,
Wherein the sealing pattern is disposed only at a connection portion between the pad electrode and the gate wiring or the data wiring and is disposed in a plurality of island patterns.
The method according to claim 1,
Wherein the sealing pattern is formed of an insulating material.
5. The method of claim 4,
Wherein the sealing pattern is formed as a sealant.
5. The method of claim 4,
And a filler is further disposed between the sealing pattern and the gate wiring or the data wiring.
The method according to claim 6,
Wherein the filler includes a getter.
The method according to claim 1,
Wherein the sealing pattern is formed of a transparent conductive material.
9. The method of claim 8,
Wherein the sealing pattern comprises ITO.
9. The method of claim 8,
Wherein the first electrode of the organic light emitting device includes a plurality of electrode layers, and the sealing pattern is formed of the same material as the electrode layer disposed on the uppermost side of the first electrode.
The method according to claim 1,
Wherein the gate wiring or the data wiring is formed by laminating a first wiring layer and a second wiring layer.
12. The method of claim 11,
Wherein the pad electrode is formed of the same material as the gate wiring or the first wiring layer of the data wiring.
13. The method of claim 12,
Wherein the pad electrode is formed of any one selected from the group consisting of moly titanium (MoTi), titanium (Ti), and combinations thereof.
14. The method of claim 13,
Wherein the gate wiring or the second wiring layer of the data wiring includes copper (Cu).
12. The method of claim 11,
Wherein the sealing pattern is disposed so as to be in contact with a side surface of a second wiring layer of the gate wiring or the data wiring.
Forming a thin film transistor in the display region on the substrate divided into a display region and a non-display region, and forming a pad electrode and a dummy layer disposed on the pad electrode in the non-display region;
Forming a protective film on the thin film transistor to expose the dummy layer;
Forming a planarization film on the protective film in the display region;
Forming an electrode material layer on the entire surface of the substrate on which the planarization layer is formed;
Forming a photoresist pattern on the electrode material layer in the display area;
Etching the electrode material layer and the dummy layer using the photoresist pattern and the protective film as masks to form a first electrode in the display region and exposing the pad electrode in the non-display region; And
And forming an encapsulation pattern on the exposed pad electrode.
17. The method of claim 16,
The step of forming the thin film transistor, the pad electrode, and the dummy layer may include:
Forming a semiconductor layer on the substrate;
Forming a gate insulating film on the semiconductor layer;
Forming a gate wiring, a gate electrode, a first pad electrode, and a first dummy layer on the gate insulating layer;
Forming an interlayer insulating film on the gate wiring, the gate electrode, the first pad electrode, and the first dummy layer; And
And forming a data line, a source electrode, a drain electrode, a second pad electrode, and a second dummy layer on the interlayer insulating layer.
18. The method of claim 17,
Wherein the step of forming a protective film to expose the dummy layer,
Forming a protective layer over the entire surface of the substrate including the data line, the source electrode, the drain electrode, the second pad electrode, and the second dummy layer; And
And etching the passivation layer and the interlayer insulating layer to expose the first dummy layer and the second dummy layer.
18. The method of claim 17,
Wherein the sealing pattern is formed at a connection portion between the first pad electrode and the gate wiring and a connection portion between the second pad electrode and the data wiring.
20. The method of claim 19,
The step of forming the sealing pattern may include:
Wherein the sealing pattern includes a step of applying a substance to a connecting portion between the first pad electrode and the gate wiring and a connecting portion between the second pad electrode and the data wiring.
20. The method of claim 19,
The step of forming the sealing pattern may include:
Forming a transparent conductive material on the entire surface of the substrate on which the first electrode is formed;
Forming a photoresist pattern on the connection portion of the first pad electrode and the gate wiring, the connection portion of the second pad electrode and the data wiring, and the first electrode; And
And etching the transparent conductive material using the photoresist pattern as a mask.

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