KR20150108148A - Cache management apparatus and method of using partial reconfiguration - Google Patents

Abstract

Disclosed are a cache control apparatus and a cache management method using a partial association reconfiguration of a cache. The cache control apparatus reconfigures a form of a n-way set association cache and includes: a monitoring unit which monitors a central access region made of sets centrally used among the sets included in the cache; a reconfiguration unit which partially reconfigures the cache based on the number of the sets corresponding to the central access region and the number of ways of the cache; and an assignment unit which assigns an address space of a main memory mapped in the central access region with the reconfigured parts of the cache.

Description

[0001] CACHE MANAGEMENT APPARATUS AND METHOD OF USING PARTIAL RECONFIGURATION [0002]

The present invention relates to a cache control apparatus and a method thereof, and more particularly, to a cache control apparatus and method used in a multi-core microphone platform.

The cache (CACHE) is a high-speed memory located between the processor of the computer and the main memory, operating at a speed corresponding to the processor. The cache may store a portion of the data stored in the main memory, and the data stored in the cache may be accessed more quickly than the data stored in the main memory. This cache can mitigate bottlenecks caused by speed differences between fast processors and slower main memory.

Cache has a big impact on the performance of computer systems. Recently, as the development of process technology has been actively pursued to use various kinds of memories such as DRAM and PCRAM as caches by using TSV (Through Silicon Via), it is expected that the size of caches will continue to increase in the future. Large caches are required to accommodate the memory access patterns of various applications, but the increase in cache size causes an increase in circuit area and power consumption.

Observing the entry utilization of a large-sized cache reveals that a set of all areas is not used uniformly, and a set of specific areas is intensively used and a data miss occurs. Also, the set of specific areas has a spatial correlation due to the spatial locality of the data.

To solve the problem of data misreading in the cache, the cache generally uses a set associative mapping method. The set associative mapping cache has a fixed number of locations (e.g., at least two) in which each block of main memory can be placed. That is, the set associative cache having n possible positions for each block of memory is called an n-way set associative cache.

The n-way set associative cache consists of a number of sets of n blocks each. Each block on the main memory is mapped into a set on the cache by an index field, and all entries in the set are compared to find a match with the requested data from the processor.

However, as the number of associations increases, the number of entries to access matching entries at the same time increases, so the power consumption of the cache increases and the retrieving latency increases. Therefore, it is difficult to expect high cache efficiency.

In an embodiment of the present invention, only a specific entry of a cache memory having a large capacity is used intensively so as to alleviate a phenomenon that a large portion of the cache memory is not used and wasted.

A cache control apparatus and a cache management method for reducing a miss rate of a cache by partially reconstructing a cache based on the number of sets of caches to be intensively accessed and the number of ways of caches are provided.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

In order to accomplish the above object of the present invention, there is provided a reconfiguration cache control apparatus for reconfiguring a form of an n-way set associative cache according to an aspect of the present invention. The cache control apparatus includes a n-way (n is a natural number of 1 or more) A monitoring unit for monitoring a centralized access region composed of sets used intensively among the sets included in the cache; a monitoring unit for monitoring the number of sets corresponding to the centralized access region, A reconfiguration unit that partially reconfigures the cache based on the number of ways of the cache, and an allocator that allocates the address space of the main memory mapped to the concentrated access area to the reconstructed part of the cache.

The reconstruction unit arbitrarily selects at least one way of the n-way of the cache, and reconstructs the selected way based on the number of sets corresponding to the concentrated access area.

The allocating unit replaces data stored in the set corresponding to the concentrated access area with data requested from the processor core when the miss rate of the concentrated access set is equal to or greater than a preset miss rate.

The allocator allocates the address space of the main memory causing the data contention among the addresses of the main memory mapped to the set corresponding to the concentrated access area to the reconstructed portion of the cache.

In another aspect of the present invention, there is provided a reconfiguration cache control method for reconfiguring a form of an n-way set associative cache, the method comprising: monitoring a concentrated access area, which is a set of intensively used sets, Partially reconstructing the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache and allocating an address space of the main memory mapped to the centralized access area to the cache To the reconstructed portion.

Partially reconfiguring the cache includes arbitrarily selecting at least one of the n-ways of the cache and reconstructing the selected ways based on the number of sets corresponding to the centralized access area.

Wherein the step of assigning to the address space of the main memory includes the steps of: obtaining a miss rate of the number of sets corresponding to the concentrated access region; and, when the miss rate of the sets corresponding to the concentrated access region is equal to or greater than a predetermined rate, And replacing the data stored in the sets corresponding to the concentrated access area with data requested from the processor.

According to the present invention as described above, there is an effect of reducing the cache miss ratio by partially reconstructing the cache.

In addition, there is an advantage in that overhead and power consumption are reduced, thereby improving the performance of the computer system, by allocating an address space in the main memory that causes actual data contention in the reconstructed cache.

FIG. 1 is a schematic diagram of a multicore processor system including a cache control apparatus according to an embodiment of the present invention. Referring to FIG.
2 is a diagram showing a configuration of a cache.
3 is a configuration diagram of a cache control apparatus according to an embodiment of the present invention.
4 is a diagram illustrating an example of a cache and a main memory mapping according to an embodiment of the present invention.
5 is a diagram illustrating a partial reconfiguration of a cache in accordance with one embodiment of the present invention.
FIG. 6 illustrates an example of allocating an address space that causes actual data contention in a reconstructed portion of a cache according to an embodiment of the present invention.
7 is a flowchart illustrating a cache management method according to an embodiment of the present invention.

In the present invention, in order to increase the utilization of the cache, when an occurrence of a centralized access region in the cache occurs, the cache is partially accessed based on the number of sets included in the centralized access region and the number of ways of the cache. To a cache control apparatus and a cache management method for reducing a miss rate of a cache.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. And is intended to enable a person skilled in the art to readily understand the scope of the invention, and the invention is defined by the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that " comprises, " or "comprising," as used herein, means the presence or absence of one or more other components, steps, operations, and / Do not exclude the addition. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 is a schematic diagram of a multicore processor system including a cache controller according to an embodiment of the present invention. Referring to FIG.

Figure 1 is an illustration of an example of a multicore processor 100 system and does not limit the physical location of the blocks shown in Figure 1. [ The design choices can be adjusted, for example, by consideration of hardware size and complexity versus performance, thermal energy and heat dissipation, processor speed, overall throughput, and the like. Those skilled in the art will appreciate that multicore processor 100 may be provided in a suitable computing environment, such as a personal computer (PC).

1, a multicore processor system includes a multicore processor 100 and a main memory 140. The multicore processor 100 includes a processor core array 110, a cache 120, a cache 120, And a control device 130.

The multicore processor 100 system may include a single integrated circuit having a processor core array 110.

The processor core array 110 includes a plurality of processor cores 111 (1) to 111 (N). Each of the processor cores 111 (1) through 111 (N) includes any desired configuration including, but not limited to, a microprocessor (uP), a microcontroller (uC), a digital signal processor (DSP), or any combination thereof. Lt; / RTI > Thus, each of the processor cores 111 (1) through 111 (N) may be coupled to other processor cores such as an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing (DSP) core, a register, an accumulator, Functional block as well as logic for executing program instructions. All or only a portion of each of the processor cores 111 (1) through 111 (N) may include a cache memory (not shown).

The cache 120 is a high-speed storage device in which instructions or programs requested from the processor cores 111 (1) to 111 (N) are stored. Accordingly, the processor cores 111 (1) to 111 (N) access the cache 120 to retrieve frequently used data or program instructions. Data and program instructions frequently accessed by the processor cores 111 (1) to 111 (N) are stored in the cache 120 so that the processor cores 111 (1) to 111 (N) .

The cache 120 may be implemented as a volatile or non-volatile memory device. For example, cache 120 may be implemented with, for example, a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, or a flash memory device. The cache 120 may be shared by some or all of the processor cores 111 (1) through 111 (N).

If the data requested by the processor cores 111 (1) through 111 (N) can be found in the cache 120, this is called a hit. On the other hand, if the data requested by the processor cores 111 (1) to 111 (N) can not be found in the cache 120, this is called a miss. When a miss occurs, the processor cores 111 (1) to 111 (N) access the main memory 140 to find a block containing necessary data.

The hit rate of the cache 120 is the access rate of the processor cores 111 (1) to 111 (N) that can be found in the cache 120 and the hit rate is used to evaluate the performance of the cache 120 . The miss rate refers to the access rate of the processor cores 111 (1) to 111 (N) that can not be found in the cache 120.

Cache controller 130 may be configured to reduce the miss rate of cache 120,

Monitoring a centralized access region comprised of sets of heavily used ones of the sets contained in the cache to determine the number of sets assigned to the centralized access region and the number of ways of the cache, Partially reconstructed. In addition, the cache controller 130 allocates the address space of the main memory, which is mapped to the centralized access area, to the reconstructed portion of the cache.

The main memory 140 stores programs and various data and commands necessary for driving the processor cores 111 (1) to 111 (N). The main memory 140 may be a volatile memory such as a DRAM device or an SRAM device, a non-volatile memory such as a read only memory (ROM) device or a flash memory device, a data storage device such as a magnetic disk storage device , Tape storage devices, optical storage devices (e.g., compact discs or CDs, digital versatile discs or DVDs), or other machine-readable storage media that may be removable, non-removable, volatile or non- Type memory.

For better understanding of the embodiment of the present invention, the cache operation will be described in more detail with reference to FIG.

2 is a diagram showing a configuration of a cache. The cache 120 includes an index selection unit 210, a cache tag array 220, a comparison unit 230, a cache data array 240, a data selection unit 240, and a multiplexer (MUX) 260 .

The accesses of the processor cores 111 (1) to 111 (N) to the cache 120 may be made in units of data blocks. Specifically, the unit of cache 120 access may be a data block, and cache 120 may store one or more blocks of data. Basically, the data block is stored in the main memory 140. The storage of the particular data block may be restricted to specific ones of the entire slots used by the cache 120 in the cache 120 for storing specific data blocks. Specifically, the address space of the main memory 140 storing the data block may be mapped to the cache 120 based on the address of the data block.

The index selection unit 210 selects the position of the index field 14 among the data addresses 10 requested to access from the processor cores 111 (1) to 111 (N) . Specifically, the index selection unit 210 selects the position of a bit to be used as the index 14 on the data address 10 requested from the processor cores 111 (1) to 111 (N) according to the size of the input / output unit do.

The data address 10 requested from the processor cores 111 (1) to 111 (N) includes a tag field 12, an index field 14 and an offset field 16.

The tag field 12 is used to identify whether the data block stored in the location on the cache 120 mapped by the index field 14 matches the data block of the address that is currently accessed.

The index field 14 determines the location at which the data block of the main memory 140 is mapped onto the cache 120. Where the location may represent one set corresponding to the index field 14 of one or more sets of the cache 120. For example, if the index field 14 is i bits, the number of locations where data blocks can be mapped on the cache 120 may be 2 i. Specifically, if the value of the index field 14 of the data address 10 is x, the data block may be mapped to the xth set of cache. It can be identified by the tag field 12 and the index field 14 that the data blocks stored in the cache are data blocks of which address among the address spaces of the main memory.

The offset field 16 may be the least significant bits other than the index field 14 and the tag field 312. The offset field 16 may be any one of the bits of the address indicating the location of the address space of the main memory 140, and may be non-mapping bits between positions on the data block and on the cache. The size of the offset field 16 may correspond to the size of a data block that is an access unit of the cache. For example, if the offset field (16) is j bits, the size of the data block is 2 ^j byte (byte), n2 ^j byte (byte) 2 or ^j Word or the like. In the above description, i, j and n may each be an integer of 0 or more.

The size of the data address 10, the size of the tag field 12, the size of the index field 14 and the size of the offset 16 may be determined depending on the computer system including the cache or cache.

A set corresponding to the data block of the main memory 140 among the sets in the cache data array 250 is determined by the index field 14 among the data addresses 10. [ Once the set in the cache data array 250 is determined by the index field 14, one way of the selected set of ways may be used for access to the data block. Here, the access may include the storage of data blocks. For example, a data block may be stored in a way selected by an empty way or a cache policy of the set of ways determined by the index field 14.

The cache tag array 220 stores tags for data blocks in main memory. The cache tag array 220 may be divided into M sets and N ways. Specifically, the set of data blocks in the set in the cache tag array 220 is determined by the index field 14 of the data address 10. For example, in the jth column of the i-th row of the cache tag array 220, the tag 12 for the data block stored in the i-set's j-way of the cache data array 220 is stored.

The comparing unit 230 compares the tags stored in the cache tag array 220 and the tag field 12 values of the data address 10. Assuming, for example, that the set of cache tag arrays 220 determined by the index field 14 of the data address 10 is the first set 221, the comparator 230 may compare the first set of cache tag arrays 220 For each tag stored in the N ways of the tag 221, the value of each of the stored tags and the tag field 12 of the data block address 10 are compared. The above comparison can be made simultaneously for the stored tags. If the comparison result shows that the tag stored in the second way, one of the N ways of the first set 221, has the same value as the tag field 12 of the data address 10, a cache hit do. On the other hand, as a result of the above comparison, if there is no value equal to the tag field 12 value of the data block address 10 among the values of the tags stored in the N ways of the first set 221, a cache miss do.

The data selection unit 240 determines whether or not a cache hit occurs based on a result obtained by ANDing the comparison result obtained from the comparison unit 230 and the cache hit condition. The data selector 240 controls the output of the cache data array 250 according to the cache association. Specifically, the data selector 240 may output at least one way among a plurality of ways of a selected set of the cache data array 240, and the number of the at least one way may be determined by the number of associations of the cache Can be determined.

The set corresponding to the data block of the main memory 140 is determined by the index field 14 among the sets in the cache data array 250. [ Once the set in the cache data array 250 is determined, one of the selected set of ways is used for access to the data block. The cache data array 250 may be divided into m rows and n columns. In one example, the Ith row of the cache data array 250 may correspond to an I-set, and the Jth column may correspond to a J-way.

When a cache hit signal is obtained from the data selection unit 240, the MUX 260 outputs the way designated by the signal of the data selection unit 240 among one or more ways of the set selected by the index selection unit 210 To the processor cores 111 (1) to 111 (N). On the other hand, when the MUX 260 acquires a cache miss signal from the data selector 240, the MUX 260 outputs an access signal to the main memory 140 for the data address 10. [

3 is a configuration diagram of a cache control apparatus according to an embodiment of the present invention.

3, the cache control apparatus 130 for reducing a miss rate of the cache 120 includes a monitoring unit 131, a reconfiguring unit 133, and an allocating unit 135. [

The monitoring unit 131 monitors a concentrated access area consisting of sets used intensively among the sets included in the cache. Herein, the concentrated access area may mean a set in which the access frequency of the sets included in the cache is equal to or greater than a preset access frequency.

The reconfiguration unit 133 partially reconstructs the cache based on the number of sets corresponding to the concentrated access area and the number of ways of the cache from the monitoring unit 131. [ For example, the reconfiguration unit 133 may arbitrarily select one of the n-way (where n is a natural number of 1 or more) of the cache, reconstruct the selected way to the number of sets corresponding to the concentrated access region, At least one of the ways is arbitrarily selected, and the selected ways are reconstructed into the number of sets corresponding to the concentrated access area.

The allocating unit 135 maps the address space of the main memory causing the data contention among the address spaces of the main memory mapped to the set corresponding to the dense access area to the reconstructed part of the cache.

4 is a diagram illustrating an example of a cache and a main memory mapping according to an embodiment of the present invention.

4, a set of 4-way associative caches 410 and sets contained in the 4-way associative cache 410 are allocated to the address space of the main memory 420, As shown in Fig.

If monitoring the access frequencies of the processor cores 111 (1) to 111 (N) with the sets included in the cache 410 via the monitoring unit 131 according to the embodiment, It can be seen that the accesses of the processor cores 111 (1) to 111 (N) are concentrated only on the specific sets 411 without accessing the processor cores 111 (1) to 111 (N). The monitoring unit 131 monitors the access frequency and the like from the sets of processors contained in the cache from the processor cores 111 (1) to 111 (N), and sets the access frequency to a set It is determined whether or not the concentrated access area 411 has occurred. Generally, because of the spatial correlation due to the spatial locality of the main memory data allocated to the centralized access area 411, the sets constituting the centralized access area 411 are located adjacent to each other.

The central access address area 411 may be mapped to the main memory address space MAS0 (0 to 128) and the main memory address space MAS1 (1024 + 1 to 1024 + 128), and MAS2 (2048 + 1 to 2048 + 128).

In the case of the four-way associative cache 410 according to the embodiment shown in FIG. 4, each address space of the main memory 140, when mapped to the cache 410, has four selectable cache tags I have.

5 is a diagram illustrating a partial reconfiguration of a cache in accordance with one embodiment of the present invention.

The cache controller 130 partially re-configures the cache based on the number of sets constituting the centralized access area 510 and the number of ways of the cache to reduce the miss rate of the cache .

At this time, the reconfiguring unit 133 may arbitrarily select one of the n-ways of the cache, and reconfigure the selected way to the number of sets constituting the dense access area 510. For example, the reconstruction unit 133 may arbitrarily select one way (for example, four ways) of the four ways in the four-way partial associative cache as shown in FIG. 5, Reconfigure the selected way according to the number. Specifically, in the illustrated embodiment, the reconstruction unit 133 selects one way consisting of nine sets and determines three ways (e.g., three ways) according to the number of sets (e.g., three) (520).

The form of the reconstructed cache may vary depending on the nature of the centralized access area 510. Here, the property of the centralized access region 510 means the number of sets corresponding to the centralized access region 510. In the illustrated embodiment, since the number of sets corresponding to the concentrated access area 510 is 3, the reconstructed part 520 has three sets of one way and has a total of three associativity.

As another example, when the number of sets corresponding to the concentrated access region among the eight-way sets is two, the reconstruction unit 133 may set eight sets included in one way And reconstructs into two sets, the number of sets constituting the concentrated access area. Then, the cache is reconfigured into four ways of two sets. At this time, the reconstructed part of the cache has two sets of one way, and has a total of two associations. In an embodiment, the number of ways selected to be reconfigured is arbitrarily set according to the number of associations in the cache and the number of sets included in the way at the time of cache design.

In addition, the reconfiguration unit 133 may arbitrarily select at least one of the n-ways of the cache, and reconstruct the selected ways with the number of sets corresponding to the concentrated access region. For example, when a centralized access area corresponding to three sets occurs in the 4-way 9-set cache, the reconfiguring unit 133 selects any two ways and selects each of the selected ways as the number of sets constituting the concentrated access area, Can be reconstructed. In the embodiment, the two ways selected by the reconstruction unit 133 are reconstructed into a total of six ways. Therefore, after the partial reconfiguration by the reconfiguration unit 133, the cache has a total of nine ways.

FIG. 6 illustrates an example of allocating an address space that causes actual data contention in a reconstructed portion of a cache according to an embodiment of the present invention.

As shown in FIG. 6, the address space of the main memory 610 includes address spaces MAS0 to MAS5 that are mapped to sets constituting the central access area.

The address space MAS0 to MAS5 mapped to the set constituting the access area includes address spaces MAS0 and MAS3 which cause a serious data contention in the cache due to a large number of accesses and addresses spaces MAS1, MAS2, and MAS4 , MAS5).

The storage space of the cache memory 620 includes a portion 621 to which address spaces MAS0 and MAS3 are mapped and a portion 623 to which other address spaces MAS1, MAS2, MAS4, and MAS5 are mapped, . The portion 621 to which the address space MAS0, MAS3 causing the severe data contention is mapped includes the portion 60 reconstructed by the reconstruction portion 133. [

In the embodiment, the reconstruction unit 133 selects one way including nine sets, and reconstructs one way into three ways according to the number of sets (three) corresponding to the approach area. Thus, as shown in the reconstructed portion 60, one way selected by the reconstruction unit 133 is reconstructed into three ways with three sets.

According to the embodiment of the present invention, when the main memory 610 address space (MAS0, MAS3) in a highly contested area due to a lot of data accesses is mapped to the cache 620, the main memory addresses MAS0, MAS3 are mapped to the storage space 621 of the cache 620 including the reconstructed portion 60 of the cache 620. [ When the main memory 610 address space MAS0, MAS3 is mapped to the cache 620, the number of ways of the allocated cache 620 increases.

More specifically, in the embodiment, when the address space MAS0 and MAS3 of the main memory 610 are mapped to the cache 620, a tag mapped to the main memory addresses MAS0 and MAS3, . Due to the tag being increased due to the reconfiguration of the cache, it is possible to reduce the cache miss rate by storing the data in the cache that receives a lot of requests from the processor cores 111 (1) to 111 (N).

In addition, in order to reduce the cache miss rate, the allocator 135 selectively allocates the main memory 610 address space to the reconstructed portion 60 of the cache. Specifically, the allocating unit 135 allocates the reconfigured portion 60 to the address spaces MAS0 and MAS3 causing actual data contention. In addition, the allocating unit 135 modifies the replacement policy of the cache 620 to reduce the cache miss rate, and replaces the data stored in the specific set when the specific set of the concentrated access sets exceeds the preset mistake rate .

Here, the replacement policy of the cache 620 means that the processor cores 111 (1) to 111 (N) access the cache in a state where all the sets of the cache are filled with data, , It removes data from a particular set of caches and fetches new data blocks from main memory 140. When a cache miss occurs, the data block to be accessed may first be stored in the cache. If there is no free space in the cache that can be used for storage of the data block, the data block must be replaced with another data block already stored in the cache. A block of data that is released from the cache through a replacement due to a cache miss is referred to as a victim. The victim can be determined according to the Cache Replacement Policy. The replacement policy determines how data is removed from a set of caches. Common replacement policies include Least Recently Used (LRU), Least Frequently Used (LFU), First in First Out (FIFO), and Random.

In addition, the allocating unit 135 allocates the address spaces MAS1, MAS2, MAS4, and MAS5 of the main memory, which are mapped to the sets corresponding to the concentrated access region excluding the regions with high contention, Can be mapped.

As a result, the allocating unit 135 allocates the main memory spaces MAS0 and MAS3 in the region where the data contention is severe to the region 621 including the reconfigured portion 60 of the cache, By decreasing the cache miss rate by increasing the way of the cache allocated to the cache.

7 is a flowchart illustrating a cache management method according to an embodiment of the present invention. Hereinafter, a cache management method according to an embodiment of the present invention will be described in detail with reference to FIG.

The monitoring unit 131 monitors a concentrated access area consisting of sets used intensively among the sets included in the cache (S710). For example, in step S710, the monitoring unit 131 monitors the usage patterns of the respective sets included in the cache for a predetermined time, (1) to 111 (N)).

The monitoring unit 131 determines whether a concentrated access region composed of the intensively used sets occurs (S720). For example, in step S720, the monitoring unit 131 determines whether a concentrated access area with an access frequency equal to or higher than a predetermined access frequency occurs.

The reconfiguration unit 133 partially reconstructs the cache based on the number of sets corresponding to the concentrated access area and the number of ways of the cache (S730). For example, in step S730, the reconfiguration unit 133 partially reconstructs the cache based on the number of sets corresponding to the concentrated access area and the number of ways of the cache. At this time, the reconfiguring unit 133 arbitrarily selects one or a plurality of ways of the n-way of the cache, and reconstructs the selected way with the number of sets corresponding to the concentrated access area.

The allocating unit 135 allocates the address space of the main memory causing the data contention among the addresses of the main memory mapped to the sets corresponding to the dense access area to the reconstructed part of the cache at step S740. At this time, in step S740, the assigning unit 135 acquires the miss rate of the centralized approach set, and when the obtained rate of miss of the centralized approach set is equal to or greater than a preset miss rate, It can be replaced with data requested from the cores 111 (1) to 111 (N).

The above description with reference to Figs. 1 to 6 can also be applied to the embodiment of Fig. Duplicate description is omitted.

A cache control apparatus and method according to an embodiment of the present invention is characterized by an advantage of reducing the cache miss rate by partially reconstructing the cache based on the number of sets corresponding to the concentrated access area and the number of ways of the cache .

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

Claims (7)

(n is a natural number equal to or greater than 1) set associative cache in a cache,
A monitoring unit for monitoring a concentrated access area consisting of sets used intensively among sets included in the cache;
A reconstruction unit that partially reconstructs the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache,
An allocation unit for allocating an address space of a main memory mapped to the concentrated access area to a reconstructed part of the cache,
And a cache control unit.
The apparatus of claim 1, wherein the reconstruction unit
Ways of the n-way of the cache, and reconstructs the selected way based on the number of sets corresponding to the concentrated access area
In cache control device.
2. The apparatus of claim 1, wherein the allocator
And replacing data stored in the set corresponding to the concentrated access area with data requested from the processor core when the miss rate of the concentrated access set is equal to or greater than a preset miss rate
In cache control device.
2. The apparatus of claim 1, wherein the allocator
Assigning an address space of a main memory that causes data contention among the addresses of the main memory mapped to the set corresponding to the centralized access area to the reconstructed portion of the cache
In cache control device.
Method for reconfiguring the form of an n-way set associative cache A method for controlling a cache,
Monitoring a centralized access area comprising sets of heavily used ones of the sets contained in the cache;
Partially reconstructing the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache,
Assigning an address space of a main memory mapped to the centralized access area to a reconstructed portion of the cache
Lt; / RTI >
6. The method of claim 5, wherein partially restructuring the cache further comprises:
Arbitrarily selecting at least one of the n-ways of the cache and
Reconstructing the selected ways based on the number of sets corresponding to the concentrated access area
The cache management method comprising:
6. The method of claim 5, wherein allocating to the address space of the main memory
Obtaining a miss rate of the number of sets corresponding to the centralized access area and
Replacing the data stored in the sets corresponding to the concentrated access area with data requested from the processor when the miss ratio of the sets corresponding to the acquired concentrated access area is equal to or greater than a preset mis-
The cache management method comprising:

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