KR20150059058A - User device having host ftl and method for transfering page offset of open block thereof - Google Patents

Abstract

A user device according to an embodiment of the present comprises a storage device based on a flash memory; and a host connected with the storage device through an interface, and transmitting data to the storage device, wherein the host provides page offset information of an open block of the flash memory to the storage device, before sending a reading command, when satisfying a specific condition. The user device according to an embodiment of the present invention transmits page offset of an open block from the host to the storage device, thereby improving performance of the storage device, and assuring reliability.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a user device having a host FTL and a method of transmitting a page offset of an open block thereof.

The present invention relates to a user device, and more particularly to a user device having a host flash translation layer (FTL) and a method for transmitting a page offset of an open block thereof.

A storage system is composed of a host and a storage device and includes a universal flash storage (UFS), a serial ATA (SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS) eMMC (embedded MMC), and the like.

The storage device is connected to the host through an interface. The storage device may include a non-volatile memory such as flash memory, MRAM, PRAM, FeRAM, and the like. A storage device based on a flash memory efficiently utilizes the characteristics of a flash memory using a flash translation layer (FTL).

Meanwhile, as the process of the storage device is gradually shrinked and the characteristics of the storage device become worse, various schemes are being developed to guarantee reliability for each storage device. In particular, a user device that manages the FTL in a host needs to provide the storage device with the necessary information to improve the performance of the storage device and ensure reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned technical problems, and it is an object of the present invention to provide a user device for managing FTL in a host, in which, in order to improve the performance of a storage device and ensure reliability, The page offset of the page offset.

A user device according to an embodiment of the present invention includes a storage device based on flash memory; And a host connected to the storage device via an interface and transmitting data to the storage device, wherein the host provides page offset information of an open block of the flash memory to the storage device.

In an embodiment, the host provides the page offset information of the open block to the storage device if the specific condition is satisfied. The specific condition may be a case where the read target block is an open block, a first read after the user device is initialized, a case where the read target block is an open block, a memory block is changed in the same CAU, Is the open block and the page offset of the read target block is changed.

In another embodiment, the host provides the page offset command field format of the open block to the storage device prior to sending the read command field format. The page offset command field format of the open block includes a read command mark, a storage address format, and a read command and mark. The storage address format includes a read hint area and a page offset area. The page offset command field format and the read command field format are determined by the read hint area. The host includes a buffer RAM for driving the Host FTL.

Another aspect of the present invention relates to a method of transmitting a page offset of an open block of a user equipment. The user device includes a host connected to the storage device via a storage device based on a flash memory. A method of transmitting a page offset of an open block of a user equipment comprises the steps of: the host providing page offset information of an open block to the storage device when a specific condition is satisfied; And providing the read command to the storage device after providing the page offset information of the open block.

A user device according to an embodiment of the present invention transmits a page offset of an open block from a host to a storage device, thereby improving the performance of the storage device and ensuring reliability.

1 is a block diagram showing a user equipment.
2 is a block diagram illustrating a user device based on a flash memory.
3 is a block diagram illustrating an exemplary flash memory shown in FIG.
4 is a circuit diagram illustrating an exemplary memory block shown in FIG.
5 is a diagram showing a threshold voltage distribution of the memory cell shown in FIG.
FIG. 6 is a block diagram illustrating the command field format of the user equipment shown in FIG. 2. FIG.
FIG. 7 is a conceptual diagram for explaining an open block in the memory block of the flash memory shown in FIG. 3. FIG.
FIG. 8 is a block diagram showing a more detailed storage address format of the read command field format shown in FIG.
9 is a block diagram illustrating a page offset transmission method of an open block in a user equipment according to an embodiment of the present invention.
FIG. 10 is a conceptual diagram for explaining a specific embodiment of the page offset transmission method shown in FIG.
11 is a conceptual diagram showing an example in which a normal read operation is performed when the read hint area is set to 0;
12 is a block diagram exemplarily showing a three-dimensional flash memory used in the present invention.
13 is a perspective view exemplarily showing a three-dimensional structure of the memory block BLK1 shown in FIG.
14 is an equivalent circuit diagram of the memory block BLK1 shown in Fig.
FIG. 15 shows an example in which a storage device of a user apparatus according to an embodiment of the present invention is applied to a memory card.
16 is a block diagram showing an example of applying a storage device according to an embodiment of the present invention to a solid state drive (SSD).
17 is a block diagram illustrating an exemplary configuration of the SSD controller 4210 shown in FIG.
18 is a block diagram showing an example of implementing a storage device according to an embodiment of the present invention with an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

Ⅰ. User device with host FTL

1 is a block diagram showing a user equipment. Referring to FIG. 1, a user device 1000 includes a host 1100 and a storage device 1200. The host 1100 and the storage device 1200 may be connected via standard interfaces such as universal flash storage (UFS), serial ATA (SATA), small computer small interface (SCSI), serial attached SCSI (SAS) Can be connected.

Referring to FIG. 1, the host interface 1101 and the device interface 1201 may be connected to a data line (DIN, DOUT) for exchanging data and signals and a power line (PWR) for providing power. The host 1100 includes an application 1110, a device driver 1120, a host controller 1130, and a buffer memory 1140.

Application 1110 is a variety of application programs running on host 1100. The device driver 1120 is for driving peripheral devices connected to the host 1100 and drives the storage device 1200 in FIG. The application 1110 or the device driver 1120 may be implemented through software or firmware. The host controller 1130 provides data to the storage device 1200 or receives data from the storage device 1200 via the host interface 1101. [

The buffer memory 1140 may be used as a main memory or a cache memory of the host 1100. The buffer memory 1140 may be used as a driving memory for driving software such as an application 1110 or a device driver 1120 or firmware such as a host FTL It is possible.

The storage device 1200 may be connected to the host 1100 through a device interface 1201. [ The storage device 1200 includes a non-volatile memory 1210, a device controller 1230, and a buffer memory 1240. The nonvolatile memory 1210 may include a flash memory, an MRAM, a PRAM, and an FeRAM. The device controller 1230 controls overall operations such as writing, reading, erasing, etc. of the nonvolatile memory 1210. The device controller 1230 exchanges data with the nonvolatile memory 1210 or the buffer memory 1240 via an address or data bus.

The buffer memory 1240 may be used to temporarily store data to be stored in or read from the non-volatile memory 1210. [ The buffer memory 1240 may be implemented as volatile memory or non-volatile memory. The buffer memory 1240 may be used as a main memory or a cache memory of the storage device 1200.

The buffer memory 1240 may also include a driving memory for driving software or firmware such as a command manager, a flash manager, an error fix manager, ).

2 is a block diagram illustrating a user device based on a flash memory. The user device 2000 shown in FIG. 2 may be a mobile device such as a smart phone, a tablet PC, an electronic book, a cellular phone, and the like. Referring to FIG. 2, a user device 2000 includes a host 2100 and a storage device 2200.

The host 2100 includes an application 2110, a device driver 2120, a host controller 2130, and a buffer RAM 2140. The host controller 2130 includes a command queue (CMD queue) 2131, a host DMA 2132, and a power manager 2133.

A command (for example, a write command) generated by the application 2110 of the host 2100 and the device driver 2120 is input to the command queue 2131 of the host controller 2130. The command queue 2131 stores commands to be provided to the storage device 2200 in order. The command stored in the command queue 2131 is provided to the host DMA 2132. The host DMA 2132 sends the command to the storage device 2200 via the host interface 2101.

2, the storage device 2200 includes a flash memory 2210, a device controller 2230, and a buffer RAM 2240. The device controller 2230 includes a central processing unit (CPU) 2231, a device DMA 2232, a flash DMA 2233, a CMD manager 2234, a buffer manager 2235, an error fix manager 2235, , 2236, and a flash manager 2237.

Commands input from the host 2100 to the storage device 2200 are provided to the device DMA 2232 via the device interface 2201. [ The device DMA 2232 provides the command input to the command manager 2234. The command manager 2234 is a module that analyzes the command received from the host 2100 and converts the command so as to send the command to the flash memory 2210. The command manager 2234 also allocates a buffer RAM 2240 to receive data through the buffer manager 2235. The command manager 2234 sends a transmission ready signal (READY_TO_TRANSFER) to the host 2100 when the data transfer preparation is completed.

The host 2100 transmits the data to the storage device 2200 in response to the transmission ready signal. Data is transferred to the storage device 2200 through the host DMA 2132 and the host interface 2101. [ The storage device 2200 stores the supplied data in the buffer RAM 2240 through the device DMA 2232 and the buffer manager 2235. The data stored in the buffer RAM 2240 is provided to the flash manager 2237 via the flash DMA 2233. The flash manager 2237 stores data at the corresponding address in the flash memory 2210.

The storage device 2200 sends a response signal (response) to the host 2100 via the interface and notifies the completion of the command when the data transfer and the program necessary for the command are completed. The host 2100 notifies the device driver 2120 and the application 2110 whether or not the command received the response signal has been completed, and ends the operation for the command.

3 is a block diagram illustrating an exemplary flash memory shown in FIG. The flash memory 2210 includes a memory cell array 110, a data input / output circuit 120, an address decoder 130, and a control logic 140.

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block is composed of a plurality of pages. Each page (for example, 111) is composed of a plurality of memory cells. The flash memory 2210 performs an erase operation on a memory block basis and performs a write operation or a read operation on a page basis.

Each memory cell can store one bit of data or two or more bits of data. A memory cell capable of storing one bit of data in one memory cell is called a single level cell (SLC) or a single bit cell. A memory cell capable of storing two or more bits of data in one memory cell is called a multi-level cell (MLC) or a multi-bit cell.

The single-level cell SLC may have an erase state or a program state depending on the threshold voltage. The multi-level cell MLC may have either an erase state or a plurality of program states, depending on the threshold voltage. The flash memory 2210 may have a single level cell and a multilevel cell at the same time.

The data input / output circuit 120 is connected to the memory cell array 110 through a plurality of bit lines BLs. The data input / output circuit 120 receives data (DATA) from the outside at the time of program operation and transmits program data (program data) to the selection page 111. The data input / output circuit 120 reads data from the selected page 111 at the time of a read operation and outputs data (DATA) to the outside.

The address decoder 130 is connected to the memory cell array 110 through a plurality of word lines WLs. The address decoder 130 receives the address ADDR and selects a memory block or page. Here, an address for selecting a memory block is referred to as a block address, and an address for selecting a page is referred to as a page address. Hereinafter, it is assumed that one page 111 of the first memory block BLK1 is selected.

The control logic 140 may control operations such as programming, reading, erasing, etc. of the flash memory 2210. For example, the control logic 140 controls the address decoder 130 to provide the program voltage to the selected word line and controls the data input / output circuit 120, Data can be provided. The control logic 1140 may perform operations such as program, read, erase, etc. according to the control signal CTRL provided from the device controller (see FIG. 2, 2230).

4 is a circuit diagram illustrating an exemplary memory block shown in FIG. Referring to FIG. 4, the memory block BLK1 has a cell string structure. One cell string includes a string selection transistor connected to a string selection line (SSL), a plurality of memory cells connected to a plurality of word lines WL1 to WLn, and a ground selection line (GSL) Lt; RTI ID = 0.0 > a < / RTI > The string selection transistors are connected to bit lines (BL1 to BLm), and the ground selection transistors are connected to a common source line (CSL).

A plurality of memory cells may be connected to one word line (e.g., WLi). The set of memory cells connected to the selected word line WLi and programmed at the same time is called a page. In Fig. 4, the selection page 111 is programmed simultaneously. On the other hand, one page can be divided into a main area for storing main data and a spare area for storing additional data such as parity bits.

5 is a diagram showing a threshold voltage distribution of the memory cell shown in FIG. 5 illustrates a threshold voltage distribution of memory cells in which 2-bit data is stored in one memory cell. 5, the horizontal axis represents the threshold voltage (Vth), and the vertical axis represents the number of memory cells (# of cells). The memory cell may have one of four states (E, P1, P2, P3) depending on the threshold voltage distribution. Here, E represents an erase state. And P1, P2 and P3 represent program states.

FIG. 6 is a block diagram illustrating the command field format of the user equipment shown in FIG. 2. FIG. The command field format is an interfacing standard to be exchanged between the host interface 2101 of the host 2100 and the device interface 2201 of the storage device 2200.

6 shows a program command field format for writing data to the storage device 2200 and a read command field format for reading data from the storage device 2200, Respectively.

Referring to FIG. 6, the host 2100 transmits a program mark to the storage device 2200, which means that it sends information for writing. After transmitting the program mark, a storage address format and program data for specifying the storage location of the data are transmitted. After the program data is transmitted, the host 2100 transmits a program end mark indicating the end of the program. The storage device 2200 internally performs the program operation during the wait busy period.

6, the host 2100 transmits a read command mark (read CMD mark) to the storage device 2200, which means that the storage device 2200 sends information for reading. After transmitting the read command mark (read CMD mark), a storage address format and a read CMD end mark for notifying the data storage position information are transmitted.

After a read CMD end mark is transmitted, the storage device 2200 performs a read operation internally during the wait busy period. Upon completion of the read operation, the host 2100 transmits a data out mark to the storage device 2200, and the storage device 2200 outputs the data to the host 2100.

2, a user apparatus 2000 according to an embodiment of the present invention includes an error correction manager 2236 in a storage device 2200, and a buffer RAM 2140 of a host 2100 stores an FTL translation layer. Because the user device 2000 shown in FIG. 2 drives the FTL in the host 2100, it is necessary to provide various information to the storage device 2200 that affects the performance of the flash memory 2210.

Ⅱ. How to transfer the page offset of the open block of the user device

As the process of a storage device becomes increasingly shrinking and its characteristics become worse, various schemes are being developed to ensure reliability for each storage device. At this time, the page offset of the open block is one of very important information. The present invention can improve the performance of the storage device 2200 and guarantee reliability by transmitting the page offset of the open block from the host 2100 to the storage device 2200. [

FIG. 7 is a conceptual diagram for explaining an open block in the memory block of the flash memory shown in FIG. 3. FIG. An open block is an entire block of memory that is in the process of writing and can be rewritten.

Referring to FIG. 7, the memory block is composed of 64 pages, and the first to fifth pages (page1 to page5) are programmed pages, and the sixth to 64th pages (page6 to page64) It is an unprogrammed page. The fifth page (page 5) is the last programmed page. The page offset refers to the number of the last programmed page. In the example of FIG. 7, the page offset is the fifth page (page 5).

FIG. 8 is a block diagram showing a more detailed storage address format of the read command field format shown in FIG. Referring to FIG. 8, the storage address format may be composed of, for example, 32 bits.

The unused area consists of X bits. The cell type area determines which cell type (eg, SLC or MLC) is to be read, and consists of A bits. A CAU area (concurrently addressable unit area) specifies a data storage location at an upper level such as a chip, a die, and a plane, and is composed of B bits. The block area designates a block number within the CAU, and consists of C bits. The page area specifies the page number within the block, and it consists of D bits. In the above example, the store address format can be composed of 32 bits, which is the sum of X bits and A to D bits.

9 is a block diagram illustrating a page offset transmission method of an open block in a user equipment according to an embodiment of the present invention. FIG. 9 shows a page offset command field format for transmitting a page offset of an open block.

The host 2100 transmits the page offset of the open block to the storage device 2200 using the Host FTL. The storage device 2200 can improve the performance of programs, reads, and the like through page offsets of open blocks, and can further guarantee the reliability of data.

 The host 2100 transmits the read hint information to the storage device 2200 in advance using the page offset command field format before providing the command field format for reading . The read hint information includes page offset information for the memory block to be read. The page offset command field format need not be provided for every read operation, but can only be provided for a read operation to an open block.

Referring to FIG. 9, the page offset command field format may be used in a manner similar to the read command field format. That is, in the page offset command field format, only the read command mark, the storage address format, and the read command end mark can be used in the read command field format. The page offset command field format does not output data after the read command end mark.

The host 2100 transmits a read command mark (read CMD mark) to the storage device 2200 to send information for reading to the storage device 2200. The host 2100 transmits a read command mark (read CMD mark) and then transmits a storage address format and a read CMD end mark for informing the data storage position information.

Continuing with reference to FIG. 9, the storage address format is composed of 32 bits and may include a read hint area and a page offset area.

The read hint area can use 1 bit of the X bits of the unused area. In this case, the unused area consists of X-1 bits, and the read hint area can consist of 1 bit. The cell type area is composed of A bits, the CAU area (concurrently addressable unit area) is composed of B bits, and the block area is composed of C bits. The page area of FIG. 7 is used as a page offset area and may be composed of D bits.

FIG. 10 is a conceptual diagram for explaining a specific embodiment of the page offset transmission method shown in FIG. The host 2100 transmits a page offset command field format in which a read hint area of the storage address format is set to 1 before a read command is provided.

The condition that the read hint command bit in FIG. 9 is set to 1 is expressed by Equation (1).

(⊙ is an and operation, and ∥ is an or operation)

Here, the condition A is a case where the read target block is an open block. Condition B is the first read after the user device is initialized. For example, the condition B is a case where a read operation is performed after the page offset command field format is transmitted, and a power on / off occurs. Condition C is a case where a memory block is changed in the same CAU. That is, the read target block is changed in the same chip or die. Condition D is the case where the page offset of the read target block is changed. For example, the condition D is a case where the read operation is performed after the transmission of the page offset command field format, and the last programmed page offset is changed by executing the program in the corresponding memory block.

Referring to FIG. 10, a 04h of the storage address format includes a read hint CMD bit, and a page offset bit finally programmed at 05h may be included. In the example of Fig. 10, the page offset of the open block is the fifth page. The user device (see FIG. 2, 2000) according to the embodiment of the present invention sets the read hint command bit to 1, sets the page offset to the fifth page, And transmits the offset command field format to the storage device 2200.

11 is a conceptual diagram showing an example in which a normal read operation is performed when the read hint area is set to 0; If the condition of Equation (1) is not satisfied, the host 2100 sets the read hint region of FIG. 9 to 0 and performs a normal read operation.

Referring to FIG. 11, a read command bit (read CMD bit) is included in 00h of the storage address format, and a page number to be read may be included in 03h. In the example of Fig. 11, the read target page is the third page. The user apparatus 2000 according to the embodiment of the present invention sets the read command bit to 0, sets the read target page as the third page, and then sets the read command bit to the read command field format To the storage device (2200).

The user apparatus 2000 according to the embodiment of the present invention manages the FTL in the host 2100 and transmits a read hint command to the storage device 2200 before transmitting the read command when the specific condition is satisfied. The read hint command includes the page offset information of the open block. The read hint command has a page offset command field format similar to the read command field format, thereby reducing performance degradation. The storage device 2200 can improve the performance of programs, reads, and the like by using the page offset information transmitted from the host 2100.

Ⅲ. Application examples of the present invention

The user device according to the embodiment of the present invention can be applied not only to a flash memory having a two-dimensional structure but also to a flash memory having a three-dimensional structure.

12 is a block diagram exemplarily showing a three-dimensional flash memory used in the present invention. Referring to FIG. 12, the flash memory 2210 includes a three-dimensional cell array 210, a data input / output circuit 220, an address decoder 230, and control logic 240.

The data input / output circuit 220 is connected to the three-dimensional cell array 210 through a plurality of bit lines BLs. The data input / output circuit 220 receives data (DATA) from the outside or outputs data (DATA) read from the three-dimensional cell array 210 to the outside. The address decoder 230 is connected to the three-dimensional cell array 210 through a plurality of word lines WLs and select lines GSL and SSL. The address decoder 230 receives the address ADDR and selects the word line.

The control logic 240 controls operations such as programming, reading, erasing, etc. of the flash memory 2210. For example, the control logic 240 may cause the program voltage to be provided to the selected word line by controlling the address decoder 230 during program operation, and the data to be programmed by controlling the data input / output circuit 220 .

13 is a perspective view exemplarily showing a three-dimensional structure of the memory block BLK1 shown in FIG. Referring to FIG. 13, the memory block BLK1 is formed in a direction perpendicular to the substrate SUB. An n + doped region is formed in the substrate SUB.

A gate electrode layer and an insulation layer are alternately deposited on the substrate SUB. An information storage layer may be formed between the gate electrode layer and the insulation layer.

When the gate electrode film and the insulating film are vertically patterned in a vertical direction, a V-shaped pillar is formed. The pillar penetrates the gate electrode film and the insulating film and is connected to the substrate (SUB). The interior of the pillar may be a filing dielectric pattern and may consist of an insulating material such as silicon oxide. The exterior of the pillar may be composed of a channel semiconductor in a vertical active pattern.

The gate electrode layer of the memory block BLK1 may be connected to a ground selection line GSL, a plurality of word lines WL1 to WL8, and a string selection line SSL. A pillar of the memory block BLK1 may be connected to the plurality of bit lines BL1 to BL3. 13, one memory block BLK1 is shown to have two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, May be more or less than these.

14 is an equivalent circuit diagram of the memory block BLK1 shown in Fig. Referring to FIG. 14, cell strings CS11 to CS33 are connected between the bit lines BL1 to BL3 and the common source line CSL. Each cell string (for example, CS11) includes a ground selection transistor GST, a plurality of memory cells MC1 to MC8, and a string selection transistor SST.

The string selection transistor (SST) is connected to a string selection line (SSL). The string selection line SSL is divided into first to third string selection lines SSL1 to SSL3. The ground selection transistor (GST) is connected to the ground selection line (GSL). The ground selection line GSL of each cell string is connected. The string selection transistor SST is connected to the bit line BL and the ground selection transistor GST is connected to the common source line CSL.

The plurality of memory cells MC1 to MC8 are connected to the corresponding word lines WL1 to WL8, respectively. A set of memory cells connected to one word line and programmed at the same time is called a page. The memory block BLK1 is composed of a plurality of pages. In addition, a plurality of pages may be connected to one word line. Referring to Fig. 14, word lines (e.g., WL4) of the same height from the common source line CSL are connected in common to three pages.

Meanwhile, the user apparatus according to the embodiment of the present invention can be applied to or applied to various products. A user apparatus according to an embodiment of the present invention can be implemented in an electronic apparatus such as a personal computer, a digital camera, a camcorder, a mobile phone, an MP3, a PMP, a PSP, a PDA and the like. The storage medium of the user device may be implemented as a storage device such as a memory card, a USB memory, a solid state drive (SSD), or the like.

FIG. 15 shows an example in which a storage device of a user apparatus according to an embodiment of the present invention is applied to a memory card. The memory card system 3000 includes a host 3100 and a memory card 3200. The host 3100 includes a host controller 3110 and a host connection unit 3120. The memory card 3200 includes a card connecting unit 3210, a card controller 3220, and a flash memory 3230.

The host 3100 writes data to the memory card 3200 or reads data stored in the memory card 3200. The host controller 3110 transmits a command (for example, a write command), a clock signal CLK generated in a clock generator (not shown) in the host 3100, and data DAT through the host connection unit 3120 And transmits it to the memory card 3200.

The card controller 3220 responds to the write command received via the card connection unit 3210 to transfer data to the flash memory 3230 in synchronization with the clock signal generated in the clock generator (not shown) . The flash memory 3230 stores the data transmitted from the host 3100. [ For example, when the host 3100 is a digital camera, it stores image data.

 16 is a block diagram showing an example of applying a storage device according to an embodiment of the present invention to a solid state drive (SSD). Referring to FIG. 16, the SSD system 4000 includes a host 4100 and an SSD 4200.

The SSD 4200 exchanges signals with the host 4100 through a signal connector 4211 and receives power through a power connector 4221. [ The SSD 4200 may include a plurality of flash memories 4201 through 420n, an SSD controller 4210, and an auxiliary power supply 4220. [

The plurality of flash memories 4201 to 420n are used as the storage medium of the SSD 4200. The SSD 4200 may be a nonvolatile memory device such as a PRAM, an MRAM, a ReRAM, or a FRAM in addition to a flash memory. The plurality of flash memories 4201 to 420n may be connected to the SSD controller 4210 through a plurality of channels CH1 to CHn. One channel may be connected to one or more flash memories. The flash memory connected to one channel can be connected to the same data bus.

The SSD controller 4210 sends and receives the signal SGL to the host 4100 through the signal connector 4211. Here, the signal SGL may include a command, an address, data, and the like. The SSD controller 4210 writes data to the flash memory or reads data from the flash memory according to a command of the host 4100. [ The internal structure of the SSD controller 4210 will be described in detail with reference to FIG.

The auxiliary power supply 4220 is connected to the host 4100 through a power connector 4221. [ The auxiliary power supply 4220 can receive and charge the power source PWR from the host 4100. [ On the other hand, the auxiliary power supply 4220 may be located within the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4220 is located on the main board and may provide auxiliary power to the SSD 4200.

17 is a block diagram illustrating an exemplary configuration of the SSD controller 4210 shown in FIG. 17, the SSD controller 4210 includes an NVM interface 4211, a host interface 4212, an ECC circuit 4213, a central processing unit (CPU) 4214, and a buffer memory 4215.

The NVM interface 4211 scatters the data transferred from the buffer memory 4215 to each of the channels CH1 to CHn. The NVM interface 4211 transfers the data read from the flash memories 4201 to 420n to the buffer memory 4215. Here, the NVM interface 4211 can use the flash memory interface method. That is, the SSD controller 4210 can perform a program, read, or erase operation according to the flash memory interface method.

Host interface 4212 provides interfacing with SSD 4200 in correspondence with the host 4100 protocol. The host interface 4212 is connected to the host (host) 4212 using a USB (Universal Serial Bus), a SCSI (Small Computer System Interface), a PCI express, an ATA, a Parallel ATA (PATA), a Serial ATA 4100). The host interface 4212 may perform a disk emulation function for allowing the host 4100 to recognize the SSD 4200 as a hard disk drive (HDD).

The ECC circuit 4213 generates an error correction code (ECC) using the data transmitted to the flash memories 4201 to 420n. The error correction code (ECC) thus generated is stored in a spare area of the flash memories 4201 to 420n. The ECC circuit 4213 detects an error in the data read from the flash memories 4201 to 420n. If the detected error is within the correcting capacity, the ECC circuit 4213 corrects the detected error.

The central processing unit 4214 analyzes and processes the signal SGL input from the host 4100 (see Fig. 16). The central processing unit 4214 controls the host 4100 and the flash memories 4201 to 420n through the host interface 4212 or the NVM interface 4211. [ The central processing unit 4214 controls the operation of the flash memories 4201 to 420n according to the firmware for driving the SSD 4200.

The buffer memory 4215 temporarily stores write data provided from the host 4100 or data read from the flash memory. The buffer memory 4215 may store metadata or cache data to be stored in the flash memories 4201 to 420n. At the time of the power-off operation, the metadata and the cache data stored in the buffer memory 4215 are stored in the flash memories 4201 to 420n. The buffer memory 4215 may include DRAM, SRAM, and the like.

18 is a block diagram showing an example of implementing a storage device according to an embodiment of the present invention with an electronic device. Here, the electronic device 5000 may be implemented in a personal computer (PC) or a portable electronic device such as a notebook computer, a mobile phone, a PDA (Personal Digital Assistant), and a camera.

18, the electronic device 5000 includes a memory system 5100, a power supply 5200, an auxiliary power supply 5250, a central processing unit 5300, a RAM 5400, and a user interface 5500 . The memory system 5100 includes a flash memory 5110 and a memory controller 5120.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

1000, 2000: User device
1100, 2100: Host
1101, 2101: Host interface
1110, 2110: Application
1120, 2120: Device Driver
1130, 2130: Host controller
1140, 2140: Buffer memory or buffer RAM
1200, 2200: Storage device
1201, 2201: Device interface
1210, 2210: NVM or flash memory
1230, 2230: Device controller
1240, 2240: buffer memory or buffer RAM

Claims (10)

A storage device based on flash memory; And
A host connected to the storage device via an interface and transmitting data to the storage device,
Wherein the host provides page offset information of an open block of the flash memory to the storage device. The method according to claim 1,
Wherein the host provides the page offset information of the open block to the storage device when a specific condition is satisfied. 3. The method of claim 2,
Wherein the specific condition is the case where the read target block is an open block and the first read after the user device is initialized. 3. The method of claim 2,
Wherein the specific condition is a case where the read target block is an open block and the memory block is changed in the same CAU. 3. The method of claim 2,
Wherein the specific condition is a case where the read target block is an open block and the page offset of the read target block is changed. The method according to claim 1,
Wherein the host provides the page offset command field format of the open block to the storage device prior to sending the read command field format. The method according to claim 6,
Wherein the page offset command field format of the open block includes a read command mark, a storage address format, and a read command and mark. 8. The method of claim 7,
Wherein the storage address format comprises a read hint region and a page offset region. 9. The method of claim 8,
Wherein the page offset command field format and the read command field format are determined by the read hint area. The method according to claim 1,
Wherein the host comprises a buffer RAM for driving a Host FTL.

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