KR20150033129A - Semiconductor memory apparatus - Google Patents

Abstract

A semiconductor memory apparatus comprises a memory block connected between a bit line and a source line and including memory cells operated upon voltages applied to word lines; and a surrounding circuit formed to perform operations relating to data input and output of memory cells, wherein the surrounding circuit is formed to apply free charge voltage to the bit line while word lines adjacent to a selected word line are set into a floating state.

Description

Semiconductor memory apparatus < RTI ID = 0.0 >

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a memory cell connected to a word line.

Sufficient current must be secured in order to improve data input / output operation characteristics of the memory cell. However, as the structure of the memory block is changed or the size of the memory cell is reduced, the operating current may decrease and the operating characteristics may deteriorate.

An embodiment of the present invention provides a semiconductor memory device capable of improving operating characteristics.

A semiconductor memory device according to an embodiment of the present invention includes a memory block including memory cells connected between a bit line and a source line and operating according to voltages applied to word lines, and operations related to data input / output of memory cells Wherein the peripheral circuitry is configured to apply a precharge voltage to the bit line while the selected word line and adjacent word lines are set to the floating state.

A semiconductor memory device according to another embodiment of the present invention includes a memory block including memory cells connected between a bit line and a source line and operating according to voltages applied to word lines, Wherein peripheral circuits are configured to apply a pass voltage to a word line adjacent to the selected word line in the direction of the selected bit line and to set the precharge voltage to the bit line in a state where the adjacent word line is set to the floating state .

A semiconductor memory device according to another embodiment of the present invention includes select transistors operating between memory cells operating according to voltages applied to word lines and voltages applied to select lines between a bit line and a source line And a peripheral circuit configured to perform operations related to data input / output of the memory cells, wherein the peripheral circuit turns on the select transistors when applying the pass voltage to the unselected word lines, And turn on the select transistors and turn on the select transistors while setting the unselected word lines to the floating state.

The semiconductor memory device according to the embodiment of the present invention can improve the operation characteristics.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
2A and 2B are circuit diagrams for explaining embodiments of the memory block shown in FIG.
3 is a view for explaining a current flow of a memory cell according to an embodiment of the present invention.
4A to 4E are diagrams for explaining a cell current in a memory string including the memory cell transistor of FIG.
5A to 5G are views for explaining the operation of the semiconductor memory device according to the embodiments of the present invention.
6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above.
8 is a block diagram briefly illustrating a computing system including a flash memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device includes a memory array 110 and peripheral circuits 120 to 160.

The memory array 110 includes a plurality of memory blocks 110MB. The structure of the memory block (110 MB) will be described below.

2A and 2B are circuit diagrams for explaining embodiments of the memory block shown in FIG.

Referring to FIG. 2A, each memory block 110MB includes a plurality of memory strings ST connected between bit lines BL0 to BLk and a common source line CSL. That is, the memory strings ST are connected to the corresponding bit lines BL0 to BLk, respectively, and are connected in common with the common source line CSL. Each memory string ST includes a source select transistor SST having a source connected to the common source line CSL, a cell string having a plurality of memory cells C00 to Cn0 connected in series, and a drain connected to the bit line BL0, And a drain select transistor (DST) connected to the gate of the transistor. The memory cells C00 to Cn0 included in the cell string are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL and the gates of the memory cells C00 to Cn0 are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL).

The drain select transistor DST controls connection or disconnection of the cell strings C00 to Cn0 and the bit line and the source select transistor SST controls the connection between the cell strings C00 to Cn0 and the common source line CSL Or blocking.

In a NAND flash memory device, memory cells included in a memory cell block can be divided into a physical page unit or a logical page unit. For example, memory cells C00 through C0k coupled to one word line (e.g., WL0) constitute one physical page (PAGE). The even memory cells C00, C01, C03, C05 and C0k connected to one word line (e.g., WL0) constitute one even physical page and the odd memory cells C00, C02, C04, C0k -1) can constitute one odd physical page. These pages (or even pages and odd pages) are the basic unit of program operation or read operation.

Referring to FIG. 2B, in the case of a three-dimensional memory block, each memory block 110MB includes a plurality of memory strings ST. For example, in a P-BiCS structure, each memory string ST includes a first memory string MT1 and a bit line BL, which are vertically connected between a common source line CSL and a pipe transistor PTa of a substrate, And a second memory string MT2 vertically connected between the substrate and the pipe transistor of the substrate. The first memory string MT1 includes a source select transistor SST and memory cells C0 to C7. The source select transistor SST is controlled by a voltage applied to the source select line SSLa1 and the memory cells C0 to C7 are controlled by voltages applied to the stacked word lines WL0 to WL7. The second memory string MT2 includes a drain select transistor DST and memory cells C8 to C15. The drain select transistor DST is controlled by a voltage applied to the drain select line DSLa1 and the memory cells C8 to C15 are controlled by a voltage applied to the word lines WL8 to WL8.

The pipe transistor PTa connected between the pair of memory cells C7 and C8 located in the middle of the memory string of the P-BiCS structure is connected to the first memory block 110B included in the selected memory block 110MB when the memory block 110MB is selected And electrically connects the channel layers of the memory string MT1 and the channel layers of the second memory string MT2.

Meanwhile, in the memory block of the 2D structure, one memory string is connected to each bit line and the drain select transistors of the memory block are simultaneously controlled by one drain select line. However, in the memory block 110MB of the 3D structure, A plurality of memory strings ST are connected in common. The number of memory strings ST connected in common to one bit line BL in the same memory block 110 MB and controlled by the same word lines can be changed according to the design.

A plurality of memory strings are connected in parallel to one bit line BL so that the drain select transistors DST are connected to the drain select line DST in order to selectively connect one bit line BL to the memory strings ST, Lt; RTI ID = 0.0 > DSLa1-DSLa4. ≪ / RTI >

The memory cells C0 to C7 of the first memory string MT1 vertically connected to the memory block 110MB and the memory cells C8 to C15 of the second memory string MT2 are connected to the word lines WLa0 to WLa7 ) And the stacked word lines (WLa8 to WLa15), respectively. The word lines WLa0 to WLa15 are divided into memory blocks.

1 and 2A, peripheral circuits 120-160 are configured to perform a program loop, an erase loop, and a read operation of memory cells (C00-C0k) coupled to a selected word line (e.g., WL0) . These peripheral circuits 120 to 160 are configured to perform a program loop, an erase loop, and a read operation under the control of the control circuit 120. [ The peripheral circuits 120 to 160 may supply the operating voltages V1, Vpgm, Vread, Vpass, Vdsl, Vssl and Vsl to the local lines of the selected memory block SSL, WL0 to WLn, DSL and a common source line CSL to control the precharge / discharge of the bit lines BL0 to BLk or to control the current flow of the bit lines BL0 to BLk .

In the case of a NAND flash memory device, the operation circuit includes a control circuit 120, a voltage supply circuit 130, a read / write circuit 140, a column selection circuit 150 and an input / output circuit 160. Each component will be described in detail as follows.

The control circuit 120 generates operation voltages (Verase, Vpgm, Vread, Vpass, and Vdsl) for performing a program loop, an erase loop, and a read operation in response to a command signal CMD input from the outside through the input / , Vssl, Vsl) to be generated at a desired level. The voltage control signal CMD_bias for controlling the voltage supply circuit 130 is output. Then, the control circuit 120 outputs control signals CMD_rw for controlling the read / write circuit 140 to perform a program loop, an erase loop, and a read operation. When the address signal ADD is input to the control circuit 120, the control circuit 120 generates the column address signal CADD and the row address signal RADD, respectively, and the row address RADD is supplied to the voltage supply circuit 130 and the column address CADD is output to the column selection circuit 15. [

The voltage supply circuit 130 responds to the voltage control signal CMD_bias of the control circuit 120 to supply necessary operating voltages (Verase, Vpgm, Vread, Vpass, Vdsl, VSS1 and Vsl and supplies the operation voltages to the local lines SSL, WL0 to WLn and DSL of the selected memory block and the common source line CSL in response to the row address signal RADD of the control circuit 120 Output.

The voltage supply circuit 130 may include a voltage generation circuit 131 and a row decoder 133. The voltage generating circuit 131 generates the operating voltages Verase, Vpgm, Vread, Vpass, Vdsl, Vssl and Vsl in response to the voltage control signal CMD-bias of the control circuit 120, Responds to the row address signal RADD of the control circuit 120 to supply the operating voltages to the local lines SSL, WL0 to WLn, DSL and the common source line CSL of the selected memory block of the memory blocks 110MB, .

As described above, the output and the change of the operation voltages (Verase, Vpgm, Vread, Vpass, Vdsl, Vssl, Vsl) described below are applied to the voltage supply circuit 130 according to the voltage control signal CMD_bias of the control circuit 120 Lt; / RTI >

The read / write circuit 140 is connected to the memory blocks 110MB of the memory array 110 via the bit lines BL0 to BLk. The read / write circuit 140 selectively precharges the bit lines BL0 to BLk according to the control signal CMD_rw of the control circuit 120 and the data (DATA) to be stored in the memory cells during the program operation . The read / write circuit 140 precharges the bit lines BL0 to BLk according to the control signal CMD_rw of the control circuit 120 and then outputs the bit lines BL0 to BLk And senses a voltage change or a current to latch data read from the memory cell.

The column selection circuit 150 sequentially transfers the data from the input / output circuit 160 to the read / write circuit 140 in response to the column address CADD output from the control circuit 120, To the input / output circuit 160 sequentially.

The input / output circuit 160 transmits the command signal CMD and the address signal ADD input from the outside to the control circuit 120. The input / output circuit 160 transfers externally input data (DATA) to the column selection circuit 150 during a program operation or outputs data read from the memory cells during a read operation to the outside.

3 is a view for explaining a current flow of a memory cell according to an embodiment of the present invention.

3, when the gate voltage VG is applied to the gate of the memory cell transistor having the channel length L and the threshold voltage VT and the drain voltage VBL is applied to the drain thereof, the current flowing through the memory cell transistor I) can be expressed as a product of the charge (Q) induced in the channel of the memory cell transistor and the carrier velocity (v). In order to improve data input / output characteristics, the operating current (I) of the memory cell transistor must be increased.

The charge (Q) induced in the channel of the memory cell transistor is proportional to VG-VT-Vch. Here, Vch is the channel electric potential, the source side Vch is 0V, and the drain side Vch is VBL. Therefore, when the same gate voltage VG is applied after the memory cell transistor is programmed so that the threshold voltage VT is high, the cell current I can not be reduced.

The carrier velocity v depends on the electric field (e.g., E = VBL / L) applied to the channel of the memory cell transistor. When the electric field is low, the carrier velocity (v) is proportional to the electric field, but the carrier velocity saturates above a certain electric field. A memory cell transistor of reduced size for high integration is already operating in the short channel region. After the memory cell transistor is programmed, the effective gate voltage VG, eff = VG-VT is lowered, and the drain voltage VBL is not increased to some extent and a pinch-off occurs. As a result, the carrier velocity v becomes saturated.

Therefore, in order to increase the operating current I of the memory cell transistor, saturation of the carrier speed which may occur in the unselected word line is prevented, and the effective gate voltage (VG, eff = VG-VT) The amount of induced charge (Q) must be increased.

4A to 4E are diagrams for explaining a cell current in a memory string including the memory cell transistor of FIG.

Referring to FIG. 4A, the x-axis represents the positions of the transistors included in the memory string, and the y-axis represents the electric potential at each position. A pass voltage Vpass_read is applied to a non-selected word line in the memory string, and a read voltage Vread is applied to the selected word line Sel. For convenience of explanation, it is assumed that all the memory cells are programmed to the highest program level (e.g., PV3) among the program levels (e.g., PV1 to PV3). In this case, the threshold voltage of the memory cell becomes the highest level voltage (VT, PV3).

Under the above conditions, when a specific voltage (Vread) is applied to a word line selected for a read operation (or a verify operation), a channel below the selected word line is pinch-off to perform carrier velocity saturation ). Therefore, in order to secure the operating current in this situation, the charge (Q) induced in the channel must be increased. However, since the voltage Vpass_read applied to the unselected word lines is fixed, the induced charge Q decreases as the drain voltage VBL increases.

Referring to FIG. 4B, when the drain voltage VBL is further increased, the carrier velocity saturation occurs even in the channel of the unselected word line, and the induced charge Q is further reduced.

Referring to FIGS. 4C and 4D, when the voltage applied to the unselected word line is changed according to the channel potential profile (Vch (x)), the amount of charge Q induced in the channel can be secured. When the potential of the unselected word line changes in accordance with the channel potential profile, not only when the drain voltage VBL is low (see FIG. 4C) but also when the drain voltage VBL is high The amount of charge (Q) induced in the channel can be maintained.

In this case, it is difficult to control the potential of the unselected word line in accordance with the channel potential profile (Vch (x)).

When the high drain voltage VBL is applied while controlling the potential of the unselected word line in accordance with the channel potential profile Vch (x), the selected word line Sel.WL and the adjacent unselected word lines Unsel.WL) may generate a hot carrier.

Therefore, by adjusting the voltage applied to the adjacent unselected word lines Unsel.WL so that the electric field decreases in the corresponding area as shown in FIG. 4E, the non-selected word lines (Unsel.WL) adjacent to the memory cell of the selected word line Unsel.WL) may be prevented from being injected into the memory cells.

Hereinafter, embodiments of the present invention capable of changing a voltage applied to a non-selected word line in accordance with a channel potential profile (Vch (x)) will be described.

5A to 5F are diagrams for explaining the operation of the semiconductor memory device according to the embodiments of the present invention.

Referring to FIG. 5A, the peripheral circuits 120 to 160 of FIG. 1 are connected to the bit line BL in a state where the selected word line SEL.WL and the adjacent word lines Unsel.WL are set to the floating state, To apply the voltage VBL. This operation will be described in detail.

First, in the gate bias set-up period, a positive voltage is applied to the drain select line DSL so that the drain select transistor connected between the bit line BL and the memory cell is turned on. Then, a pass voltage VPASS_READ is applied to the word lines Sel.WL and Unsel.WL. That is, the peripheral circuits 120 to 160 of FIG. 1 are connected to the bit line BL and the drain select transistor connected between the bit line BL and the memory cell when the pass voltage VPASS_READ is applied to the word lines Sel.WL and Unsel.WL, Can be turned on. As a result, the word lines (Sel.WL, Unsel.WL) are precharged by the pass voltage VPASS_READ. Also, all the memory cells in the memory string are turned on by the pass voltage VPASS_READ, and the channel regions of the memory cells are electrically connected to the bit line BL.

In the sensing bias setup period, the precharge voltage VBL is applied to the bit line BL and the read voltage VREAD is applied to the selected word line Sel.WL. At this time, the peripheral circuits 120 to 160 of FIG. 1 apply a precharge voltage (" 1 ") to the bit line BL when floating or floating the unselected word lines Unsel.WL adjacent to the selected word line Sel.WL VBL) can be applied. On the other hand, the peripheral circuits (120 to 160 in FIG. 1) can also float the drain select line (DSL) together with the unselected word lines (Unsel.WL).

When the precharge voltage VBL is applied to the bit line BL in a state where the unselected word lines Unsel.WL are floating as described above, a channel potential profile Vch (x) is formed , The potential of the unselected word lines (Unsel.WL) floating by the capacitor coupling phenomenon changes in accordance with the corresponding channel potential profile (Vch (x)).

Therefore, the channel-induced charge difference is maintained by the channel set in the previous gate bias set-up period and the channel induced charge amount is not changed. As a result, the operating current of the memory cell transistor can be stably ensured and the data input / output characteristics can be improved.

Subsequently, in the sensing period, peripheral circuits (120 to 160 in FIG. 1) apply a positive voltage to the source select line SSL so that the source select transistor connected between the memory cell and the common source line CSL is turned on. The peripheral circuit senses the voltage change (or the amount of current) of the bit line BL, latches the data stored in the memory cell, and outputs the latched data.

On the other hand, when the precharge voltage VBL is applied to the bit line BL or the precharge voltage VBL is applied to the bit line BL, VREAD) or a verify voltage can be applied. Further, the peripheral circuit can apply the read voltage VREAD or the verify voltage to the selected word line (Sel.WL) when the adjacent word lines Unsel.WL are floated or after floating.

The timing at which the bit line voltage VBL, the pass voltage VPASS_READ and the read voltage VREAD are applied and the timing at which the positive voltage is applied to the select lines DSL and SSL are described in the embodiments described below The same can be applied.

In the above description, the same pass voltage VPASS_READ is applied to all the unselected word lines Unsel.WL, but different pass voltages are applied according to the positions of the unselected word lines Unsel.WL. 5f.

There are two main reasons for setting the operation mode.

First, when the read voltage VREAD is applied to fetch the information stored in the selected word line Sel.WL, the potential of the adjacent unselected word lines Unsel.WL in the floating state is increased by the capacitor coupling phenomenon, Can be changed not only by the potential profile (Vch (x)) but also by the read voltage VREAD of the selected word line (Sel.WL).

Normally, since the read voltage VREAD is smaller than the pass voltage VPASS_READ, it is necessary to compensate the potential of the adjacent unselected word lines Unsel.WL which is decreased by the read voltage VREAD.

Second, by looking at the channel potential profile (V_ch (x)) of FIGS. 4d and 4e, it can be seen that by floating the unselected word lines Unsel.WL, A strong electric field is generated in adjacent sub-channels of the unselected word lines (Unsel.WL). Since the hot carriers generated by the strong electric field are likely to be injected into the memory cells of the selected word line (Sel.WL) and the adjacent unselected word lines (Unsel.WL), the unselected word lines (Unsel.WL) It is necessary to adjust the electric potential of the electric field to suitably control the electric field.

Referring to FIG. 5B, in the gate bias set-up period, peripheral circuits (120 to 16 in FIG. 1) are connected to the selected word line (Sel.WL) before the unselected word lines (Unsel.WL1 Unsel.WL2) The first pass voltage VPASS_READ1 is applied to the non-selected word lines Unsel.WL1 not adjacent to the selected word line Unsel.WL1 and the second pass voltage VPSS_READ2 is applied to the unselected word lines Unsel.WL2 adjacent to the selected word line Sel.WL, (VPASS_READ2).

The second pass voltage VPASS_READ2 is input in accordance with the read voltage VREAD.

Normally, VPASS_READ2 is input to VPASS_READ1 + alpha * (VPASS_READ1-VREAD) ± beta level considering capacitor coupling with the selected word line (Sel.WL), alpha can be adjusted from 0 to 1.0 level, It can be added or subtracted by beta to prevent carrier.

Although the same pass voltage VPASS_READ2 is applied to the selected word line Sel.WL and the non-selected word lines Unsel.WL2 adjacent to the selected word line Sel.WL, Voltages may be applied.

The non-selected word line Unsel.WL adjacent to the direction of the common source line CSL and the channel potential profile V_ch (x) in the selected word line Sel.WL of FIGS. It can be seen that the channel potential of the adjacent unselected word line Unsel.WL in the direction of the bit line BL is different. Therefore, it is necessary to compensate the potential of the adjacent unselected word lines (Unsel.WL).

Referring to FIG. 5C, peripheral circuits (120 to 16 in FIG. 1) in the gate bias set-up period before the unselected word lines Unsel.WL1 to Unsel.WL3 are set to the floating state are selected by the selected word line Sel.WL, And the second pass voltage VPASS_READ2 is applied to the unselected word line Unsel.WL2 adjacent to the direction of the bit line BL by applying the first pass voltage VPASS_READ1 to the non-selected word lines Unsel.WL1 not adjacent to the bit line BL, And applies the third pass voltage VPASS_READ3 to the unselected word line Unsel.WL3 adjacent to the direction of the common source line CSL.

The second pass voltage VPASS_READ2 of the unselected word line Unsel.WL2 in the direction of the bit line BL is input in accordance with the read voltage VREAD and the bit line bias VBL.

Normally, VPASS_READ2 is input at VPASS_READ1 + alpha * (VPASS_READ1-VREAD) ± beta + gamma * VBL level considering the capacitor coupling between the selected word line (Sel.WL) and the channel, . In addition, it is possible to add / subtract by beta to prevent hot carriers, and gamma can be adjusted at the level of -0.5 ~ 0.5 as an empirical constant.

The third pass voltage VPASS_READ3 is input in accordance with the read voltage VREAD.

Normally, VPASS_READ3 is input to VPASS_READ1 + alpha * (VPASS_READ1-VREAD) ± beta level considering the capacitor coupling with the selected word line (Sel.WL), alpha can be adjusted at 0 ~ 1.0 level, It can be added or subtracted by beta to prevent carrier.

Although the same pass voltage VPASS_READ1 is applied to the selected word line Sel.WL and non-selected word lines Unsel.WL1 that are not adjacent to the selected word line Sel.WL, The different pass voltages may be applied depending on the position of the pixel UnLL.WL1.

The channel potential profile (Vch (x)) in the selected word line (Sel.WL) of Figures 4d and 4e can be viewed as a non-adjacent non-selected word line in the direction of the common source line (CSL) ) Is lower than the channel potential of the non-adjacent non-selected word line Unsel.WL in the direction of the bit line BL.

Therefore, in order to slightly reduce the read disturb due to the pass voltage VPASS_READ of the non-selected word line Unsel.WL that is not adjacent to each other, Pass voltages.

Referring to FIG. 5D, peripheral circuits (120 to 16 in FIG. 1) in the gate bias set-up period before the unselected word lines (Unsel.WL1 to Unsel.WL4) are set to the floating state are connected to the selected word line (Sel.WL) The first pass voltage VPASS_READ1 is applied to the non-selected word lines Unsel.WL1 which are not adjacent to each other in the direction of the bit line BL and the adjacent non-selected word lines Unsel.WL1 in the direction of the bit line BL. The second pass voltage VPASS_READ2 is applied to the common source line CS2 and the third pass voltage VPASS_READ3 is applied to the adjacent unselected word line Unsel.WL3 in the common source line CSL direction, The fourth pass voltage VPASS_READ4 can be applied to the unselected word lines Unsel.WL4 of the direction.

The fourth pass voltage VPASS_READ4 of the non-selected word line Unsel.WL in the direction of the common source line CSL is changed in accordance with the bit line bias VBL.

Normally, VPASS_READ4 is input at the level of (VPASS_READ1 + gamma * VBL), taking into account the capacitor coupling between the selected word line (Sel.WL) and the channel, where gamma is preferably from -1.0 to 0.

Although the non-selected word lines Unsel.WL1 and Unsel.WL4 that are not adjacent to the selected word line Sel.WL are all set to the floating state in the above description, the non-selected word lines Sel.WL, The non-selected word lines Unsel.WL1 and Unsel.WL4 can be selectively set to the floating state according to the positions of the word lines Unsel.WL1 and Unsel.WL4.

Looking at the channel potential profile (Vch (x)) of Figures 4d and 4e, it can be seen that most of the voltage drops occur in the selected word line (Sel.WL) and the non-adjacent non-selected word in the common source line It can be seen that the line Unsel.WL4 is close to the source voltage (typically 0V).

Therefore, it is possible to take an operation of fixedly supplying the voltage only to the non-adjacent non-selected word line Unsel.WL4 in the common source line CSL direction.

The fourth pass voltage VPASS_READ4 of the unselected unselected word line Unsel.WL4 in the common source line CSL direction is fixedly input in accordance with the bit line bias VBL.

Normally, VPASS_READ4 is input at the level of (VPASS_READ1 + gamma * VBL), where gamma is preferably from -1.0 to +1.0.

Referring to FIG. 5E, the gate bias setup period may be set as shown in FIG. 5D. In the sensing bias setup period, peripheral circuits (120 to 160 in FIG. 1) are connected to selected word lines (Sel.WL) and non-adjacent non-selected word lines (Unsel.WL1) in the bit line (BL) Selected word line Unsel.WL2 in the direction of the common source line CS and the adjacent unselected word line Unsel.WL3 in the direction of the common source line CSL are set to the floating state and the adjacent non- The non-selected word lines Unsel.WL4 can continue to apply the fourth pass voltage VPASS_READ4.

Although the selected word line Sel.WL and the non-selected word lines Unsel.WL2 and Unsel.WL3 adjacent to the selected word line Sel.WL are all set to the floating state, the selected word line Sel.WL and the adjacent unselected word lines Unsel.WL2, and Unsel.WL3 may be selectively set to the floating state according to the positions of the non-selected word lines Unsel.WL2 and Unsel.WL3.

4D and 4e, it can be seen that most of the voltage drops occur in the selected word line Sel.WL and are not non-selected in the direction of the common source line CSL It can be seen that the adjacent unselected word line Unsel.WL3 in the direction of the word lines Unsel.WL4 and the common source line CSL is close to the source voltage (generally 0V).

Therefore, a voltage is fixedly applied to the unselected word lines Unsel.WL4 not adjacent in the direction of the common source line CSL as well as the adjacent unselected word lines Unsel.WL3 in the direction of the common source line CSL Can be taken.

The third pass voltage VPASS_READ3 of the adjacent unselected word line Unsel.WL3 in the direction of the common source line CSL is changed in accordance with the bit line voltage VBL and input fixedly.

Normally, VPASS_READ3 is entered at the (VPASS_READ1 + gamma * VBL) level, where gamma can have a value from -1.0 to +1.0.

Referring to FIG. 5F, the gate bias setup period may be set as shown in FIG. 5D. In the sensing bias setup period, the peripheral circuits 120 to 160 of FIG. 1 select unselected word lines (Unsel.WL1, Unsel.WL2) adjacent in the direction of the selected word line (Sel.WL) and the bit line (BL) The precharge voltage VBL can be applied to the bit line BL in a floating state.

At this time, the peripheral circuits 120 to 160 of FIG. 1 sequentially apply the selected voltage to the unselected word lines Unsel.WL3 and Unsel.WL4 in the direction of the selected word line Sel.WL and the common source line CSL, (VPASS_READ3, VPASS_READ4).

Referring to FIG. 5G, when a pass voltage VPASS_READ is applied to the unselected word lines Unsel.WL in the gate bias set-up period, a positive voltage is applied to the select lines DSL and SSL, All the select transistors can be turned on. In the sensing bias setup period, the ground voltage is applied to the select lines DSL and SSL while the precharge voltage VBL is applied to the bit line BL and the non-selected word lines Unsel.WL are set to the floating state So that the drain select transistor and the source select transistor can be turned off. Subsequently, in the sensing period, a positive voltage is applied to the select lines DSL and SSL while the precharge voltage VBL is applied to the bit line BL and the non-selected word lines Unsel.WL are set to the floating state To turn on the drain select transistor and the source select transistor

The unselected word lines Unsel.WL may be selectively floating according to the method described in Figs. 5B through 5F. In addition, the pass voltage applied to the unselected word lines Unsel.WL may be set according to the method described in Figs. 5B through 5F.

As described above, when applying the pass voltage VPASS_READ to the selected word lines Unsel.WL in the gate bias set-up period, by turning on all the select transistors, the precharge time of the word lines can be shortened to improve the read speed . Further, by turning off all the select transistors in the sensing bias set-up period, the lead stress due to the read bias can be minimized.

By applying pass voltages to non-selected word lines under the above-described conditions and applying a pre-charge voltage to the bit lines in a state in which a part or all of the non-selected word lines are floating, sufficient operation current can be ensured and data input / Can be improved.

6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 6, a memory system 600 according to an embodiment of the present invention includes a non-volatile memory device 620 and a memory controller 610.

The nonvolatile memory device 620 may be composed of the above-described semiconductor memory device. The memory controller 610 is configured to control the non-volatile memory device 620 in a normal operation mode such as a program loop, a read operation, or an erase loop.

May be provided as a memory card or a solid state disk (SSD) by the combination of the nonvolatile memory device 620 and the memory controller 610. The SRAM 611 is used as an operation memory of the processing unit 612. [ The host interface 613 has a data exchange protocol of a host connected to the memory system 600. The error correction block 614 detects and corrects errors included in data read from the nonvolatile memory device 620. The memory interface 614 interfaces with the nonvolatile memory device 620 of the present invention. The processing unit 612 performs all the control operations for exchanging data of the memory controller 610.

Although it is not shown in the drawing, the memory system 600 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 620 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 600 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) which has been actively studied recently. In this case, the memory controller 610 is configured to communicate with an external (e.g., host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, will be.

7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above. For example, the technical features of the present invention described above can be applied to the original NAND flash memory device 700 as a fusion memory device.

The original NAND flash memory device 700 includes a host interface 710 for exchanging various information with devices using different protocols, a buffer RAM 720 for embedding codes for driving the memory devices or temporarily storing data A control unit 730 for controlling reading, programs, and all states in response to control signals and commands issued from the outside; data such as commands, addresses, and configurations for defining a system operating environment in the memory device; A register 740 to be stored, and a NAND flash cell array 750 constituted by an operation circuit including a nonvolatile memory cell and a page buffer. The memory array of the NAND flash cell array 750 can be applied to the memory array shown in FIG.

8, a computing system including a flash memory device 812 in accordance with the present invention is schematically illustrated.

A computing system 800 in accordance with the present invention includes a microprocessor 820 electrically coupled to a system bus 860, a RAM 830, a user interface 840, a modem 850 such as a baseband chipset, Memory system 810. When the computing system 800 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 800 will additionally be provided. Although it is not shown in the drawing, it is to be appreciated that the computing system 800 in accordance with the present invention may be further provided with application chipsets, camera image processors (CIS), mobile DRAMs, It is obvious to those who have acquired knowledge. The memory system 810 may comprise, for example, a solid state drive / disk (SSD) using nonvolatile memory to store data. Alternatively, the memory system 810 may be provided as a fusion flash memory (e.g., a one-NAND flash memory).

110: memory array 110 MB: memory block
ST: Memory string PAGE: Page
120: control circuit 130: voltage supply circuit
131: Voltage generation circuit 132: Low decoder
140: read / write circuit 150: column select circuit
160: Input / output circuit

Claims (20)

A memory block including memory cells connected between a bit line and a source line and operating according to voltages applied to word lines; And
A peripheral circuit configured to perform operations related to data input / output of the memory cells,
Wherein the peripheral circuit is configured to apply a pre-charge voltage to the bit line while the selected word line and adjacent word lines are set to a floating state.
The method according to claim 1,
Wherein the peripheral circuit is configured to apply a precharge voltage to the bit line when floating the adjacent word lines or after floating the adjacent word lines.
3. The method of claim 2,
Wherein the peripheral circuit is configured to apply the read voltage or the verify voltage to a selected word line after applying the pre-charge voltage to the bit line or after applying the pre-charge voltage to the bit line.
The method according to claim 1,
Wherein the peripheral circuit is configured to turn on a drain select transistor connected between the bit line and the memory cell before floating the adjacent word lines.
The method according to claim 1,
And the peripheral circuit is configured to float the adjacent word lines after applying a pass voltage to the word lines.
6. The method of claim 5,
And the peripheral circuit is configured to apply the pre-charge voltage to the bit line after applying the pass voltage to the word lines.
6. The method of claim 5,
And the peripheral circuit is configured to turn on a drain select transistor connected between the bit line and the memory cell when applying the pass voltage to the word lines.
The method according to claim 1,
Wherein the peripheral circuitry is configured to apply a read voltage or a verify voltage to the selected word line after floating the adjacent word lines or after floating the adjacent word lines.
9. The method of claim 8,
And the peripheral circuit is configured to apply the read voltage or the verify voltage after applying a pass voltage to the selected word line.
9. The method of claim 8,
And the peripheral circuit is configured to turn on a source select transistor that electrically connects the source line and the memory cell after applying the read voltage or the verify voltage to the selected word line.
The method according to claim 1,
And the peripheral circuit is configured to turn on a source select transistor that electrically connects the source line and the memory cell after floating the adjacent word lines.
The method of claim 1, wherein before the adjacent word lines are set to a floating state,
Wherein the peripheral circuit is configured to apply a first pass voltage to word lines not adjacent to the selected word line and to apply a second pass voltage to word lines adjacent to the selected word line.
The method of claim 1, wherein before the adjacent word lines are set to a floating state,
Wherein the peripheral circuit applies a first pass voltage to word lines not adjacent to the selected word line and applies a second pass voltage to a word line adjacent to the selected word line in one direction, And applying a third pass voltage to the adjacent word line in the direction of the first word line.
The method of claim 1, wherein before the adjacent word lines are set to a floating state,
The peripheral circuit applies a first pass voltage to word lines not adjacent to the selected word line in one direction and applies a second pass voltage to the selected word line and a word line adjacent in the one direction, A third pass voltage is applied to the word line adjacent to the word line and the other direction and a fourth pass voltage is applied to the word line not adjacent to the selected word line in the other direction.
15. The method of claim 14, wherein when the adjacent word lines are set to a floating state,
And the peripheral circuit is configured to set the selected word line and the word lines not adjacent to the selected word line in the one direction and the selected word line and the word lines not adjacent in the other direction to a floating state.
14. The method of claim 13, wherein when the adjacent word lines are set to a floating state,
And the peripheral circuit is configured to set the selected word line and the word lines not adjacent in the one direction to a floating state.
2. The method of claim 1, wherein when the adjacent word lines are set to a floating state,
And the peripheral circuit is configured to set the gate of the drain select transistor connected between the bit line and the memory cell to a floating state.
A memory block including memory cells connected between a bit line and a source line and operating according to voltages applied to word lines; And
A peripheral circuit configured to perform operations related to data input / output of the memory cells,
Wherein the peripheral circuit applies a precharge voltage to the bit line while applying a pass voltage to a selected word line and a word line adjacent to the bit line in a direction of the selected bit line and then setting the adjacent word line to a floating state, Device.
19. The method of claim 18,
The peripheral circuit turns on a drain select transistor connected between the bit line and the memory cell when the pass voltage is applied to the adjacent word line,
And the peripheral circuit is configured to set the gate of the drain select transistor to a floating state when the adjacent word line is set to a floating state.
A memory block including select transistors operating between the bit line and the source line and operating according to voltages applied to the select lines and memory cells operating according to voltages applied to the word lines; And
A peripheral circuit configured to perform operations related to data input / output of the memory cells,
The peripheral circuit turns on the select transistors when applying a pass voltage to non-selected word lines, turns on the select transistors while applying a pre-charge voltage to the bit lines and sets the non-selected word lines to a floating state. Off and then turns on the semiconductor memory device.

Images