KR20140118478A - Overall duty controller using DVI, and duty control method using the same - Google Patents

Abstract

The present invention relates to an overall duty controller using DVI, and a duty control method using the same. The present invention comprises: DVI receiver (2) which receives DVI data of a computer through DVI CH (1), and converts the received data into an RGB signal; and FPGA device (3) which stores the converted data in DDR SDRAM1 (4). The FPGA device (3) enables overall duty (static duty, 1/2 duty, 1/4 duty, 1/8 duty, 16 duty) to be coded into the FPGA Device (3) and selected in order to enable the overall duty to be set up using a single board. As a result, the overall duty (static duty, 1/2 duty, 1/4 duty, 1/8 duty, 16 duty) can be set up using a single board in order to unify models generated while producing and installing an electronic display board. Also, the present invention improves production issues by being equipped with the entire duty and automatically selecting a module; does not require lots of components; and eliminates various unnecessary elements in terms of production management and technology management.

Description

[0001] The present invention relates to an overall duty controller using DVI and a duty control method using the same,

[0001] The present invention relates to a full duty controller using DVI and a duty control method using the same. More specifically, the present invention relates to a duty controller having a duty (Duty, Duty, 1/8 Duty, and 16 Duty) to a single board, and a duty control method using the same.

BACKGROUND ART In general, an electric signboard or an electronic signboard is an electronic application display system for displaying various kinds of information in a state of visible stop or moving picture. Such electric signboards are widely used for advertisement, commercial, stadium, multi-purpose, traffic signal, information and message, and their size and application system may be different depending on the application, object or location.

In other words, the advertisement commercial is used for indoor or outdoor use, color or dual color is mainly used, and the stadium is applied to main stadium, racetrack, soccer field, baseball field or swimming pool and the multi-purpose is for conference hall, small theater, And traffic signal is used for railway, which has a platform, ticket gate, waiting room, a passage, etc., and road including a city road, a highway or an induction lamp.

Also, the latest news from the stock market, stock market, stock market, airport for the arrival or departure, environmental information for environmental pollution, factories, office, And for information and messages used for publicity and information transmission by governments and local governments.

Such a display board can be classified into a mobile type that can be mounted on a truck or a container for various events, and a block type that can be used as a substitute for a show or a multi-cube.

Most electronic application display system companies use industrial computers or industrial embedded systems to implement high resolution LED display devices, PDP, and LCD display devices. When implementing small LED display devices, LED display devices are implemented using microcomputer boards have.

When an LED display device is implemented using an industrial computer, a signal is used from a VGA card or a DVI card of a computer, so a digital signal is converted into an LED signal through an image conversion device.

Accordingly, image quality is deteriorated in a process of converting a VGA signal or a DVI signal to a digital signal using a computer and an image conversion device, and the image is converted into an LED signal through a computer, a VGA card, a DVI card, The image quality is deteriorated, the system becomes complicated, and the system becomes large and the cost increases.

In addition, it is necessary to produce individual boards for different duties (Static Duty, ½ Duty, ¼ Duty, 1/8 Duty, and 16 Duty) for each model while producing and installing electric signboards, Is also occurring.

[Related Technical Literature]

1. SYSTEM-ON-CHIP BASED LED SIGNAL PROCESSING APPARATUS (Patent Application No. 10-2006-0100927)

2. CLOCK GENERATING METHOD AND DATA TRANSMITTING METHOD IN MULTIMEDIA SOURCES (Patent Application No. 10-2008-0101611)

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an image forming apparatus and a method of manufacturing the same, in which a total duty (Static Duty, ½ Duty, 1/4 Duty, And a duty control method using the entire duty controller using the DVI.

In addition, the present invention can improve productive matters by automatically selecting modules by mounting all the duties, and does not require many parts, and DVI for eliminating a lot of unnecessary space in terms of production management and technical management And a duty control method using the same.

However, the objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a full duty controller using DVI according to an embodiment of the present invention includes a DVI receiver for receiving DVI data of a computer through a DVI CH and converting input data into RGB signals; And an FPGA Device for storing the converted data in the DDR SDRAM1; And the FPGA Device can code the entire duty in the FPGA Device so that the overall duty (Static Duty, Duty Duty, Duty, 1/8 Duty, and 16 Duty) can be set as one board .

In the overall duty controller using DVI according to another embodiment of the present invention, the DVI receiver receives DVI input data, Red data, Green data, Blue data, and Clock data, as TMDS signals of international standards, The output of the 24-bit image is performed in RGB format, which is an image value.

In the overall duty controller using DVI according to another embodiment of the present invention, the FPGA device 3 receives and processes V-Sync, H-Sync, Data Enable, and Clock signals, And stores the read data in the DDR SDRAM 1, reads the stored data one frame after, and outputs the shifted data to the output.

According to an aspect of the present invention, there is provided a duty control method using an entire duty controller using DVI, the method comprising: A first step of analyzing a clock and data fed back from the module by the signal analysis circuit, analyzing the duty and delivering the analysis data to the next step; A second step of selecting each duty (1/1 Duty, ½ Duty, ¼ Duty, 1/8 Duty, 1/16 Duty) to be converted into a form suitable for duty by using the analysis data, ; A third step of performing position setting and actual data generation and output at the same time as the second step and transmitting the output to the next step; And a fourth step of performing a function of generating output data to the electric panel module by performing Data, Clock, Out Enable, and Latch. And a control unit.

In the duty control method using the entire duty controller using DVI according to another embodiment of the present invention, the position setting of the third step sets a position to be displayed on the electric panel module, and before the fourth step, Processing the brightness adjustment of the step; And further comprising:

The duty control method using the entire duty controller using DVI according to another embodiment of the present invention may further include an output OUT for performing processing on data before entering the buffer, A fifth step of performing a process; Is further preferably performed.

The entire duty controller using DVI according to the embodiment of the present invention and the duty control method using the DVI according to the embodiment of the present invention may be configured to perform a total duty (Static Duty, Duty, 1/4 duty, 1/8 Duty, 16 Duty) can be set on one board.

In addition, the entire duty controller using DVI according to another embodiment of the present invention and the duty control method using the same can perform product improvement by automatically selecting modules by mounting all the duties, And it is possible to eliminate a lot of unnecessary space in terms of production management and technical management.

1 is a view illustrating a duty controller using DVI according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a duty control method performed in the FPGA device of FIG. 1. Referring to FIG.
3 is a circuit diagram illustrating a DVI receiver input description for the DVI receiver of FIG.
4 is a circuit diagram for explaining an ARM9 Core (MCU) description corresponding to the MCU in FIG.
5 and 6, a description will be given of a duty controller using DVI.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the present specification, when any one element 'transmits' data or signals to another element, the element can transmit the data or signal directly to the other element, and through at least one other element Data or signal can be transmitted to another component.

1 is a view illustrating a duty controller using DVI according to an embodiment of the present invention. Referring to FIG. 1, a duty controller using DVI includes a DVI CH 1, a DVI receiver 2, an FPGA device 3, a DDR SDRAM 1 4, an MCU 5, a power supply 6, a line buffer (Duty, ¼ Duty, 1/8 Duty, and 16 Duty) for the purpose of unifying the models generated while manufacturing and installing the electronic signboard by including the output module ) Can be set as a single board. To do this, the duty controller using DVI allows coding the entire duty cycle in the FPGA Device (3). Of course, there is a disadvantage that VHDL Coding data to be loaded here is increased, but it is for unification of the board, and it is improved from the administrative management side as well as management side.

DVI receives DVI from computer (1) and converts the data into RGB signal through DVI receiver (2). Input signal is stored in DDR SDRAM1 (4) through FPGA Device (3). After reading the stored data one frame later, it connects to the part set in duty and outputs it.

In the present invention, the main processing function is handled in the FPGA device 3, and the processed data is transmitted to the MCU 5 to notify whether the currently used function is to process the correct data.

Detailed description of each component will be given below.

DVI Receiver (2) receives DVI input data (Red data, Green data, Blue data, Clock data) as TMDS signal of international standard. Of course, when input as a pair signal, it performs 24bit output in RGB format which is the image value of DVI Receiver (2). In this case, the data does not have a function for gamma and brightness, and the FPGA device 3 receives and processes the data. Although various functions are provided here, it is desirable to simply convert the TMDS signal into 24 bits (RGB Data).

When the FPGA device 3 is converted into 24 bit RGB data for the TMDS data by the DVI receiver 2, the input data is stored in the DDR SDRAM1 (4).

The FPGA device 3 receives signals such as V-Sync, H-Sync, Data Enable, and Clock as well as the above-described data processing.

More specifically, the FPGA device 3 converts the RGB data into the selected gamma value, stores it in the DDR SDRAM1 (4), reads the stored data one frame after, and outputs the shift to the output.

To further illustrate, the FPGA Device (3) should be able to adjust the brightness according to the external brightness by adjusting the brightness using CDS or the optical sensor. The brightness is usually set to a few days . After processing the above-described functions, the FPGA device 3 processes the above functions, and then transmits information related to the MCU 5 to check the operation status and the like from time to time. The FPGA device (3) is designed to be 1024x768, which is commonly used for resolution, but it is designed to be able to select resolution.

The scaler function by the FPGA Device (3) is actually a lot of function, but there are many cases where a controller is used with a scaler separately.

However, the FPGA device (3) according to the present invention is designed so that the scaler is also designated and processed by the software. However, since the FPGA device (3) can prevent the distortion or other discoloration due to a similar size to some extent, it is preferable to limit the video and text.

In the DDR SDRAM1 (4), the SDRAM1 (4) is capable of storing and reading image data, reading and writing data at a high speed, and has characteristics in data processing.

The power supply 6, the line buffer 7, the output module 8, and the LED module 9 will not be described here because they are conventional components irrespective of the gist of the present invention.

2 is a diagram illustrating a duty control method performed in the FPGA device 3 in FIG. First, in step S1, a signal analysis circuit is used. That is, the signal analysis circuit in the FPGA device 3 analyzes the clock and data fed back from the module, analyzes the duty, and transmits the data to the next step S2.

Next, automatic duty selection (1/1 duty, ½ duty, ¼ duty, 1/8 duty, 1/16 duty) is performed in step S2. That is, the automatic duty selection of the step S2 is switched to a form suitable for the duty by using the data analyzed in the step S1, and each duty is selected and the operation is shifted to the next step S6. (Step S7) and the actual data are generated and outputted (steps S2 to S5) at the same time as the process of step S2 and then transferred to the next step S6.

In step S3, RGB Data 24 Bits, V-Sync, H-Sync, Pixel Clock, and Data Enable are performed. That is, in step S3, the image data is received, the signal is separated, and the process proceeds to the next step S4.

In step S4, Gamma conversion is performed. The Gamma conversion in step S4 can select the image data from 2.0 to 3.0 to convert the gamma value to match the image of the LED, and the data is converted and transferred to the next step S5.

Next, DDRAM Write & Read is performed in step S5. That is, the DDRRAM reading and storing in step S5 performs a function of reading and storing in the memory.

When both steps S2 and S5 are completed, the process goes to step S6 where Data, Clock, Out Enable, and Latch are performed. That is, the step S6 performs a function of generating output data to the electric sign board module.

On the other hand, apart from steps S1 to S6, positioning is performed in step S7 before step S2. That is, in step S7, a function to set the position to be displayed is performed.

Next, brightness adjustment is performed in step S8. That is, the brightness adjustment function of step S8 is processed in 10 steps.

An output (OUT) process of step S9 is performed, and processing for data before entering the buffer inputted to the electric panel module is performed.

Through the above process, the FPGA device has DVI receiver 8bit to 12bit data input function and memory function, Gamma 2.0 to 3.0 data process function, DMA (Direct Memory Access) processing function, All Duty VHDL Coding, (Light) sensor detection and brightness adjustment, resolution 1024x768, support for 1080x1024, scaler mounting and control functions.

3 is a circuit diagram illustrating a DVI receiver input description for the DVI receiver 2 of FIG. Referring to FIG. 3, first, the DVI receiver 2 supports True-Color 24 bit / pixel, 16.7M color at 1 or 2 pixel per clock. Second, DVI Receiver (2) supports Supports pixel rates up to 165MHZ (Including 1080p and WUXGA at 60HZ). Third, DVI Receiver (2) supports Digital Visual Interface (DVI) specification compliant. Fourth, DVI Receiver (2) supports Reduced ground bounce using time-staggered pixel outputs. Fifth, DVI receiver (2) supports low noise and good power dissipation using TI power PAD packaging.

FIG. 4 is a circuit diagram for explaining the ARM9 Core (MCU) description corresponding to the MCU 5 in FIG. 4, the MCU 5 includes a 2-ch IIS controller (1-ch support of Dolby 5.1 channel) and a combined PCM and AC97 I / F function, a 2-ch SD host controller v2.0 (SDHC) 1-port USB host v1.1 full speed function, 1-port USB dev v2.0 high speed function, 4-ch PWM timers & 1-ch internal timers, Real -time clock & watchdog timer function, 2 PLLs with on-chip clock generator function, Power modes (Normal, Idle, Stop & Deep Stop, Sleep and Power-off), MtCMOS technology incorporated function, touch screen interface, 32KB internal ROM / 64KB internal SRAM, 128-bit e-Fuse for security and 65nm low-power technology.

In addition, the MCU 5 is a dual-port external memory controller (DRAM / ROM controller and chip select logic), 32 KB internal ROM and 64 KB internal RAM allows booting from 4KB 8-bit MLC NAND, One NAND and moviNAND flash.

In addition, MCU 5 features x16 DDR2 support, Deep-stop mode, 2D hardware support, 2 high-speed SPIs, LCD controller with LCD-dedicated DMA, camera controller, 2D graphics accelerator -ch DMAs with external request pins, 4-ch UART with IrDA 1.0, 2-ch HS SPI, CF + and ATA I / F, and 2-ch multi-master IIC.

The MCU 5 controls the communication functions (RS232, RS485, TCP / IP), the output signals (Out Enable, Latch, Data, Clock) using the functions of the duty controller using DVI, Monitoring function, DVI Receiver & FPGA in / out signal processing function, DVI DDC signal processing function, and controller board function status notification function.

5 and 6, a description will be given of a duty controller using DVI. First, the DVI-based duty controller maintains the existing complexity of the duty, while the additional matter automatically recognizes the module (RGB LED) function, and unifies the controller as one model to improve the unification of parts and productivity. In addition, the duty controller using DVI has the advantage of realizing unification of production enhancement. That is, the details will be described with reference to FIGS. 5 and 6. FIG. 5 is a timing diagram for a general LED Module semiconductor. However, existing data is only output, and there is no monitoring or inspection function. Because it is this part, you can not know which module is the output. We want to add a function that can automatically process the inspection function of this part to the duty controller using DVI. 6 shows a 16 duty cycle performed by a duty controller using DVI. For the explanation, if data input is given to the clock for the first time, the data output is output from the LED Driver Chip on the LED Module (9) functioning as a 16 channel shift register (Data Output shows High Level after 16 clocks.

This is the most important and most basic of the duty. Therefore, it is a function to grasp how many duties are using the data output (Data Output). Then, 8 Duty shows High level after 32 clocks. So, to distinguish between three colors or full colors, you need to check how many data inputs you have.

As a supplementary description, the technical aspects of the present invention are as described above, and all the duties are mounted so that the modules can be automatically selected to improve the productive matters. Also, It is possible to obtain the effect of eliminating a lot of unnecessary space in terms of technology management.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and also implemented in the form of a carrier wave (for example, transmission over the Internet) .

The computer readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers skilled in the art to which the present invention pertains.

As described above, preferred embodiments of the present invention have been disclosed in the present specification and drawings, and although specific terms have been used, they have been used only in a general sense to easily describe the technical contents of the present invention and to facilitate understanding of the invention , And are not intended to limit the scope of the present invention. It is to be understood by those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

1: DVI CH
2: DVI Receiver
3: FPGA Device
4: DDR SDRAM1
5: MCU
6: Power Supply
7: Line Buffer
8: Output
9: LED Module

Claims (6)

A DVI receiver 2 for receiving DVI data of the computer through the DVI CH 1 and converting the input data into an RGB signal; And
An FPGA device (3) for storing the converted data in the DDR SDRAM1 (4); / RTI >
The FPGA device 3 may code the entire duty in the FPGA device 3 so as to set the overall duty (Static Duty, Duty, Duty, 1/8 Duty, and 16 Duty) Wherein the controller is configured to control the duty of the DVI controller.
The method according to claim 1,
The DVI receiver (2)
And outputs 24-bit output in the form of RGB, which is an image value when inputted as a pair signal, after inputting DVI input data (Red data, Green data, Blue data, and Clock data) Used full duty controller.
The method according to claim 1,
The FPGA device (3)
V-Sync, H-Sync, Data Enable, and Clock signals,
Converts the RGB data into a selected gamma value, stores the converted gamma value in the DDR SDRAM1 (4), reads the stored data one frame after, and outputs the shifted output to the output.
In a duty control method performed on an FPGA device (3) of a full duty controller using DVI,
A signal analysis circuit in the FPGA device (3) analyzes the clock and data fed back from the module, analyzes the duty, and transmits analysis data to the next step;
A second step of selecting each duty (1/1 Duty, ½ Duty, ¼ Duty, 1/8 Duty, 1/16 Duty) to be converted into a form suitable for duty by using the analysis data, ;
A third step of performing position setting and actual data generation and output at the same time as the second step and transmitting the output to the next step; And
A fourth step of performing a function of generating output data to the electric panel module by performing Data, Clock, Out Enable, and Latch; And a duty control method using the entire duty controller using the DVI.
5. The method of claim 4,
The position setting of the third step may include:
Set the position to display on the electric panel module,
Prior to the fourth step,
Processing brightness adjustment in ten steps; And a duty controller for controlling duty control using the entire duty controller using DVI.
5. The method of claim 4,
After the fourth step,
A fifth step of performing an output (OUT) process of performing processing on data before entering the buffer input to the electric sign board module; And a duty controller for controlling duty control using the entire duty controller using DVI.

Images