KR20140111986A - Apparatus and method for processing alternately configured longest prefix match tables - Google Patents

Abstract

A network switch includes a memory configurable to store alternate table representations of individual tries in a hierarchy of tries. A prefix table processor accesses the alternate table representations of the individual tries in parallel using an input network address, and searches for the longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match is selected from the local prefix matches. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses the next hop index table in the memory using the next hop index base address and the offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.

Description

[0001] APPARATUS AND METHOD FOR PROCESSING ALTERNATELY CONFIGURED LONGEST PREFIX MATCH TABLES [0002]

Cross-reference to related application

This application claims priority to U.S. Provisional Application No. 61 / 778,293, filed March 12, 2013, the content of which is incorporated herein by reference.

The present invention is generally directed to processing traffic in a computer network, and more particularly, the present invention is directed to network switches having longest prefix match tables configured alternately.

Figure 1 illustrates a longest prefix matching processor 100 used in accordance with the prior art. The longest prefix matching processor 100 includes a search engine 102 for looking up an entry in the forwarding table 104. Each entry in the forwarding table has an associated switch identifier, which represents the next destination (hop) for the network packet.

2 illustrates a simplified version of the forwarding table 200 of the prior art. The forwarding table has a prefix column with a set of entries and a next hop column with a designated switch identifier. Each prefix entry is a segment of the network address. The asterisk * specifies the "do not care" state. If there is no prefix match, the next hop is designated as switch "A ". It is desirable to obtain a match with the longest prefix because it represents the most specific path to the target machine.

FIG. 3 illustrates a packet 300 received by a switch 302 having a longest prefix matching processor 100. This longest prefix matching processor creates a hop to another machine, such as switch A, C or E, or machine B, D, F or G.

Figure 4 illustrates a binary tree or trie. The top of this figure shows a triangle 400, which is a simplified representation of the trie 400 shown at the bottom of this figure. The trie 400 has different paths represented by 1 and 0, where 0 represents the path to the left and 1 represents the path to the right. Using this technique, any path in the trie can be designated with digital values. The lower portion of the trie 400 has four leaf nodes branching to eight destinations (0) to (7) as shown. The path to destination 0 is represented as 000 because three left branches are used to reach this destination. The path to the destination 3 is represented as 011 because one left branch 0 and the next two right branches 11 are used to arrive at this location. Thus, each path can be specified by binary values. Trie 400 is said to have three node layers and thus to have three strides.

Figure 5 illustrates that the trie 400 may be in an arbitrarily complex hierarchical relationship with a number of other trials. For example, the trie 400 may be considered as level 0 for the eight trials 400_1 through 400_8 at level one. This triage may proceed to any number of levels as shown in FIG. Each trie can have a different size. Thus, arbitrarily long path expressions can be defined through such a structure.

FIG. 6 illustrates that each node of trie 600 may have a specified number. In this example, the nodes are numbered from 1 to 7 as shown.

FIG. 7 illustrates a scenario in which the next hop information resides in the black nodes 5,7. The path to the node 5 may be represented by a binary number of 01 and the path to the node 7 may be represented by the binary number 11. It will be appreciated with reference to FIG. 5 that the node path can be expressed as a long binary value through the multiple levels and the resulting path to a particular node.

In view of the foregoing, there is a continuing need to provide improved techniques for identifying longest prefix matches.

The network switch includes a memory configured to store alternate table representations of individual trials in a hierarchy of tries. The prefix table processor accesses the alternate table representations of the individual trie in parallel using the input network address and searches for the longest prefix match in each alternate table expression to obtain local prefix matches. The longest prefix match is selected from the local prefix matches. The longest prefix match has an associated next hop index base address and offset value. The next hop index processor accesses the next hop index table in the memory using the next hop index base address and offset value to obtain the next hop table pointer. The next hop processor uses the next hop table pointer to access the next hop table in the memory to obtain the destination network address.

The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.
Figure 1 illustrates a longest prefix matching processor of the prior art.
Figure 2 illustrates a prior art forwarding table.
Figure 3 illustrates a switch having a longest prefix matching processor for routing packets to any number of switches or machines.
Figure 4 illustrates a prior art binary tree.
Figure 5 illustrates a nested configuration of binary trees with arbitrarily complex paths.
Figure 6 illustrates node numbers used in accordance with an embodiment of the present invention.
Figure 7 illustrates a binary tree with the next hop information at the selected node.
8 illustrates a sparse mode table configuration used in accordance with an embodiment of the present invention.
Figure 9 illustrates a bitmap mode table configuration used in accordance with an embodiment of the present invention.
Figure 10 illustrates a leaf-push mode table configuration used in accordance with an embodiment of the present invention.
Figure 11 illustrates the next hop index table used in accordance with an embodiment of the present invention.
Figure 12 illustrates the next hop table used in accordance with an embodiment of the present invention.
Figure 13 illustrates packet processing operations performed in accordance with an embodiment of the present invention.
Figure 14 illustrates the processing components used in accordance with an embodiment of the present invention.
Like numbers refer to like elements throughout the several views of the drawings.

The present invention is a longest prefix matching processor incorporated in a switch. The longest prefix matching processor uses alternate longest prefix matching tables that can be optimized for different longest prefix matching search schemes and memory optimization schemes. A single longest prefix matching table is shown in FIG. The first column of this table specifies the packet type, in this case IPV4. Advantageously, the IPV4 and IPV6 packet types can be efficiently stored in a single table. The next column specifies the storage mode, in this case the sparse mode. Sparse mode achieves a large stride in individual trials. That is, the sparse mode implements processing for configurations where the individual trials are large. The next column specifies the branch length. The branch length is an indicator of the length of the path from the root node of the hierarchical trie to the arbitrary root node of the individual trie, such as any trie (also referred to as a subtree) in FIG. Stride specifies the size of the trie such as 2 ^strides . In this example, the stride is 5, 2 ^5, or 32. The next column is the next hop index base address. The present invention uses the next hop index for reference to the next hop table. This ensures maximum flexibility in configuring memory resources. The next column in this table is the same branch ID as the binary representation of the path through the tree, as described above. The last column of FIG. 8 specifies the triode IDs having the next hop information. FIG. 7 shows an example of corresponding node IDs having tri node and next hop information. The first four fields of Figure 8 have a fixed width. The remaining two fields have a variable width.

Figure 9 illustrates an alternate configuration for a prefix matching table. The first field of this table is the packet type. The next field specifies the bitmap mode. The next field specifies the branch length as described above. The next field specifies the stride. In bitmap mode, all the nodes for the triplets of the 5 strides are stored in a 2 ⁵ -1 or 31 bit array. The next two fields are the next hop index (NHI) base address and the branch ID. The branch ID specifies the branch path as described above. The NHI base address specifies the base position corresponding to the least significant bit of the tri-bit map, which is displayed as 1. Other nodes have their pointers to the NHI table incremented from the base location. For example, if the base position is zero, the fifth bit marked as 1 will be incremented 4 entries from the base position. The last field is a tri-bit map. In this example, the tri-bit map is a 31-bit map. This bitmap specifies different locations within a particular trie with next hop information.

Figure 10 illustrates an alternate configuration for a prefix matching table. The second field of this table specifies a leaf-push mode. In the leaf-push mode, only the lowest nodes in the array will appear. For example, referring to FIG. 6, only nodes 4,5,6,7 will appear in this array. If the other nodes in FIG. 6 have next hop information, then various techniques such as controlled prefix expansion will be used to position this information in the lowest nodes. The NHI table needs to perform corresponding replication in this case. This mode is particularly memory efficient when directly connected hosts typically have contiguous addresses and network addresses for such hosts are stored in the same table. This mode is also advantageous because all searches are terminated at the same level.

The table of FIG. 10 has a branch length field, a stride field, an NHI base address field, a branch ID field, and a trie bottom bitmap field. In the case of 5 strides, the entire bitmap has 2 ⁵ -1 or 31 bits, which results in a set of 16 base nodes. Thus, a 16 bit map can be used to specify the locations of these different nodes.

Figure 11 illustrates the next hop index table. The different entries in this table specify a pointer indicating the addition of the block size offset to the next hop table base location. This base position specifies the entry point in the table, and the block size specifies additional fields from the base position. The block size of the next hop table entries is used in ECMP (equal-cost multi-path) routing and advanced network routing techniques. Along with the IP address, each request to the longest prefix matching engine is accompanied by an ECMP hash value for path selection. The ECMP hash value may be greater than the available block size, so the final path selection is calculated as the sum of the ECMP hash value input to the next hop base address plus the modulo divided by the next hop block size. In one embodiment, 1024 paths are supported in the ECMP.

The NHI table size is a function of the trie configuration. This table size can be dynamically configured and optimized.

Figure 12 illustrates the next hop table. Each entry in this table specifies a hop to the destination machine.

Figure 13 illustrates processing operations performed in accordance with an embodiment of the present invention. An ingress network address (e.g., Internet Protocol address) 1300 is applied to prefix table 0 through prefix table N set, and some or all of these tables may be configured by software. Each prefix table includes a set of prefix entries, and each prefix entry specifies the path to the trie and the characteristics of this trie as discussed with reference to Figures 8-10. Using prefix table 0 1302 as an example, a software configured selection of bits of the ingress network address is applied 1304 to the hash function to map to the prefix table address. Advantageously, all matching is performed with hardware latency fixed. The prefix table memory is then read 1306 to obtain a subtree 0 (an individual trie in an arbitrarily complex hierarchical trie structure as shown in FIG. 5). The longest prefix match is performed in this subtree (1308). This processing is repeated throughout all the prefix tables 0 to N to produce local prefix matches. The results are processed to select the longest prefix match (1310). The NHI table is then read (1312), an access to the next hop table is made (1314), and a next hop is generated (1316).

FIG. 14 illustrates a longest prefix matching processor 1400 constructed in accordance with an embodiment of the present invention. Processor 1400 includes a prefix table processor 1402, which is a hardware resource configured to specify and subsequently access different longest prefix matching tables such as those of FIGS. 8-10. The tables reside in memory 1404, which can be a pool of SRAM resources. The prefix table processor 1402 coordinates the operations 1304-1310 of FIG. The next hop index processor 1406 is then used to access the next hop index table in memory 1404, and returns the base address and, if any, the offset to the next hop processor 1408. The next hop processor 1408 accesses the next hop table stored in the memory 1404, and then generates the next hop address as a result 1410. If prefix table processor 1402 has a trie miss or other error, an error or default result 1410 may be generated directly as indicated by arrow 1412. [

The foregoing description for the purpose of illustration has been made using specific nomenclature to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that these specific details are not required to practice the present invention. Accordingly, the foregoing description of specific embodiments of the invention has been presented to illustrate, but not to limit, the invention. They should not be construed as limiting the invention to the disclosed forms, but it is evident that many modifications and variations are possible in light of the above teaching. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art to which it pertains according to the various embodiments having various modifications as are suited to the particular use contemplated, . The following claims and their equivalents define the scope of the invention.

Claims (14)

As a network switch,
Memory, a prefix table processor, a next hop index processor, and a next hop processor,
Wherein the memory is configured to store alternate table representations of individual trials in a hierarchy of tries,
Wherein the prefix table processor comprises:
Accessing the alternate table representations of the individual trie in parallel using the input network address and searching for the longest prefix match in each alternated table expression to obtain local prefix matches,
Selecting the longest prefix match from the local prefix matches,
Wherein the longest prefix match has an associated next hop index base address and offset value,
Wherein the next hop index processor accesses the next hop index table in the memory using the next hop index base address and offset value to obtain a next hop table pointer,
Wherein the next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address,
Network switch.
The method according to claim 1,
Wherein the alternate table representations include a sparse mode representation identifying the selected tri nodes.
Network switch.
3. The method of claim 2,
Wherein the sparse mode representation comprises a branch identifier and a stride value.
Network switch.
The method according to claim 1,
Wherein the alternate table representations comprise a bitmap mode representation having a bitmap identifying the selected tri nodes,
Network switch.
5. The method of claim 4,
Wherein the bitmap mode representation comprises a branch identifier and a stride value.
Network switch.
The method according to claim 1,
Wherein the alternate table representations include a leaf-push mode representation identifying selected tri nodes at a bottom of the trie,
Network switch.
The method according to claim 6,
The leaf-push mode representation includes a branch identifier and a stride value.
Network switch.
The method according to claim 1,
Wherein the prefix table processor is a hardware resource having a deterministic lookup latency,
Network switch.
The method according to claim 1,
Wherein the alternate table representations comprise tables having different packet types in the same table,
Network switch.
10. The method of claim 9,
Wherein the different packet types include an IPV4 packet and an IPV6 packet.
Network switch.
The method according to claim 1,
Wherein the prefix table processor identifies the longest prefix match for the remote host and an exact match to the directly attached host,
Network switch.
The method according to claim 1,
Wherein the prefix table processor identifies the longest prefix match for the remote host and an exact match to the directly attached host in the same table,
Network switch.
The method according to claim 1,
Wherein the next hop index processor processes a block of next hop table entries to implement equal-cost multi-path routing,
Network switch.
14. The method of claim 13,
The block specifies 1024 paths,
Network switch.

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